arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi

   1 /*
   2  * Device Tree Source for the r8a7795 ES1.x SoC
   3  *
   4  * Copyright (C) 2015 Renesas Electronics Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include "r8a7795.dtsi"
  12
  13 &soc {
  14         xhci1: usb@ee040000 {
  15                 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";
  16                 reg = <0 0xee040000 0 0xc00>;
  17                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  18                 clocks = <&cpg CPG_MOD 327>;
  19                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  20                 resets = <&cpg 327>;
  21                 status = "disabled";
  22         };
  23
  24         /delete-node/ mmu@febe0000;
  25         /delete-node/ mmu@fe980000;
  26         /delete-node/ mmu@fd960000;
  27         /delete-node/ mmu@fd970000;
  28
  29         ipmmu_mp1: mmu@ec680000 {
  30                 compatible = "renesas,ipmmu-r8a7795";
  31                 reg = <0 0xec680000 0 0x1000>;
  32                 renesas,ipmmu-main = <&ipmmu_mm 5>;
  33                 #iommu-cells = <1>;
  34         };
  35
  36         ipmmu_sy: mmu@e7730000 {
  37                 compatible = "renesas,ipmmu-r8a7795";
  38                 reg = <0 0xe7730000 0 0x1000>;
  39                 renesas,ipmmu-main = <&ipmmu_mm 8>;
  40                 #iommu-cells = <1>;
  41                 status = "disabled";
  42         };
  43
  44         /delete-node/ usb-phy@ee0e0200;
  45         /delete-node/ usb@ee0e0100;
  46         /delete-node/ usb@ee0e0000;
  47         /delete-node/ usb@e659c000;
  48
  49         /delete-node/ dma-controller@e6460000;
  50         /delete-node/ dma-controller@e6470000;
  51
  52         fcpf2: fcp@fe952000 {
  53                 compatible = "renesas,fcpf";
  54                 reg = <0 0xfe952000 0 0x200>;
  55                 clocks = <&cpg CPG_MOD 613>;
  56                 power-domains = <&sysc R8A7795_PD_A3VP>;
  57                 resets = <&cpg 613>;
  58                 iommus = <&ipmmu_vp0 2>;
  59         };
  60
  61         vspi2: vsp@fe9c0000 {
  62                 compatible = "renesas,vsp2";
  63                 reg = <0 0xfe9c0000 0 0x8000>;
  64                 interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;
  65                 clocks = <&cpg CPG_MOD 629>;
  66                 power-domains = <&sysc R8A7795_PD_A3VP>;
  67                 resets = <&cpg 629>;
  68
  69                 renesas,fcp = <&fcpvi2>;
  70         };
  71
  72         fcpvi2: fcp@fe9cf000 {
  73                 compatible = "renesas,fcpv";
  74                 reg = <0 0xfe9cf000 0 0x200>;
  75                 clocks = <&cpg CPG_MOD 609>;
  76                 power-domains = <&sysc R8A7795_PD_A3VP>;
  77                 resets = <&cpg 609>;
  78                 iommus = <&ipmmu_vp0 10>;
  79         };
  80
  81         vspd3: vsp@fea38000 {
  82                 compatible = "renesas,vsp2";
  83                 reg = <0 0xfea38000 0 0x4000>;
  84                 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
  85                 clocks = <&cpg CPG_MOD 620>;
  86                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  87                 resets = <&cpg 620>;
  88
  89                 renesas,fcp = <&fcpvd3>;
  90         };
  91
  92         fcpvd3: fcp@fea3f000 {
  93                 compatible = "renesas,fcpv";
  94                 reg = <0 0xfea3f000 0 0x200>;
  95                 clocks = <&cpg CPG_MOD 600>;
  96                 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  97                 resets = <&cpg 600>;
  98                 iommus = <&ipmmu_vi0 11>;
  99         };
 100
 101         fdp1@fe948000 {
 102                 compatible = "renesas,fdp1";
 103                 reg = <0 0xfe948000 0 0x2400>;
 104                 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 105                 clocks = <&cpg CPG_MOD 117>;
 106                 power-domains = <&sysc R8A7795_PD_A3VP>;
 107                 resets = <&cpg 117>;
 108                 renesas,fcp = <&fcpf2>;
 109         };
 110 };
 111
 112 &gpio1 {
 113         gpio-ranges = <&pfc 0 32 28>;
 114 };
 115
 116 &ipmmu_vi0 {
 117         renesas,ipmmu-main = <&ipmmu_mm 11>;
 118 };
 119
 120 &ipmmu_vp0 {
 121         renesas,ipmmu-main = <&ipmmu_mm 12>;
 122 };
 123
 124 &ipmmu_vc0 {
 125         renesas,ipmmu-main = <&ipmmu_mm 9>;
 126 };
 127
 128 &ipmmu_vc1 {
 129         renesas,ipmmu-main = <&ipmmu_mm 10>;
 130 };
 131
 132 &ipmmu_rt {
 133         renesas,ipmmu-main = <&ipmmu_mm 7>;
 134 };
 135
 136 &audma0 {
 137         iommus = <&ipmmu_mp1 0>, <&ipmmu_mp1 1>,
 138                <&ipmmu_mp1 2>, <&ipmmu_mp1 3>,
 139                <&ipmmu_mp1 4>, <&ipmmu_mp1 5>,
 140                <&ipmmu_mp1 6>, <&ipmmu_mp1 7>,
 141                <&ipmmu_mp1 8>, <&ipmmu_mp1 9>,
 142                <&ipmmu_mp1 10>, <&ipmmu_mp1 11>,
 143                <&ipmmu_mp1 12>, <&ipmmu_mp1 13>,
 144                <&ipmmu_mp1 14>, <&ipmmu_mp1 15>;
 145 };
 146
 147 &audma1 {
 148         iommus = <&ipmmu_mp1 16>, <&ipmmu_mp1 17>,
 149                <&ipmmu_mp1 18>, <&ipmmu_mp1 19>,
 150                <&ipmmu_mp1 20>, <&ipmmu_mp1 21>,
 151                <&ipmmu_mp1 22>, <&ipmmu_mp1 23>,
 152                <&ipmmu_mp1 24>, <&ipmmu_mp1 25>,
 153                <&ipmmu_mp1 26>, <&ipmmu_mp1 27>,
 154                <&ipmmu_mp1 28>, <&ipmmu_mp1 29>,
 155                <&ipmmu_mp1 30>, <&ipmmu_mp1 31>;
 156 };
 157
 158 &fcpvb1 {
 159         iommus = <&ipmmu_vp0 7>;
 160 };
 161
 162 &fcpf1 {
 163         iommus = <&ipmmu_vp0 1>;
 164 };
 165
 166 &fcpvi1 {
 167         iommus = <&ipmmu_vp0 9>;
 168 };
 169
 170 &fcpvd2 {
 171         iommus = <&ipmmu_vi0 10>;
 172 };
 173
 174 &du {
 175         vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
 176 };