arch/arm64/boot/dts/qcom/sc8280xp.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
   8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
  12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
  13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/mailbox/qcom-ipcc.h>
  17 #include <dt-bindings/phy/phy-qcom-qmp.h>
  18 #include <dt-bindings/power/qcom-rpmpd.h>
  19 #include <dt-bindings/soc/qcom,gpr.h>
  20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  21 #include <dt-bindings/sound/qcom,q6afe.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23
  24 / {
  25         interrupt-parent = <&intc>;
  26
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         clocks {
  31                 xo_board_clk: xo-board-clk {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                 };
  35
  36                 sleep_clk: sleep-clk {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <32764>;
  40                 };
  41         };
  42
  43         cpus {
  44                 #address-cells = <2>;
  45                 #size-cells = <0>;
  46
  47                 CPU0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a78c";
  50                         reg = <0x0 0x0>;
  51                         clocks = <&cpufreq_hw 0>;
  52                         enable-method = "psci";
  53                         capacity-dmips-mhz = <602>;
  54                         next-level-cache = <&L2_0>;
  55                         power-domains = <&CPU_PD0>;
  56                         power-domain-names = "psci";
  57                         qcom,freq-domain = <&cpufreq_hw 0>;
  58                         operating-points-v2 = <&cpu0_opp_table>;
  59                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  60                         #cooling-cells = <2>;
  61                         L2_0: l2-cache {
  62                                 compatible = "cache";
  63                                 cache-level = <2>;
  64                                 cache-unified;
  65                                 next-level-cache = <&L3_0>;
  66                                 L3_0: l3-cache {
  67                                         compatible = "cache";
  68                                         cache-level = <3>;
  69                                         cache-unified;
  70                                 };
  71                         };
  72                 };
  73
  74                 CPU1: cpu@100 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a78c";
  77                         reg = <0x0 0x100>;
  78                         clocks = <&cpufreq_hw 0>;
  79                         enable-method = "psci";
  80                         capacity-dmips-mhz = <602>;
  81                         next-level-cache = <&L2_100>;
  82                         power-domains = <&CPU_PD1>;
  83                         power-domain-names = "psci";
  84                         qcom,freq-domain = <&cpufreq_hw 0>;
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  87                         #cooling-cells = <2>;
  88                         L2_100: l2-cache {
  89                                 compatible = "cache";
  90                                 cache-level = <2>;
  91                                 cache-unified;
  92                                 next-level-cache = <&L3_0>;
  93                         };
  94                 };
  95
  96                 CPU2: cpu@200 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a78c";
  99                         reg = <0x0 0x200>;
 100                         clocks = <&cpufreq_hw 0>;
 101                         enable-method = "psci";
 102                         capacity-dmips-mhz = <602>;
 103                         next-level-cache = <&L2_200>;
 104                         power-domains = <&CPU_PD2>;
 105                         power-domain-names = "psci";
 106                         qcom,freq-domain = <&cpufreq_hw 0>;
 107                         operating-points-v2 = <&cpu0_opp_table>;
 108                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 109                         #cooling-cells = <2>;
 110                         L2_200: l2-cache {
 111                                 compatible = "cache";
 112                                 cache-level = <2>;
 113                                 cache-unified;
 114                                 next-level-cache = <&L3_0>;
 115                         };
 116                 };
 117
 118                 CPU3: cpu@300 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a78c";
 121                         reg = <0x0 0x300>;
 122                         clocks = <&cpufreq_hw 0>;
 123                         enable-method = "psci";
 124                         capacity-dmips-mhz = <602>;
 125                         next-level-cache = <&L2_300>;
 126                         power-domains = <&CPU_PD3>;
 127                         power-domain-names = "psci";
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         operating-points-v2 = <&cpu0_opp_table>;
 130                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 131                         #cooling-cells = <2>;
 132                         L2_300: l2-cache {
 133                                 compatible = "cache";
 134                                 cache-level = <2>;
 135                                 cache-unified;
 136                                 next-level-cache = <&L3_0>;
 137                         };
 138                 };
 139
 140                 CPU4: cpu@400 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-x1c";
 143                         reg = <0x0 0x400>;
 144                         clocks = <&cpufreq_hw 1>;
 145                         enable-method = "psci";
 146                         capacity-dmips-mhz = <1024>;
 147                         next-level-cache = <&L2_400>;
 148                         power-domains = <&CPU_PD4>;
 149                         power-domain-names = "psci";
 150                         qcom,freq-domain = <&cpufreq_hw 1>;
 151                         operating-points-v2 = <&cpu4_opp_table>;
 152                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 153                         #cooling-cells = <2>;
 154                         L2_400: l2-cache {
 155                                 compatible = "cache";
 156                                 cache-level = <2>;
 157                                 cache-unified;
 158                                 next-level-cache = <&L3_0>;
 159                         };
 160                 };
 161
 162                 CPU5: cpu@500 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-x1c";
 165                         reg = <0x0 0x500>;
 166                         clocks = <&cpufreq_hw 1>;
 167                         enable-method = "psci";
 168                         capacity-dmips-mhz = <1024>;
 169                         next-level-cache = <&L2_500>;
 170                         power-domains = <&CPU_PD5>;
 171                         power-domain-names = "psci";
 172                         qcom,freq-domain = <&cpufreq_hw 1>;
 173                         operating-points-v2 = <&cpu4_opp_table>;
 174                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 175                         #cooling-cells = <2>;
 176                         L2_500: l2-cache {
 177                                 compatible = "cache";
 178                                 cache-level = <2>;
 179                                 cache-unified;
 180                                 next-level-cache = <&L3_0>;
 181                         };
 182                 };
 183
 184                 CPU6: cpu@600 {
 185                         device_type = "cpu";
 186                         compatible = "arm,cortex-x1c";
 187                         reg = <0x0 0x600>;
 188                         clocks = <&cpufreq_hw 1>;
 189                         enable-method = "psci";
 190                         capacity-dmips-mhz = <1024>;
 191                         next-level-cache = <&L2_600>;
 192                         power-domains = <&CPU_PD6>;
 193                         power-domain-names = "psci";
 194                         qcom,freq-domain = <&cpufreq_hw 1>;
 195                         operating-points-v2 = <&cpu4_opp_table>;
 196                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 197                         #cooling-cells = <2>;
 198                         L2_600: l2-cache {
 199                                 compatible = "cache";
 200                                 cache-level = <2>;
 201                                 cache-unified;
 202                                 next-level-cache = <&L3_0>;
 203                         };
 204                 };
 205
 206                 CPU7: cpu@700 {
 207                         device_type = "cpu";
 208                         compatible = "arm,cortex-x1c";
 209                         reg = <0x0 0x700>;
 210                         clocks = <&cpufreq_hw 1>;
 211                         enable-method = "psci";
 212                         capacity-dmips-mhz = <1024>;
 213                         next-level-cache = <&L2_700>;
 214                         power-domains = <&CPU_PD7>;
 215                         power-domain-names = "psci";
 216                         qcom,freq-domain = <&cpufreq_hw 1>;
 217                         operating-points-v2 = <&cpu4_opp_table>;
 218                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 219                         #cooling-cells = <2>;
 220                         L2_700: l2-cache {
 221                                 compatible = "cache";
 222                                 cache-level = <2>;
 223                                 cache-unified;
 224                                 next-level-cache = <&L3_0>;
 225                         };
 226                 };
 227
 228                 cpu-map {
 229                         cluster0 {
 230                                 core0 {
 231                                         cpu = <&CPU0>;
 232                                 };
 233
 234                                 core1 {
 235                                         cpu = <&CPU1>;
 236                                 };
 237
 238                                 core2 {
 239                                         cpu = <&CPU2>;
 240                                 };
 241
 242                                 core3 {
 243                                         cpu = <&CPU3>;
 244                                 };
 245
 246                                 core4 {
 247                                         cpu = <&CPU4>;
 248                                 };
 249
 250                                 core5 {
 251                                         cpu = <&CPU5>;
 252                                 };
 253
 254                                 core6 {
 255                                         cpu = <&CPU6>;
 256                                 };
 257
 258                                 core7 {
 259                                         cpu = <&CPU7>;
 260                                 };
 261                         };
 262                 };
 263
 264                 idle-states {
 265                         entry-method = "psci";
 266
 267                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 268                                 compatible = "arm,idle-state";
 269                                 idle-state-name = "little-rail-power-collapse";
 270                                 arm,psci-suspend-param = <0x40000004>;
 271                                 entry-latency-us = <355>;
 272                                 exit-latency-us = <909>;
 273                                 min-residency-us = <3934>;
 274                                 local-timer-stop;
 275                         };
 276
 277                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 278                                 compatible = "arm,idle-state";
 279                                 idle-state-name = "big-rail-power-collapse";
 280                                 arm,psci-suspend-param = <0x40000004>;
 281                                 entry-latency-us = <241>;
 282                                 exit-latency-us = <1461>;
 283                                 min-residency-us = <4488>;
 284                                 local-timer-stop;
 285                         };
 286                 };
 287
 288                 domain-idle-states {
 289                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 290                                 compatible = "domain-idle-state";
 291                                 arm,psci-suspend-param = <0x4100c344>;
 292                                 entry-latency-us = <3263>;
 293                                 exit-latency-us = <6562>;
 294                                 min-residency-us = <9987>;
 295                         };
 296                 };
 297         };
 298
 299         firmware {
 300                 scm: scm {
 301                         compatible = "qcom,scm-sc8280xp", "qcom,scm";
 302                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 303                 };
 304         };
 305
 306         aggre1_noc: interconnect-aggre1-noc {
 307                 compatible = "qcom,sc8280xp-aggre1-noc";
 308                 #interconnect-cells = <2>;
 309                 qcom,bcm-voters = <&apps_bcm_voter>;
 310         };
 311
 312         aggre2_noc: interconnect-aggre2-noc {
 313                 compatible = "qcom,sc8280xp-aggre2-noc";
 314                 #interconnect-cells = <2>;
 315                 qcom,bcm-voters = <&apps_bcm_voter>;
 316         };
 317
 318         clk_virt: interconnect-clk-virt {
 319                 compatible = "qcom,sc8280xp-clk-virt";
 320                 #interconnect-cells = <2>;
 321                 qcom,bcm-voters = <&apps_bcm_voter>;
 322         };
 323
 324         config_noc: interconnect-config-noc {
 325                 compatible = "qcom,sc8280xp-config-noc";
 326                 #interconnect-cells = <2>;
 327                 qcom,bcm-voters = <&apps_bcm_voter>;
 328         };
 329
 330         dc_noc: interconnect-dc-noc {
 331                 compatible = "qcom,sc8280xp-dc-noc";
 332                 #interconnect-cells = <2>;
 333                 qcom,bcm-voters = <&apps_bcm_voter>;
 334         };
 335
 336         gem_noc: interconnect-gem-noc {
 337                 compatible = "qcom,sc8280xp-gem-noc";
 338                 #interconnect-cells = <2>;
 339                 qcom,bcm-voters = <&apps_bcm_voter>;
 340         };
 341
 342         lpass_noc: interconnect-lpass-ag-noc {
 343                 compatible = "qcom,sc8280xp-lpass-ag-noc";
 344                 #interconnect-cells = <2>;
 345                 qcom,bcm-voters = <&apps_bcm_voter>;
 346         };
 347
 348         mc_virt: interconnect-mc-virt {
 349                 compatible = "qcom,sc8280xp-mc-virt";
 350                 #interconnect-cells = <2>;
 351                 qcom,bcm-voters = <&apps_bcm_voter>;
 352         };
 353
 354         mmss_noc: interconnect-mmss-noc {
 355                 compatible = "qcom,sc8280xp-mmss-noc";
 356                 #interconnect-cells = <2>;
 357                 qcom,bcm-voters = <&apps_bcm_voter>;
 358         };
 359
 360         nspa_noc: interconnect-nspa-noc {
 361                 compatible = "qcom,sc8280xp-nspa-noc";
 362                 #interconnect-cells = <2>;
 363                 qcom,bcm-voters = <&apps_bcm_voter>;
 364         };
 365
 366         nspb_noc: interconnect-nspb-noc {
 367                 compatible = "qcom,sc8280xp-nspb-noc";
 368                 #interconnect-cells = <2>;
 369                 qcom,bcm-voters = <&apps_bcm_voter>;
 370         };
 371
 372         system_noc: interconnect-system-noc {
 373                 compatible = "qcom,sc8280xp-system-noc";
 374                 #interconnect-cells = <2>;
 375                 qcom,bcm-voters = <&apps_bcm_voter>;
 376         };
 377
 378         memory@80000000 {
 379                 device_type = "memory";
 380                 /* We expect the bootloader to fill in the size */
 381                 reg = <0x0 0x80000000 0x0 0x0>;
 382         };
 383
 384         cpu0_opp_table: opp-table-cpu0 {
 385                 compatible = "operating-points-v2";
 386                 opp-shared;
 387
 388                 opp-300000000 {
 389                         opp-hz = /bits/ 64 <300000000>;
 390                         opp-peak-kBps = <(300000 * 32)>;
 391                 };
 392                 opp-403200000 {
 393                         opp-hz = /bits/ 64 <403200000>;
 394                         opp-peak-kBps = <(384000 * 32)>;
 395                 };
 396                 opp-499200000 {
 397                         opp-hz = /bits/ 64 <499200000>;
 398                         opp-peak-kBps = <(480000 * 32)>;
 399                 };
 400                 opp-595200000 {
 401                         opp-hz = /bits/ 64 <595200000>;
 402                         opp-peak-kBps = <(576000 * 32)>;
 403                 };
 404                 opp-691200000 {
 405                         opp-hz = /bits/ 64 <691200000>;
 406                         opp-peak-kBps = <(672000 * 32)>;
 407                 };
 408                 opp-806400000 {
 409                         opp-hz = /bits/ 64 <806400000>;
 410                         opp-peak-kBps = <(768000 * 32)>;
 411                 };
 412                 opp-902400000 {
 413                         opp-hz = /bits/ 64 <902400000>;
 414                         opp-peak-kBps = <(864000 * 32)>;
 415                 };
 416                 opp-1017600000 {
 417                         opp-hz = /bits/ 64 <1017600000>;
 418                         opp-peak-kBps = <(960000 * 32)>;
 419                 };
 420                 opp-1113600000 {
 421                         opp-hz = /bits/ 64 <1113600000>;
 422                         opp-peak-kBps = <(1075200 * 32)>;
 423                 };
 424                 opp-1209600000 {
 425                         opp-hz = /bits/ 64 <1209600000>;
 426                         opp-peak-kBps = <(1171200 * 32)>;
 427                 };
 428                 opp-1324800000 {
 429                         opp-hz = /bits/ 64 <1324800000>;
 430                         opp-peak-kBps = <(1267200 * 32)>;
 431                 };
 432                 opp-1440000000 {
 433                         opp-hz = /bits/ 64 <1440000000>;
 434                         opp-peak-kBps = <(1363200 * 32)>;
 435                 };
 436                 opp-1555200000 {
 437                         opp-hz = /bits/ 64 <1555200000>;
 438                         opp-peak-kBps = <(1536000 * 32)>;
 439                 };
 440                 opp-1670400000 {
 441                         opp-hz = /bits/ 64 <1670400000>;
 442                         opp-peak-kBps = <(1612800 * 32)>;
 443                 };
 444                 opp-1785600000 {
 445                         opp-hz = /bits/ 64 <1785600000>;
 446                         opp-peak-kBps = <(1689600 * 32)>;
 447                 };
 448                 opp-1881600000 {
 449                         opp-hz = /bits/ 64 <1881600000>;
 450                         opp-peak-kBps = <(1689600 * 32)>;
 451                 };
 452                 opp-1996800000 {
 453                         opp-hz = /bits/ 64 <1996800000>;
 454                         opp-peak-kBps = <(1689600 * 32)>;
 455                 };
 456                 opp-2112000000 {
 457                         opp-hz = /bits/ 64 <2112000000>;
 458                         opp-peak-kBps = <(1689600 * 32)>;
 459                 };
 460                 opp-2227200000 {
 461                         opp-hz = /bits/ 64 <2227200000>;
 462                         opp-peak-kBps = <(1689600 * 32)>;
 463                 };
 464                 opp-2342400000 {
 465                         opp-hz = /bits/ 64 <2342400000>;
 466                         opp-peak-kBps = <(1689600 * 32)>;
 467                 };
 468                 opp-2438400000 {
 469                         opp-hz = /bits/ 64 <2438400000>;
 470                         opp-peak-kBps = <(1689600 * 32)>;
 471                 };
 472         };
 473
 474         cpu4_opp_table: opp-table-cpu4 {
 475                 compatible = "operating-points-v2";
 476                 opp-shared;
 477
 478                 opp-825600000 {
 479                         opp-hz = /bits/ 64 <825600000>;
 480                         opp-peak-kBps = <(768000 * 32)>;
 481                 };
 482                 opp-940800000 {
 483                         opp-hz = /bits/ 64 <940800000>;
 484                         opp-peak-kBps = <(864000 * 32)>;
 485                 };
 486                 opp-1056000000 {
 487                         opp-hz = /bits/ 64 <1056000000>;
 488                         opp-peak-kBps = <(960000 * 32)>;
 489                 };
 490                 opp-1171200000 {
 491                         opp-hz = /bits/ 64 <1171200000>;
 492                         opp-peak-kBps = <(1171200 * 32)>;
 493                 };
 494                 opp-1286400000 {
 495                         opp-hz = /bits/ 64 <1286400000>;
 496                         opp-peak-kBps = <(1267200 * 32)>;
 497                 };
 498                 opp-1401600000 {
 499                         opp-hz = /bits/ 64 <1401600000>;
 500                         opp-peak-kBps = <(1363200 * 32)>;
 501                 };
 502                 opp-1516800000 {
 503                         opp-hz = /bits/ 64 <1516800000>;
 504                         opp-peak-kBps = <(1459200 * 32)>;
 505                 };
 506                 opp-1632000000 {
 507                         opp-hz = /bits/ 64 <1632000000>;
 508                         opp-peak-kBps = <(1612800 * 32)>;
 509                 };
 510                 opp-1747200000 {
 511                         opp-hz = /bits/ 64 <1747200000>;
 512                         opp-peak-kBps = <(1689600 * 32)>;
 513                 };
 514                 opp-1862400000 {
 515                         opp-hz = /bits/ 64 <1862400000>;
 516                         opp-peak-kBps = <(1689600 * 32)>;
 517                 };
 518                 opp-1977600000 {
 519                         opp-hz = /bits/ 64 <1977600000>;
 520                         opp-peak-kBps = <(1689600 * 32)>;
 521                 };
 522                 opp-2073600000 {
 523                         opp-hz = /bits/ 64 <2073600000>;
 524                         opp-peak-kBps = <(1689600 * 32)>;
 525                 };
 526                 opp-2169600000 {
 527                         opp-hz = /bits/ 64 <2169600000>;
 528                         opp-peak-kBps = <(1689600 * 32)>;
 529                 };
 530                 opp-2284800000 {
 531                         opp-hz = /bits/ 64 <2284800000>;
 532                         opp-peak-kBps = <(1689600 * 32)>;
 533                 };
 534                 opp-2400000000 {
 535                         opp-hz = /bits/ 64 <2400000000>;
 536                         opp-peak-kBps = <(1689600 * 32)>;
 537                 };
 538                 opp-2496000000 {
 539                         opp-hz = /bits/ 64 <2496000000>;
 540                         opp-peak-kBps = <(1689600 * 32)>;
 541                 };
 542                 opp-2592000000 {
 543                         opp-hz = /bits/ 64 <2592000000>;
 544                         opp-peak-kBps = <(1689600 * 32)>;
 545                 };
 546                 opp-2688000000 {
 547                         opp-hz = /bits/ 64 <2688000000>;
 548                         opp-peak-kBps = <(1689600 * 32)>;
 549                 };
 550                 opp-2803200000 {
 551                         opp-hz = /bits/ 64 <2803200000>;
 552                         opp-peak-kBps = <(1689600 * 32)>;
 553                 };
 554                 opp-2899200000 {
 555                         opp-hz = /bits/ 64 <2899200000>;
 556                         opp-peak-kBps = <(1689600 * 32)>;
 557                 };
 558                 opp-2995200000 {
 559                         opp-hz = /bits/ 64 <2995200000>;
 560                         opp-peak-kBps = <(1689600 * 32)>;
 561                 };
 562         };
 563
 564         qup_opp_table_100mhz: opp-table-qup100mhz {
 565                 compatible = "operating-points-v2";
 566
 567                 opp-75000000 {
 568                         opp-hz = /bits/ 64 <75000000>;
 569                         required-opps = <&rpmhpd_opp_low_svs>;
 570                 };
 571
 572                 opp-100000000 {
 573                         opp-hz = /bits/ 64 <100000000>;
 574                         required-opps = <&rpmhpd_opp_svs>;
 575                 };
 576         };
 577
 578         pmu {
 579                 compatible = "arm,armv8-pmuv3";
 580                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 581         };
 582
 583         psci {
 584                 compatible = "arm,psci-1.0";
 585                 method = "smc";
 586
 587                 CPU_PD0: power-domain-cpu0 {
 588                         #power-domain-cells = <0>;
 589                         power-domains = <&CLUSTER_PD>;
 590                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 591                 };
 592
 593                 CPU_PD1: power-domain-cpu1 {
 594                         #power-domain-cells = <0>;
 595                         power-domains = <&CLUSTER_PD>;
 596                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 597                 };
 598
 599                 CPU_PD2: power-domain-cpu2 {
 600                         #power-domain-cells = <0>;
 601                         power-domains = <&CLUSTER_PD>;
 602                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 603                 };
 604
 605                 CPU_PD3: power-domain-cpu3 {
 606                         #power-domain-cells = <0>;
 607                         power-domains = <&CLUSTER_PD>;
 608                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 609                 };
 610
 611                 CPU_PD4: power-domain-cpu4 {
 612                         #power-domain-cells = <0>;
 613                         power-domains = <&CLUSTER_PD>;
 614                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 615                 };
 616
 617                 CPU_PD5: power-domain-cpu5 {
 618                         #power-domain-cells = <0>;
 619                         power-domains = <&CLUSTER_PD>;
 620                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 621                 };
 622
 623                 CPU_PD6: power-domain-cpu6 {
 624                         #power-domain-cells = <0>;
 625                         power-domains = <&CLUSTER_PD>;
 626                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 627                 };
 628
 629                 CPU_PD7: power-domain-cpu7 {
 630                         #power-domain-cells = <0>;
 631                         power-domains = <&CLUSTER_PD>;
 632                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 633                 };
 634
 635                 CLUSTER_PD: power-domain-cpu-cluster0 {
 636                         #power-domain-cells = <0>;
 637                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 638                 };
 639         };
 640
 641         reserved-memory {
 642                 #address-cells = <2>;
 643                 #size-cells = <2>;
 644                 ranges;
 645
 646                 reserved-region@80000000 {
 647                         reg = <0 0x80000000 0 0x860000>;
 648                         no-map;
 649                 };
 650
 651                 cmd_db: cmd-db-region@80860000 {
 652                         compatible = "qcom,cmd-db";
 653                         reg = <0 0x80860000 0 0x20000>;
 654                         no-map;
 655                 };
 656
 657                 reserved-region@80880000 {
 658                         reg = <0 0x80880000 0 0x80000>;
 659                         no-map;
 660                 };
 661
 662                 smem_mem: smem-region@80900000 {
 663                         compatible = "qcom,smem";
 664                         reg = <0 0x80900000 0 0x200000>;
 665                         no-map;
 666                         hwlocks = <&tcsr_mutex 3>;
 667                 };
 668
 669                 reserved-region@80b00000 {
 670                         reg = <0 0x80b00000 0 0x100000>;
 671                         no-map;
 672                 };
 673
 674                 reserved-region@83b00000 {
 675                         reg = <0 0x83b00000 0 0x1700000>;
 676                         no-map;
 677                 };
 678
 679                 reserved-region@85b00000 {
 680                         reg = <0 0x85b00000 0 0xc00000>;
 681                         no-map;
 682                 };
 683
 684                 pil_adsp_mem: adsp-region@86c00000 {
 685                         reg = <0 0x86c00000 0 0x2000000>;
 686                         no-map;
 687                 };
 688
 689                 pil_nsp0_mem: cdsp0-region@8a100000 {
 690                         reg = <0 0x8a100000 0 0x1e00000>;
 691                         no-map;
 692                 };
 693
 694                 pil_nsp1_mem: cdsp1-region@8c600000 {
 695                         reg = <0 0x8c600000 0 0x1e00000>;
 696                         no-map;
 697                 };
 698
 699                 reserved-region@aeb00000 {
 700                         reg = <0 0xaeb00000 0 0x16600000>;
 701                         no-map;
 702                 };
 703         };
 704
 705         smp2p-adsp {
 706                 compatible = "qcom,smp2p";
 707                 qcom,smem = <443>, <429>;
 708                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 709                                              IPCC_MPROC_SIGNAL_SMP2P
 710                                              IRQ_TYPE_EDGE_RISING>;
 711                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 712                                 IPCC_MPROC_SIGNAL_SMP2P>;
 713
 714                 qcom,local-pid = <0>;
 715                 qcom,remote-pid = <2>;
 716
 717                 smp2p_adsp_out: master-kernel {
 718                         qcom,entry-name = "master-kernel";
 719                         #qcom,smem-state-cells = <1>;
 720                 };
 721
 722                 smp2p_adsp_in: slave-kernel {
 723                         qcom,entry-name = "slave-kernel";
 724                         interrupt-controller;
 725                         #interrupt-cells = <2>;
 726                 };
 727         };
 728
 729         smp2p-nsp0 {
 730                 compatible = "qcom,smp2p";
 731                 qcom,smem = <94>, <432>;
 732                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 733                                              IPCC_MPROC_SIGNAL_SMP2P
 734                                              IRQ_TYPE_EDGE_RISING>;
 735                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 736                                 IPCC_MPROC_SIGNAL_SMP2P>;
 737
 738                 qcom,local-pid = <0>;
 739                 qcom,remote-pid = <5>;
 740
 741                 smp2p_nsp0_out: master-kernel {
 742                         qcom,entry-name = "master-kernel";
 743                         #qcom,smem-state-cells = <1>;
 744                 };
 745
 746                 smp2p_nsp0_in: slave-kernel {
 747                         qcom,entry-name = "slave-kernel";
 748                         interrupt-controller;
 749                         #interrupt-cells = <2>;
 750                 };
 751         };
 752
 753         smp2p-nsp1 {
 754                 compatible = "qcom,smp2p";
 755                 qcom,smem = <617>, <616>;
 756                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
 757                                              IPCC_MPROC_SIGNAL_SMP2P
 758                                              IRQ_TYPE_EDGE_RISING>;
 759                 mboxes = <&ipcc IPCC_CLIENT_NSP1
 760                                 IPCC_MPROC_SIGNAL_SMP2P>;
 761
 762                 qcom,local-pid = <0>;
 763                 qcom,remote-pid = <12>;
 764
 765                 smp2p_nsp1_out: master-kernel {
 766                         qcom,entry-name = "master-kernel";
 767                         #qcom,smem-state-cells = <1>;
 768                 };
 769
 770                 smp2p_nsp1_in: slave-kernel {
 771                         qcom,entry-name = "slave-kernel";
 772                         interrupt-controller;
 773                         #interrupt-cells = <2>;
 774                 };
 775         };
 776
 777         soc: soc@0 {
 778                 compatible = "simple-bus";
 779                 #address-cells = <2>;
 780                 #size-cells = <2>;
 781                 ranges = <0 0 0 0 0x10 0>;
 782                 dma-ranges = <0 0 0 0 0x10 0>;
 783
 784                 ethernet0: ethernet@20000 {
 785                         compatible = "qcom,sc8280xp-ethqos";
 786                         reg = <0x0 0x00020000 0x0 0x10000>,
 787                               <0x0 0x00036000 0x0 0x100>;
 788                         reg-names = "stmmaceth", "rgmii";
 789
 790                         clocks = <&gcc GCC_EMAC0_AXI_CLK>,
 791                                  <&gcc GCC_EMAC0_SLV_AHB_CLK>,
 792                                  <&gcc GCC_EMAC0_PTP_CLK>,
 793                                  <&gcc GCC_EMAC0_RGMII_CLK>;
 794                         clock-names = "stmmaceth",
 795                                       "pclk",
 796                                       "ptp_ref",
 797                                       "rgmii";
 798
 799                         interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
 800                                      <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
 801                         interrupt-names = "macirq", "eth_lpi";
 802
 803                         iommus = <&apps_smmu 0x4c0 0xf>;
 804                         power-domains = <&gcc EMAC_0_GDSC>;
 805
 806                         snps,tso;
 807                         snps,pbl = <32>;
 808                         rx-fifo-depth = <4096>;
 809                         tx-fifo-depth = <4096>;
 810
 811                         status = "disabled";
 812                 };
 813
 814                 gcc: clock-controller@100000 {
 815                         compatible = "qcom,gcc-sc8280xp";
 816                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 817                         #clock-cells = <1>;
 818                         #reset-cells = <1>;
 819                         #power-domain-cells = <1>;
 820                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 821                                  <&sleep_clk>,
 822                                  <0>,
 823                                  <0>,
 824                                  <0>,
 825                                  <0>,
 826                                  <0>,
 827                                  <0>,
 828                                  <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 829                                  <0>,
 830                                  <0>,
 831                                  <0>,
 832                                  <0>,
 833                                  <0>,
 834                                  <0>,
 835                                  <0>,
 836                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 837                                  <0>,
 838                                  <0>,
 839                                  <0>,
 840                                  <0>,
 841                                  <0>,
 842                                  <0>,
 843                                  <0>,
 844                                  <0>,
 845                                  <0>,
 846                                  <&pcie2a_phy>,
 847                                  <&pcie2b_phy>,
 848                                  <&pcie3a_phy>,
 849                                  <&pcie3b_phy>,
 850                                  <&pcie4_phy>,
 851                                  <0>,
 852                                  <0>;
 853                         power-domains = <&rpmhpd SC8280XP_CX>;
 854                 };
 855
 856                 ipcc: mailbox@408000 {
 857                         compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
 858                         reg = <0 0x00408000 0 0x1000>;
 859                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 860                         interrupt-controller;
 861                         #interrupt-cells = <3>;
 862                         #mbox-cells = <2>;
 863                 };
 864
 865                 qup2: geniqup@8c0000 {
 866                         compatible = "qcom,geni-se-qup";
 867                         reg = <0 0x008c0000 0 0x2000>;
 868                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 869                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 870                         clock-names = "m-ahb", "s-ahb";
 871                         iommus = <&apps_smmu 0xa3 0>;
 872
 873                         #address-cells = <2>;
 874                         #size-cells = <2>;
 875                         ranges;
 876
 877                         status = "disabled";
 878
 879                         i2c16: i2c@880000 {
 880                                 compatible = "qcom,geni-i2c";
 881                                 reg = <0 0x00880000 0 0x4000>;
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 885                                 clock-names = "se";
 886                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 887                                 power-domains = <&rpmhpd SC8280XP_CX>;
 888                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 889                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 890                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 891                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 892                                 status = "disabled";
 893                         };
 894
 895                         spi16: spi@880000 {
 896                                 compatible = "qcom,geni-spi";
 897                                 reg = <0 0x00880000 0 0x4000>;
 898                                 #address-cells = <1>;
 899                                 #size-cells = <0>;
 900                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 901                                 clock-names = "se";
 902                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 903                                 power-domains = <&rpmhpd SC8280XP_CX>;
 904                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 905                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 906                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 907                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 908                                 status = "disabled";
 909                         };
 910
 911                         i2c17: i2c@884000 {
 912                                 compatible = "qcom,geni-i2c";
 913                                 reg = <0 0x00884000 0 0x4000>;
 914                                 #address-cells = <1>;
 915                                 #size-cells = <0>;
 916                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 917                                 clock-names = "se";
 918                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 919                                 power-domains = <&rpmhpd SC8280XP_CX>;
 920                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 921                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 922                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 923                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 924                                 status = "disabled";
 925                         };
 926
 927                         spi17: spi@884000 {
 928                                 compatible = "qcom,geni-spi";
 929                                 reg = <0 0x00884000 0 0x4000>;
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 933                                 clock-names = "se";
 934                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 935                                 power-domains = <&rpmhpd SC8280XP_CX>;
 936                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 937                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 938                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 939                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 940                                 status = "disabled";
 941                         };
 942
 943                         uart17: serial@884000 {
 944                                 compatible = "qcom,geni-uart";
 945                                 reg = <0 0x00884000 0 0x4000>;
 946                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 947                                 clock-names = "se";
 948                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 949                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 950                                 power-domains = <&rpmhpd SC8280XP_CX>;
 951                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 952                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
 953                                 interconnect-names = "qup-core", "qup-config";
 954                                 status = "disabled";
 955                         };
 956
 957                         i2c18: i2c@888000 {
 958                                 compatible = "qcom,geni-i2c";
 959                                 reg = <0 0x00888000 0 0x4000>;
 960                                 #address-cells = <1>;
 961                                 #size-cells = <0>;
 962                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 963                                 clock-names = "se";
 964                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 965                                 power-domains = <&rpmhpd SC8280XP_CX>;
 966                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 967                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 968                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 969                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 970                                 status = "disabled";
 971                         };
 972
 973                         spi18: spi@888000 {
 974                                 compatible = "qcom,geni-spi";
 975                                 reg = <0 0x00888000 0 0x4000>;
 976                                 #address-cells = <1>;
 977                                 #size-cells = <0>;
 978                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 979                                 clock-names = "se";
 980                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 981                                 power-domains = <&rpmhpd SC8280XP_CX>;
 982                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 983                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 984                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 985                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 986                                 status = "disabled";
 987                         };
 988
 989                         i2c19: i2c@88c000 {
 990                                 compatible = "qcom,geni-i2c";
 991                                 reg = <0 0x0088c000 0 0x4000>;
 992                                 #address-cells = <1>;
 993                                 #size-cells = <0>;
 994                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 995                                 clock-names = "se";
 996                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 997                                 power-domains = <&rpmhpd SC8280XP_CX>;
 998                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 999                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1000                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1001                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1002                                 status = "disabled";
1003                         };
1004
1005                         spi19: spi@88c000 {
1006                                 compatible = "qcom,geni-spi";
1007                                 reg = <0 0x0088c000 0 0x4000>;
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1011                                 clock-names = "se";
1012                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1013                                 power-domains = <&rpmhpd SC8280XP_CX>;
1014                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1015                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1016                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1017                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1018                                 status = "disabled";
1019                         };
1020
1021                         i2c20: i2c@890000 {
1022                                 compatible = "qcom,geni-i2c";
1023                                 reg = <0 0x00890000 0 0x4000>;
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1027                                 clock-names = "se";
1028                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1029                                 power-domains = <&rpmhpd SC8280XP_CX>;
1030                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1031                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1032                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1033                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1034                                 status = "disabled";
1035                         };
1036
1037                         spi20: spi@890000 {
1038                                 compatible = "qcom,geni-spi";
1039                                 reg = <0 0x00890000 0 0x4000>;
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1043                                 clock-names = "se";
1044                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1045                                 power-domains = <&rpmhpd SC8280XP_CX>;
1046                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1047                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1048                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1049                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1050                                 status = "disabled";
1051                         };
1052
1053                         i2c21: i2c@894000 {
1054                                 compatible = "qcom,geni-i2c";
1055                                 reg = <0 0x00894000 0 0x4000>;
1056                                 clock-names = "se";
1057                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1058                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 power-domains = <&rpmhpd SC8280XP_CX>;
1062                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1063                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1064                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1065                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1066                                 status = "disabled";
1067                         };
1068
1069                         spi21: spi@894000 {
1070                                 compatible = "qcom,geni-spi";
1071                                 reg = <0 0x00894000 0 0x4000>;
1072                                 #address-cells = <1>;
1073                                 #size-cells = <0>;
1074                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1075                                 clock-names = "se";
1076                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1077                                 power-domains = <&rpmhpd SC8280XP_CX>;
1078                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1080                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1081                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1082                                 status = "disabled";
1083                         };
1084
1085                         i2c22: i2c@898000 {
1086                                 compatible = "qcom,geni-i2c";
1087                                 reg = <0 0x00898000 0 0x4000>;
1088                                 #address-cells = <1>;
1089                                 #size-cells = <0>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1092                                 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1093                                 power-domains = <&rpmhpd SC8280XP_CX>;
1094                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1095                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1096                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1097                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1098                                 status = "disabled";
1099                         };
1100
1101                         spi22: spi@898000 {
1102                                 compatible = "qcom,geni-spi";
1103                                 reg = <0 0x00898000 0 0x4000>;
1104                                 #address-cells = <1>;
1105                                 #size-cells = <0>;
1106                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1107                                 clock-names = "se";
1108                                 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1109                                 power-domains = <&rpmhpd SC8280XP_CX>;
1110                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1111                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1112                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1113                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1114                                 status = "disabled";
1115                         };
1116
1117                         i2c23: i2c@89c000 {
1118                                 compatible = "qcom,geni-i2c";
1119                                 reg = <0 0x0089c000 0 0x4000>;
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122                                 clock-names = "se";
1123                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1124                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1125                                 power-domains = <&rpmhpd SC8280XP_CX>;
1126                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1127                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1128                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1129                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1130                                 status = "disabled";
1131                         };
1132
1133                         spi23: spi@89c000 {
1134                                 compatible = "qcom,geni-spi";
1135                                 reg = <0 0x0089c000 0 0x4000>;
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1139                                 clock-names = "se";
1140                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1141                                 power-domains = <&rpmhpd SC8280XP_CX>;
1142                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1143                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1144                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1145                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1146                                 status = "disabled";
1147                         };
1148                 };
1149
1150                 qup0: geniqup@9c0000 {
1151                         compatible = "qcom,geni-se-qup";
1152                         reg = <0 0x009c0000 0 0x6000>;
1153                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1154                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1155                         clock-names = "m-ahb", "s-ahb";
1156                         iommus = <&apps_smmu 0x563 0>;
1157
1158                         #address-cells = <2>;
1159                         #size-cells = <2>;
1160                         ranges;
1161
1162                         status = "disabled";
1163
1164                         i2c0: i2c@980000 {
1165                                 compatible = "qcom,geni-i2c";
1166                                 reg = <0 0x00980000 0 0x4000>;
1167                                 #address-cells = <1>;
1168                                 #size-cells = <0>;
1169                                 clock-names = "se";
1170                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1171                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1172                                 power-domains = <&rpmhpd SC8280XP_CX>;
1173                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1174                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1175                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1176                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1177                                 status = "disabled";
1178                         };
1179
1180                         spi0: spi@980000 {
1181                                 compatible = "qcom,geni-spi";
1182                                 reg = <0 0x00980000 0 0x4000>;
1183                                 #address-cells = <1>;
1184                                 #size-cells = <0>;
1185                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1186                                 clock-names = "se";
1187                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1188                                 power-domains = <&rpmhpd SC8280XP_CX>;
1189                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1190                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1191                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1192                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1193                                 status = "disabled";
1194                         };
1195
1196                         i2c1: i2c@984000 {
1197                                 compatible = "qcom,geni-i2c";
1198                                 reg = <0 0x00984000 0 0x4000>;
1199                                 #address-cells = <1>;
1200                                 #size-cells = <0>;
1201                                 clock-names = "se";
1202                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1203                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1204                                 power-domains = <&rpmhpd SC8280XP_CX>;
1205                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1207                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209                                 status = "disabled";
1210                         };
1211
1212                         spi1: spi@984000 {
1213                                 compatible = "qcom,geni-spi";
1214                                 reg = <0 0x00984000 0 0x4000>;
1215                                 #address-cells = <1>;
1216                                 #size-cells = <0>;
1217                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1218                                 clock-names = "se";
1219                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1220                                 power-domains = <&rpmhpd SC8280XP_CX>;
1221                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1223                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1224                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1225                                 status = "disabled";
1226                         };
1227
1228                         i2c2: i2c@988000 {
1229                                 compatible = "qcom,geni-i2c";
1230                                 reg = <0 0x00988000 0 0x4000>;
1231                                 #address-cells = <1>;
1232                                 #size-cells = <0>;
1233                                 clock-names = "se";
1234                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1235                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1236                                 power-domains = <&rpmhpd SC8280XP_CX>;
1237                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1239                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1240                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1241                                 status = "disabled";
1242                         };
1243
1244                         spi2: spi@988000 {
1245                                 compatible = "qcom,geni-spi";
1246                                 reg = <0 0x00988000 0 0x4000>;
1247                                 #address-cells = <1>;
1248                                 #size-cells = <0>;
1249                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1250                                 clock-names = "se";
1251                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1252                                 power-domains = <&rpmhpd SC8280XP_CX>;
1253                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1254                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1255                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1256                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1257                                 status = "disabled";
1258                         };
1259
1260                         uart2: serial@988000 {
1261                                 compatible = "qcom,geni-uart";
1262                                 reg = <0 0x00988000 0 0x4000>;
1263                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1264                                 clock-names = "se";
1265                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1266                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1267                                 power-domains = <&rpmhpd SC8280XP_CX>;
1268                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1270                                 interconnect-names = "qup-core", "qup-config";
1271                                 status = "disabled";
1272                         };
1273
1274                         i2c3: i2c@98c000 {
1275                                 compatible = "qcom,geni-i2c";
1276                                 reg = <0 0x0098c000 0 0x4000>;
1277                                 #address-cells = <1>;
1278                                 #size-cells = <0>;
1279                                 clock-names = "se";
1280                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1281                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1282                                 power-domains = <&rpmhpd SC8280XP_CX>;
1283                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1284                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1285                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1286                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1287                                 status = "disabled";
1288                         };
1289
1290                         spi3: spi@98c000 {
1291                                 compatible = "qcom,geni-spi";
1292                                 reg = <0 0x0098c000 0 0x4000>;
1293                                 #address-cells = <1>;
1294                                 #size-cells = <0>;
1295                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1296                                 clock-names = "se";
1297                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1298                                 power-domains = <&rpmhpd SC8280XP_CX>;
1299                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1301                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1302                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1303                                 status = "disabled";
1304                         };
1305
1306                         i2c4: i2c@990000 {
1307                                 compatible = "qcom,geni-i2c";
1308                                 reg = <0 0x00990000 0 0x4000>;
1309                                 clock-names = "se";
1310                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1311                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1312                                 #address-cells = <1>;
1313                                 #size-cells = <0>;
1314                                 power-domains = <&rpmhpd SC8280XP_CX>;
1315                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1316                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1317                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1318                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1319                                 status = "disabled";
1320                         };
1321
1322                         spi4: spi@990000 {
1323                                 compatible = "qcom,geni-spi";
1324                                 reg = <0 0x00990000 0 0x4000>;
1325                                 #address-cells = <1>;
1326                                 #size-cells = <0>;
1327                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1328                                 clock-names = "se";
1329                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1330                                 power-domains = <&rpmhpd SC8280XP_CX>;
1331                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1332                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1333                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1334                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1335                                 status = "disabled";
1336                         };
1337
1338                         i2c5: i2c@994000 {
1339                                 compatible = "qcom,geni-i2c";
1340                                 reg = <0 0x00994000 0 0x4000>;
1341                                 #address-cells = <1>;
1342                                 #size-cells = <0>;
1343                                 clock-names = "se";
1344                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1346                                 power-domains = <&rpmhpd SC8280XP_CX>;
1347                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1348                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1349                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1350                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1351                                 status = "disabled";
1352                         };
1353
1354                         spi5: spi@994000 {
1355                                 compatible = "qcom,geni-spi";
1356                                 reg = <0 0x00994000 0 0x4000>;
1357                                 #address-cells = <1>;
1358                                 #size-cells = <0>;
1359                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1360                                 clock-names = "se";
1361                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1362                                 power-domains = <&rpmhpd SC8280XP_CX>;
1363                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1364                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1365                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1366                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1367                                 status = "disabled";
1368                         };
1369
1370                         i2c6: i2c@998000 {
1371                                 compatible = "qcom,geni-i2c";
1372                                 reg = <0 0x00998000 0 0x4000>;
1373                                 #address-cells = <1>;
1374                                 #size-cells = <0>;
1375                                 clock-names = "se";
1376                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1377                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1378                                 power-domains = <&rpmhpd SC8280XP_CX>;
1379                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1380                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1381                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1382                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1383                                 status = "disabled";
1384                         };
1385
1386                         spi6: spi@998000 {
1387                                 compatible = "qcom,geni-spi";
1388                                 reg = <0 0x00998000 0 0x4000>;
1389                                 #address-cells = <1>;
1390                                 #size-cells = <0>;
1391                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1392                                 clock-names = "se";
1393                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1394                                 power-domains = <&rpmhpd SC8280XP_CX>;
1395                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1396                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1397                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1398                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1399                                 status = "disabled";
1400                         };
1401
1402                         i2c7: i2c@99c000 {
1403                                 compatible = "qcom,geni-i2c";
1404                                 reg = <0 0x0099c000 0 0x4000>;
1405                                 #address-cells = <1>;
1406                                 #size-cells = <0>;
1407                                 clock-names = "se";
1408                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1409                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1410                                 power-domains = <&rpmhpd SC8280XP_CX>;
1411                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1412                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1413                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1414                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1415                                 status = "disabled";
1416                         };
1417
1418                         spi7: spi@99c000 {
1419                                 compatible = "qcom,geni-spi";
1420                                 reg = <0 0x0099c000 0 0x4000>;
1421                                 #address-cells = <1>;
1422                                 #size-cells = <0>;
1423                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1424                                 clock-names = "se";
1425                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1426                                 power-domains = <&rpmhpd SC8280XP_CX>;
1427                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1428                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1429                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1430                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1431                                 status = "disabled";
1432                         };
1433                 };
1434
1435                 qup1: geniqup@ac0000 {
1436                         compatible = "qcom,geni-se-qup";
1437                         reg = <0 0x00ac0000 0 0x6000>;
1438                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1439                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1440                         clock-names = "m-ahb", "s-ahb";
1441                         iommus = <&apps_smmu 0x83 0>;
1442
1443                         #address-cells = <2>;
1444                         #size-cells = <2>;
1445                         ranges;
1446
1447                         status = "disabled";
1448
1449                         i2c8: i2c@a80000 {
1450                                 compatible = "qcom,geni-i2c";
1451                                 reg = <0 0x00a80000 0 0x4000>;
1452                                 #address-cells = <1>;
1453                                 #size-cells = <0>;
1454                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1455                                 clock-names = "se";
1456                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1457                                 power-domains = <&rpmhpd SC8280XP_CX>;
1458                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1459                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1460                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1461                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1462                                 status = "disabled";
1463                         };
1464
1465                         spi8: spi@a80000 {
1466                                 compatible = "qcom,geni-spi";
1467                                 reg = <0 0x00a80000 0 0x4000>;
1468                                 #address-cells = <1>;
1469                                 #size-cells = <0>;
1470                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1471                                 clock-names = "se";
1472                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1473                                 power-domains = <&rpmhpd SC8280XP_CX>;
1474                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1475                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1476                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1477                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1478                                 status = "disabled";
1479                         };
1480
1481                         i2c9: i2c@a84000 {
1482                                 compatible = "qcom,geni-i2c";
1483                                 reg = <0 0x00a84000 0 0x4000>;
1484                                 #address-cells = <1>;
1485                                 #size-cells = <0>;
1486                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1487                                 clock-names = "se";
1488                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1489                                 power-domains = <&rpmhpd SC8280XP_CX>;
1490                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1491                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1492                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1493                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1494                                 status = "disabled";
1495                         };
1496
1497                         spi9: spi@a84000 {
1498                                 compatible = "qcom,geni-spi";
1499                                 reg = <0 0x00a84000 0 0x4000>;
1500                                 #address-cells = <1>;
1501                                 #size-cells = <0>;
1502                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1503                                 clock-names = "se";
1504                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1505                                 power-domains = <&rpmhpd SC8280XP_CX>;
1506                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1507                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1508                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1509                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1510                                 status = "disabled";
1511                         };
1512
1513                         i2c10: i2c@a88000 {
1514                                 compatible = "qcom,geni-i2c";
1515                                 reg = <0 0x00a88000 0 0x4000>;
1516                                 #address-cells = <1>;
1517                                 #size-cells = <0>;
1518                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1519                                 clock-names = "se";
1520                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1521                                 power-domains = <&rpmhpd SC8280XP_CX>;
1522                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1523                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1524                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1525                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1526                                 status = "disabled";
1527                         };
1528
1529                         spi10: spi@a88000 {
1530                                 compatible = "qcom,geni-spi";
1531                                 reg = <0 0x00a88000 0 0x4000>;
1532                                 #address-cells = <1>;
1533                                 #size-cells = <0>;
1534                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1535                                 clock-names = "se";
1536                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1537                                 power-domains = <&rpmhpd SC8280XP_CX>;
1538                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1539                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1540                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1541                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1542                                 status = "disabled";
1543                         };
1544
1545                         i2c11: i2c@a8c000 {
1546                                 compatible = "qcom,geni-i2c";
1547                                 reg = <0 0x00a8c000 0 0x4000>;
1548                                 #address-cells = <1>;
1549                                 #size-cells = <0>;
1550                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1551                                 clock-names = "se";
1552                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1553                                 power-domains = <&rpmhpd SC8280XP_CX>;
1554                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1555                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1556                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1557                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1558                                 status = "disabled";
1559                         };
1560
1561                         spi11: spi@a8c000 {
1562                                 compatible = "qcom,geni-spi";
1563                                 reg = <0 0x00a8c000 0 0x4000>;
1564                                 #address-cells = <1>;
1565                                 #size-cells = <0>;
1566                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1567                                 clock-names = "se";
1568                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1569                                 power-domains = <&rpmhpd SC8280XP_CX>;
1570                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1571                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1572                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1573                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1574                                 status = "disabled";
1575                         };
1576
1577                         i2c12: i2c@a90000 {
1578                                 compatible = "qcom,geni-i2c";
1579                                 reg = <0 0x00a90000 0 0x4000>;
1580                                 #address-cells = <1>;
1581                                 #size-cells = <0>;
1582                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1583                                 clock-names = "se";
1584                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1585                                 power-domains = <&rpmhpd SC8280XP_CX>;
1586                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1587                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1588                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1589                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1590                                 status = "disabled";
1591                         };
1592
1593                         spi12: spi@a90000 {
1594                                 compatible = "qcom,geni-spi";
1595                                 reg = <0 0x00a90000 0 0x4000>;
1596                                 #address-cells = <1>;
1597                                 #size-cells = <0>;
1598                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1599                                 clock-names = "se";
1600                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1601                                 power-domains = <&rpmhpd SC8280XP_CX>;
1602                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1603                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1604                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1605                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1606                                 status = "disabled";
1607                         };
1608
1609                         i2c13: i2c@a94000 {
1610                                 compatible = "qcom,geni-i2c";
1611                                 reg = <0 0x00a94000 0 0x4000>;
1612                                 #address-cells = <1>;
1613                                 #size-cells = <0>;
1614                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1615                                 clock-names = "se";
1616                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1617                                 power-domains = <&rpmhpd SC8280XP_CX>;
1618                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1619                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1620                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1621                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1622                                 status = "disabled";
1623                         };
1624
1625                         spi13: spi@a94000 {
1626                                 compatible = "qcom,geni-spi";
1627                                 reg = <0 0x00a94000 0 0x4000>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1631                                 clock-names = "se";
1632                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1633                                 power-domains = <&rpmhpd SC8280XP_CX>;
1634                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1635                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1636                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1637                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1638                                 status = "disabled";
1639                         };
1640
1641                         i2c14: i2c@a98000 {
1642                                 compatible = "qcom,geni-i2c";
1643                                 reg = <0 0x00a98000 0 0x4000>;
1644                                 #address-cells = <1>;
1645                                 #size-cells = <0>;
1646                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1647                                 clock-names = "se";
1648                                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1649                                 power-domains = <&rpmhpd SC8280XP_CX>;
1650                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1651                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1652                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1653                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1654                                 status = "disabled";
1655                         };
1656
1657                         spi14: spi@a98000 {
1658                                 compatible = "qcom,geni-spi";
1659                                 reg = <0 0x00a98000 0 0x4000>;
1660                                 #address-cells = <1>;
1661                                 #size-cells = <0>;
1662                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1663                                 clock-names = "se";
1664                                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1665                                 power-domains = <&rpmhpd SC8280XP_CX>;
1666                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1667                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1668                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1669                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1670                                 status = "disabled";
1671                         };
1672
1673                         i2c15: i2c@a9c000 {
1674                                 compatible = "qcom,geni-i2c";
1675                                 reg = <0 0x00a9c000 0 0x4000>;
1676                                 #address-cells = <1>;
1677                                 #size-cells = <0>;
1678                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1679                                 clock-names = "se";
1680                                 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1681                                 power-domains = <&rpmhpd SC8280XP_CX>;
1682                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1683                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1684                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1685                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1686                                 status = "disabled";
1687                         };
1688
1689                         spi15: spi@a9c000 {
1690                                 compatible = "qcom,geni-spi";
1691                                 reg = <0 0x00a9c000 0 0x4000>;
1692                                 #address-cells = <1>;
1693                                 #size-cells = <0>;
1694                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1695                                 clock-names = "se";
1696                                 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1697                                 power-domains = <&rpmhpd SC8280XP_CX>;
1698                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1699                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1700                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1701                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1702                                 status = "disabled";
1703                         };
1704                 };
1705
1706                 rng: rng@10d3000 {
1707                         compatible = "qcom,prng-ee";
1708                         reg = <0 0x010d3000 0 0x1000>;
1709                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1710                         clock-names = "core";
1711                 };
1712
1713                 pcie4: pcie@1c00000 {
1714                         device_type = "pci";
1715                         compatible = "qcom,pcie-sc8280xp";
1716                         reg = <0x0 0x01c00000 0x0 0x3000>,
1717                               <0x0 0x30000000 0x0 0xf1d>,
1718                               <0x0 0x30000f20 0x0 0xa8>,
1719                               <0x0 0x30001000 0x0 0x1000>,
1720                               <0x0 0x30100000 0x0 0x100000>,
1721                               <0x0 0x01c03000 0x0 0x1000>;
1722                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1723                         #address-cells = <3>;
1724                         #size-cells = <2>;
1725                         ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1726                                  <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1727                         bus-range = <0x00 0xff>;
1728
1729                         dma-coherent;
1730
1731                         linux,pci-domain = <6>;
1732                         num-lanes = <1>;
1733
1734                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1735                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1736                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1738                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1739
1740                         #interrupt-cells = <1>;
1741                         interrupt-map-mask = <0 0 0 0x7>;
1742                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1743                                         <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1744                                         <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1745                                         <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1746
1747                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1748                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1749                                  <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1750                                  <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1751                                  <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1752                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1753                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1754                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1755                                  <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1756                         clock-names = "aux",
1757                                       "cfg",
1758                                       "bus_master",
1759                                       "bus_slave",
1760                                       "slave_q2a",
1761                                       "ddrss_sf_tbu",
1762                                       "noc_aggr_4",
1763                                       "noc_aggr_south_sf",
1764                                       "cnoc_qx";
1765
1766                         assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1767                         assigned-clock-rates = <19200000>;
1768
1769                         interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1770                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1771                         interconnect-names = "pcie-mem", "cpu-pcie";
1772
1773                         resets = <&gcc GCC_PCIE_4_BCR>;
1774                         reset-names = "pci";
1775
1776                         power-domains = <&gcc PCIE_4_GDSC>;
1777
1778                         phys = <&pcie4_phy>;
1779                         phy-names = "pciephy";
1780
1781                         status = "disabled";
1782                 };
1783
1784                 pcie4_phy: phy@1c06000 {
1785                         compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1786                         reg = <0x0 0x01c06000 0x0 0x2000>;
1787
1788                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1789                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1790                                  <&gcc GCC_PCIE_4_CLKREF_CLK>,
1791                                  <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1792                                  <&gcc GCC_PCIE_4_PIPE_CLK>,
1793                                  <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1794                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1795                                       "pipe", "pipediv2";
1796
1797                         assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1798                         assigned-clock-rates = <100000000>;
1799
1800                         power-domains = <&gcc PCIE_4_GDSC>;
1801
1802                         resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1803                         reset-names = "phy";
1804
1805                         #clock-cells = <0>;
1806                         clock-output-names = "pcie_4_pipe_clk";
1807
1808                         #phy-cells = <0>;
1809
1810                         status = "disabled";
1811                 };
1812
1813                 pcie3b: pcie@1c08000 {
1814                         device_type = "pci";
1815                         compatible = "qcom,pcie-sc8280xp";
1816                         reg = <0x0 0x01c08000 0x0 0x3000>,
1817                               <0x0 0x32000000 0x0 0xf1d>,
1818                               <0x0 0x32000f20 0x0 0xa8>,
1819                               <0x0 0x32001000 0x0 0x1000>,
1820                               <0x0 0x32100000 0x0 0x100000>,
1821                               <0x0 0x01c0b000 0x0 0x1000>;
1822                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1823                         #address-cells = <3>;
1824                         #size-cells = <2>;
1825                         ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1826                                  <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1827                         bus-range = <0x00 0xff>;
1828
1829                         dma-coherent;
1830
1831                         linux,pci-domain = <5>;
1832                         num-lanes = <2>;
1833
1834                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1835                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1836                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1837                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1838                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1839
1840                         #interrupt-cells = <1>;
1841                         interrupt-map-mask = <0 0 0 0x7>;
1842                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1843                                         <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1844                                         <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1845                                         <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1846
1847                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1848                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1849                                  <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1850                                  <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1851                                  <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1852                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1853                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1854                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1855                         clock-names = "aux",
1856                                       "cfg",
1857                                       "bus_master",
1858                                       "bus_slave",
1859                                       "slave_q2a",
1860                                       "ddrss_sf_tbu",
1861                                       "noc_aggr_4",
1862                                       "noc_aggr_south_sf";
1863
1864                         assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1865                         assigned-clock-rates = <19200000>;
1866
1867                         interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1868                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1869                         interconnect-names = "pcie-mem", "cpu-pcie";
1870
1871                         resets = <&gcc GCC_PCIE_3B_BCR>;
1872                         reset-names = "pci";
1873
1874                         power-domains = <&gcc PCIE_3B_GDSC>;
1875
1876                         phys = <&pcie3b_phy>;
1877                         phy-names = "pciephy";
1878
1879                         status = "disabled";
1880                 };
1881
1882                 pcie3b_phy: phy@1c0e000 {
1883                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1884                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1885
1886                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1887                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1888                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1889                                  <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1890                                  <&gcc GCC_PCIE_3B_PIPE_CLK>,
1891                                  <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1892                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1893                                       "pipe", "pipediv2";
1894
1895                         assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1896                         assigned-clock-rates = <100000000>;
1897
1898                         power-domains = <&gcc PCIE_3B_GDSC>;
1899
1900                         resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1901                         reset-names = "phy";
1902
1903                         #clock-cells = <0>;
1904                         clock-output-names = "pcie_3b_pipe_clk";
1905
1906                         #phy-cells = <0>;
1907
1908                         status = "disabled";
1909                 };
1910
1911                 pcie3a: pcie@1c10000 {
1912                         device_type = "pci";
1913                         compatible = "qcom,pcie-sc8280xp";
1914                         reg = <0x0 0x01c10000 0x0 0x3000>,
1915                               <0x0 0x34000000 0x0 0xf1d>,
1916                               <0x0 0x34000f20 0x0 0xa8>,
1917                               <0x0 0x34001000 0x0 0x1000>,
1918                               <0x0 0x34100000 0x0 0x100000>,
1919                               <0x0 0x01c13000 0x0 0x1000>;
1920                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1921                         #address-cells = <3>;
1922                         #size-cells = <2>;
1923                         ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1924                                  <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1925                         bus-range = <0x00 0xff>;
1926
1927                         dma-coherent;
1928
1929                         linux,pci-domain = <4>;
1930                         num-lanes = <4>;
1931
1932                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1933                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1934                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1935                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1936                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1937
1938                         #interrupt-cells = <1>;
1939                         interrupt-map-mask = <0 0 0 0x7>;
1940                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1941                                         <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1942                                         <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1943                                         <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1944
1945                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1946                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1947                                  <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1948                                  <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1949                                  <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1950                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1951                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1952                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1953                         clock-names = "aux",
1954                                       "cfg",
1955                                       "bus_master",
1956                                       "bus_slave",
1957                                       "slave_q2a",
1958                                       "ddrss_sf_tbu",
1959                                       "noc_aggr_4",
1960                                       "noc_aggr_south_sf";
1961
1962                         assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1963                         assigned-clock-rates = <19200000>;
1964
1965                         interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1966                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1967                         interconnect-names = "pcie-mem", "cpu-pcie";
1968
1969                         resets = <&gcc GCC_PCIE_3A_BCR>;
1970                         reset-names = "pci";
1971
1972                         power-domains = <&gcc PCIE_3A_GDSC>;
1973
1974                         phys = <&pcie3a_phy>;
1975                         phy-names = "pciephy";
1976
1977                         status = "disabled";
1978                 };
1979
1980                 pcie3a_phy: phy@1c14000 {
1981                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1982                         reg = <0x0 0x01c14000 0x0 0x2000>,
1983                               <0x0 0x01c16000 0x0 0x2000>;
1984
1985                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1986                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1987                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1988                                  <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
1989                                  <&gcc GCC_PCIE_3A_PIPE_CLK>,
1990                                  <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
1991                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1992                                       "pipe", "pipediv2";
1993
1994                         assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1995                         assigned-clock-rates = <100000000>;
1996
1997                         power-domains = <&gcc PCIE_3A_GDSC>;
1998
1999                         resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2000                         reset-names = "phy";
2001
2002                         qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2003
2004                         #clock-cells = <0>;
2005                         clock-output-names = "pcie_3a_pipe_clk";
2006
2007                         #phy-cells = <0>;
2008
2009                         status = "disabled";
2010                 };
2011
2012                 pcie2b: pcie@1c18000 {
2013                         device_type = "pci";
2014                         compatible = "qcom,pcie-sc8280xp";
2015                         reg = <0x0 0x01c18000 0x0 0x3000>,
2016                               <0x0 0x38000000 0x0 0xf1d>,
2017                               <0x0 0x38000f20 0x0 0xa8>,
2018                               <0x0 0x38001000 0x0 0x1000>,
2019                               <0x0 0x38100000 0x0 0x100000>,
2020                               <0x0 0x01c1b000 0x0 0x1000>;
2021                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2022                         #address-cells = <3>;
2023                         #size-cells = <2>;
2024                         ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2025                                  <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2026                         bus-range = <0x00 0xff>;
2027
2028                         dma-coherent;
2029
2030                         linux,pci-domain = <3>;
2031                         num-lanes = <2>;
2032
2033                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2034                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2035                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2036                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2037                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
2038
2039                         #interrupt-cells = <1>;
2040                         interrupt-map-mask = <0 0 0 0x7>;
2041                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2042                                         <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2043                                         <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2044                                         <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2045
2046                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2047                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2048                                  <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2049                                  <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2050                                  <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2051                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2052                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2053                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2054                         clock-names = "aux",
2055                                       "cfg",
2056                                       "bus_master",
2057                                       "bus_slave",
2058                                       "slave_q2a",
2059                                       "ddrss_sf_tbu",
2060                                       "noc_aggr_4",
2061                                       "noc_aggr_south_sf";
2062
2063                         assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2064                         assigned-clock-rates = <19200000>;
2065
2066                         interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2067                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2068                         interconnect-names = "pcie-mem", "cpu-pcie";
2069
2070                         resets = <&gcc GCC_PCIE_2B_BCR>;
2071                         reset-names = "pci";
2072
2073                         power-domains = <&gcc PCIE_2B_GDSC>;
2074
2075                         phys = <&pcie2b_phy>;
2076                         phy-names = "pciephy";
2077
2078                         status = "disabled";
2079                 };
2080
2081                 pcie2b_phy: phy@1c1e000 {
2082                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2083                         reg = <0x0 0x01c1e000 0x0 0x2000>;
2084
2085                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2086                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2087                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2088                                  <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2089                                  <&gcc GCC_PCIE_2B_PIPE_CLK>,
2090                                  <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2091                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
2092                                       "pipe", "pipediv2";
2093
2094                         assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2095                         assigned-clock-rates = <100000000>;
2096
2097                         power-domains = <&gcc PCIE_2B_GDSC>;
2098
2099                         resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2100                         reset-names = "phy";
2101
2102                         #clock-cells = <0>;
2103                         clock-output-names = "pcie_2b_pipe_clk";
2104
2105                         #phy-cells = <0>;
2106
2107                         status = "disabled";
2108                 };
2109
2110                 pcie2a: pcie@1c20000 {
2111                         device_type = "pci";
2112                         compatible = "qcom,pcie-sc8280xp";
2113                         reg = <0x0 0x01c20000 0x0 0x3000>,
2114                               <0x0 0x3c000000 0x0 0xf1d>,
2115                               <0x0 0x3c000f20 0x0 0xa8>,
2116                               <0x0 0x3c001000 0x0 0x1000>,
2117                               <0x0 0x3c100000 0x0 0x100000>,
2118                               <0x0 0x01c23000 0x0 0x1000>;
2119                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2120                         #address-cells = <3>;
2121                         #size-cells = <2>;
2122                         ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2123                                  <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2124                         bus-range = <0x00 0xff>;
2125
2126                         dma-coherent;
2127
2128                         linux,pci-domain = <2>;
2129                         num-lanes = <4>;
2130
2131                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2132                                      <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2133                                      <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2134                                      <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2135                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
2136
2137                         #interrupt-cells = <1>;
2138                         interrupt-map-mask = <0 0 0 0x7>;
2139                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2140                                         <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2141                                         <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2142                                         <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2143
2144                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2145                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2146                                  <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2147                                  <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2148                                  <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2149                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2150                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2151                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2152                         clock-names = "aux",
2153                                       "cfg",
2154                                       "bus_master",
2155                                       "bus_slave",
2156                                       "slave_q2a",
2157                                       "ddrss_sf_tbu",
2158                                       "noc_aggr_4",
2159                                       "noc_aggr_south_sf";
2160
2161                         assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2162                         assigned-clock-rates = <19200000>;
2163
2164                         interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2165                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2166                         interconnect-names = "pcie-mem", "cpu-pcie";
2167
2168                         resets = <&gcc GCC_PCIE_2A_BCR>;
2169                         reset-names = "pci";
2170
2171                         power-domains = <&gcc PCIE_2A_GDSC>;
2172
2173                         phys = <&pcie2a_phy>;
2174                         phy-names = "pciephy";
2175
2176                         status = "disabled";
2177                 };
2178
2179                 pcie2a_phy: phy@1c24000 {
2180                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2181                         reg = <0x0 0x01c24000 0x0 0x2000>,
2182                               <0x0 0x01c26000 0x0 0x2000>;
2183
2184                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2185                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2186                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2187                                  <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2188                                  <&gcc GCC_PCIE_2A_PIPE_CLK>,
2189                                  <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2190                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
2191                                       "pipe", "pipediv2";
2192
2193                         assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2194                         assigned-clock-rates = <100000000>;
2195
2196                         power-domains = <&gcc PCIE_2A_GDSC>;
2197
2198                         resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2199                         reset-names = "phy";
2200
2201                         qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2202
2203                         #clock-cells = <0>;
2204                         clock-output-names = "pcie_2a_pipe_clk";
2205
2206                         #phy-cells = <0>;
2207
2208                         status = "disabled";
2209                 };
2210
2211                 ufs_mem_hc: ufs@1d84000 {
2212                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2213                                      "jedec,ufs-2.0";
2214                         reg = <0 0x01d84000 0 0x3000>;
2215                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2216                         phys = <&ufs_mem_phy>;
2217                         phy-names = "ufsphy";
2218                         lanes-per-direction = <2>;
2219                         #reset-cells = <1>;
2220                         resets = <&gcc GCC_UFS_PHY_BCR>;
2221                         reset-names = "rst";
2222
2223                         power-domains = <&gcc UFS_PHY_GDSC>;
2224                         required-opps = <&rpmhpd_opp_nom>;
2225
2226                         iommus = <&apps_smmu 0xe0 0x0>;
2227                         dma-coherent;
2228
2229                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2230                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2231                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
2232                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2233                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
2234                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2235                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2236                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2237                         clock-names = "core_clk",
2238                                       "bus_aggr_clk",
2239                                       "iface_clk",
2240                                       "core_clk_unipro",
2241                                       "ref_clk",
2242                                       "tx_lane0_sync_clk",
2243                                       "rx_lane0_sync_clk",
2244                                       "rx_lane1_sync_clk";
2245                         freq-table-hz = <75000000 300000000>,
2246                                         <0 0>,
2247                                         <0 0>,
2248                                         <75000000 300000000>,
2249                                         <0 0>,
2250                                         <0 0>,
2251                                         <0 0>,
2252                                         <0 0>;
2253                         status = "disabled";
2254                 };
2255
2256                 ufs_mem_phy: phy@1d87000 {
2257                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
2258                         reg = <0 0x01d87000 0 0x1000>;
2259
2260                         clocks = <&gcc GCC_UFS_CARD_CLKREF_CLK>,
2261                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
2262                         clock-names = "ref", "ref_aux";
2263
2264                         power-domains = <&gcc UFS_PHY_GDSC>;
2265
2266                         resets = <&ufs_mem_hc 0>;
2267                         reset-names = "ufsphy";
2268
2269                         #phy-cells = <0>;
2270
2271                         status = "disabled";
2272                 };
2273
2274                 ufs_card_hc: ufs@1da4000 {
2275                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2276                                      "jedec,ufs-2.0";
2277                         reg = <0 0x01da4000 0 0x3000>;
2278                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2279                         phys = <&ufs_card_phy>;
2280                         phy-names = "ufsphy";
2281                         lanes-per-direction = <2>;
2282                         #reset-cells = <1>;
2283                         resets = <&gcc GCC_UFS_CARD_BCR>;
2284                         reset-names = "rst";
2285
2286                         power-domains = <&gcc UFS_CARD_GDSC>;
2287
2288                         iommus = <&apps_smmu 0x4a0 0x0>;
2289                         dma-coherent;
2290
2291                         clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2292                                  <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2293                                  <&gcc GCC_UFS_CARD_AHB_CLK>,
2294                                  <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2295                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
2296                                  <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2297                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2298                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2299                         clock-names = "core_clk",
2300                                       "bus_aggr_clk",
2301                                       "iface_clk",
2302                                       "core_clk_unipro",
2303                                       "ref_clk",
2304                                       "tx_lane0_sync_clk",
2305                                       "rx_lane0_sync_clk",
2306                                       "rx_lane1_sync_clk";
2307                         freq-table-hz = <75000000 300000000>,
2308                                         <0 0>,
2309                                         <0 0>,
2310                                         <75000000 300000000>,
2311                                         <0 0>,
2312                                         <0 0>,
2313                                         <0 0>,
2314                                         <0 0>;
2315                         status = "disabled";
2316                 };
2317
2318                 ufs_card_phy: phy@1da7000 {
2319                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
2320                         reg = <0 0x01da7000 0 0x1000>;
2321
2322                         clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>,
2323                                  <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
2324                         clock-names = "ref", "ref_aux";
2325
2326                         power-domains = <&gcc UFS_CARD_GDSC>;
2327
2328                         resets = <&ufs_card_hc 0>;
2329                         reset-names = "ufsphy";
2330
2331                         #phy-cells = <0>;
2332
2333                         status = "disabled";
2334                 };
2335
2336                 tcsr_mutex: hwlock@1f40000 {
2337                         compatible = "qcom,tcsr-mutex";
2338                         reg = <0x0 0x01f40000 0x0 0x20000>;
2339                         #hwlock-cells = <1>;
2340                 };
2341
2342                 tcsr: syscon@1fc0000 {
2343                         compatible = "qcom,sc8280xp-tcsr", "syscon";
2344                         reg = <0x0 0x01fc0000 0x0 0x30000>;
2345                 };
2346
2347                 gpu: gpu@3d00000 {
2348                         compatible = "qcom,adreno-690.0", "qcom,adreno";
2349
2350                         reg = <0 0x03d00000 0 0x40000>,
2351                               <0 0x03d9e000 0 0x1000>,
2352                               <0 0x03d61000 0 0x800>;
2353                         reg-names = "kgsl_3d0_reg_memory",
2354                                     "cx_mem",
2355                                     "cx_dbgc";
2356                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2357                         iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2358                         operating-points-v2 = <&gpu_opp_table>;
2359
2360                         qcom,gmu = <&gmu>;
2361                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2362                         interconnect-names = "gfx-mem";
2363                         #cooling-cells = <2>;
2364
2365                         status = "disabled";
2366
2367                         gpu_opp_table: opp-table {
2368                                 compatible = "operating-points-v2";
2369
2370                                 opp-270000000 {
2371                                         opp-hz = /bits/ 64 <270000000>;
2372                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2373                                         opp-peak-kBps = <451000>;
2374                                 };
2375
2376                                 opp-410000000 {
2377                                         opp-hz = /bits/ 64 <410000000>;
2378                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2379                                         opp-peak-kBps = <1555000>;
2380                                 };
2381
2382                                 opp-500000000 {
2383                                         opp-hz = /bits/ 64 <500000000>;
2384                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2385                                         opp-peak-kBps = <1555000>;
2386                                 };
2387
2388                                 opp-547000000 {
2389                                         opp-hz = /bits/ 64 <547000000>;
2390                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2391                                         opp-peak-kBps = <1555000>;
2392                                 };
2393
2394                                 opp-606000000 {
2395                                         opp-hz = /bits/ 64 <606000000>;
2396                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2397                                         opp-peak-kBps = <2736000>;
2398                                 };
2399
2400                                 opp-640000000 {
2401                                         opp-hz = /bits/ 64 <640000000>;
2402                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2403                                         opp-peak-kBps = <2736000>;
2404                                 };
2405
2406                                 opp-655000000 {
2407                                         opp-hz = /bits/ 64 <655000000>;
2408                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2409                                         opp-peak-kBps = <2736000>;
2410                                 };
2411
2412                                 opp-690000000 {
2413                                         opp-hz = /bits/ 64 <690000000>;
2414                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2415                                         opp-peak-kBps = <2736000>;
2416                                 };
2417                         };
2418                 };
2419
2420                 gmu: gmu@3d6a000 {
2421                         compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2422                         reg = <0 0x03d6a000 0 0x34000>,
2423                               <0 0x03de0000 0 0x10000>,
2424                               <0 0x0b290000 0 0x10000>;
2425                         reg-names = "gmu", "rscc", "gmu_pdc";
2426                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2427                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2428                         interrupt-names = "hfi", "gmu";
2429                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2430                                  <&gpucc GPU_CC_CXO_CLK>,
2431                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2432                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2433                                  <&gpucc GPU_CC_AHB_CLK>,
2434                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2435                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2436                         clock-names = "gmu",
2437                                       "cxo",
2438                                       "axi",
2439                                       "memnoc",
2440                                       "ahb",
2441                                       "hub",
2442                                       "smmu_vote";
2443                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2444                                         <&gpucc GPU_CC_GX_GDSC>;
2445                         power-domain-names = "cx",
2446                                              "gx";
2447                         iommus = <&gpu_smmu 5 0xc00>;
2448                         operating-points-v2 = <&gmu_opp_table>;
2449
2450                         gmu_opp_table: opp-table {
2451                                 compatible = "operating-points-v2";
2452
2453                                 opp-200000000 {
2454                                         opp-hz = /bits/ 64 <200000000>;
2455                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2456                                 };
2457
2458                                 opp-500000000 {
2459                                         opp-hz = /bits/ 64 <500000000>;
2460                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2461                                 };
2462                         };
2463                 };
2464
2465                 gpucc: clock-controller@3d90000 {
2466                         compatible = "qcom,sc8280xp-gpucc";
2467                         reg = <0 0x03d90000 0 0x9000>;
2468                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2469                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2470                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2471                         clock-names = "bi_tcxo",
2472                                       "gcc_gpu_gpll0_clk_src",
2473                                       "gcc_gpu_gpll0_div_clk_src";
2474
2475                         power-domains = <&rpmhpd SC8280XP_GFX>;
2476                         #clock-cells = <1>;
2477                         #reset-cells = <1>;
2478                         #power-domain-cells = <1>;
2479                 };
2480
2481                 gpu_smmu: iommu@3da0000 {
2482                         compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2483                                      "qcom,smmu-500", "arm,mmu-500";
2484                         reg = <0 0x03da0000 0 0x20000>;
2485                         #iommu-cells = <2>;
2486                         #global-interrupts = <2>;
2487                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2488                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2489                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2490                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2491                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2492                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2493                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2494                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2495                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2496                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2497                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2498                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2499                                      <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
2500                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
2501
2502                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2503                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2504                                  <&gpucc GPU_CC_AHB_CLK>,
2505                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2506                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2507                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2508                                  <&gpucc GPU_CC_HUB_AON_CLK>;
2509                         clock-names = "gcc_gpu_memnoc_gfx_clk",
2510                                       "gcc_gpu_snoc_dvm_gfx_clk",
2511                                       "gpu_cc_ahb_clk",
2512                                       "gpu_cc_hlos1_vote_gpu_smmu_clk",
2513                                       "gpu_cc_cx_gmu_clk",
2514                                       "gpu_cc_hub_cx_int_clk",
2515                                       "gpu_cc_hub_aon_clk";
2516
2517                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2518                         dma-coherent;
2519                 };
2520
2521                 usb_0_hsphy: phy@88e5000 {
2522                         compatible = "qcom,sc8280xp-usb-hs-phy",
2523                                      "qcom,usb-snps-hs-5nm-phy";
2524                         reg = <0 0x088e5000 0 0x400>;
2525                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2526                         clock-names = "ref";
2527                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2528
2529                         #phy-cells = <0>;
2530
2531                         status = "disabled";
2532                 };
2533
2534                 usb_2_hsphy0: phy@88e7000 {
2535                         compatible = "qcom,sc8280xp-usb-hs-phy",
2536                                      "qcom,usb-snps-hs-5nm-phy";
2537                         reg = <0 0x088e7000 0 0x400>;
2538                         clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2539                         clock-names = "ref";
2540                         resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2541
2542                         #phy-cells = <0>;
2543
2544                         status = "disabled";
2545                 };
2546
2547                 usb_2_hsphy1: phy@88e8000 {
2548                         compatible = "qcom,sc8280xp-usb-hs-phy",
2549                                      "qcom,usb-snps-hs-5nm-phy";
2550                         reg = <0 0x088e8000 0 0x400>;
2551                         clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2552                         clock-names = "ref";
2553                         resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2554
2555                         #phy-cells = <0>;
2556
2557                         status = "disabled";
2558                 };
2559
2560                 usb_2_hsphy2: phy@88e9000 {
2561                         compatible = "qcom,sc8280xp-usb-hs-phy",
2562                                      "qcom,usb-snps-hs-5nm-phy";
2563                         reg = <0 0x088e9000 0 0x400>;
2564                         clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2565                         clock-names = "ref";
2566                         resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2567
2568                         #phy-cells = <0>;
2569
2570                         status = "disabled";
2571                 };
2572
2573                 usb_2_hsphy3: phy@88ea000 {
2574                         compatible = "qcom,sc8280xp-usb-hs-phy",
2575                                      "qcom,usb-snps-hs-5nm-phy";
2576                         reg = <0 0x088ea000 0 0x400>;
2577                         clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2578                         clock-names = "ref";
2579                         resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2580
2581                         #phy-cells = <0>;
2582
2583                         status = "disabled";
2584                 };
2585
2586                 usb_2_qmpphy0: phy@88ef000 {
2587                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2588                         reg = <0 0x088ef000 0 0x2000>;
2589
2590                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2591                                  <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2592                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2593                                  <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2594                         clock-names = "aux", "ref", "com_aux", "pipe";
2595
2596                         resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2597                                  <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2598                         reset-names = "phy", "phy_phy";
2599
2600                         power-domains = <&gcc USB30_MP_GDSC>;
2601
2602                         #clock-cells = <0>;
2603                         clock-output-names = "usb2_phy0_pipe_clk";
2604
2605                         #phy-cells = <0>;
2606
2607                         status = "disabled";
2608                 };
2609
2610                 usb_2_qmpphy1: phy@88f1000 {
2611                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2612                         reg = <0 0x088f1000 0 0x2000>;
2613
2614                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2615                                  <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2616                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2617                                  <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2618                         clock-names = "aux", "ref", "com_aux", "pipe";
2619
2620                         resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2621                                  <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2622                         reset-names = "phy", "phy_phy";
2623
2624                         power-domains = <&gcc USB30_MP_GDSC>;
2625
2626                         #clock-cells = <0>;
2627                         clock-output-names = "usb2_phy1_pipe_clk";
2628
2629                         #phy-cells = <0>;
2630
2631                         status = "disabled";
2632                 };
2633
2634                 remoteproc_adsp: remoteproc@3000000 {
2635                         compatible = "qcom,sc8280xp-adsp-pas";
2636                         reg = <0 0x03000000 0 0x100>;
2637
2638                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2639                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2640                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2641                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2642                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2643                                               <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2644                         interrupt-names = "wdog", "fatal", "ready",
2645                                           "handover", "stop-ack", "shutdown-ack";
2646
2647                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2648                         clock-names = "xo";
2649
2650                         power-domains = <&rpmhpd SC8280XP_LCX>,
2651                                         <&rpmhpd SC8280XP_LMX>;
2652                         power-domain-names = "lcx", "lmx";
2653
2654                         memory-region = <&pil_adsp_mem>;
2655
2656                         qcom,qmp = <&aoss_qmp>;
2657
2658                         qcom,smem-states = <&smp2p_adsp_out 0>;
2659                         qcom,smem-state-names = "stop";
2660
2661                         status = "disabled";
2662
2663                         remoteproc_adsp_glink: glink-edge {
2664                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2665                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2666                                                              IRQ_TYPE_EDGE_RISING>;
2667                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2668                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2669
2670                                 label = "lpass";
2671                                 qcom,remote-pid = <2>;
2672
2673                                 gpr {
2674                                         compatible = "qcom,gpr";
2675                                         qcom,glink-channels = "adsp_apps";
2676                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2677                                         qcom,intents = <512 20>;
2678                                         #address-cells = <1>;
2679                                         #size-cells = <0>;
2680
2681                                         q6apm: service@1 {
2682                                                 compatible = "qcom,q6apm";
2683                                                 reg = <GPR_APM_MODULE_IID>;
2684                                                 #sound-dai-cells = <0>;
2685                                                 qcom,protection-domain = "avs/audio",
2686                                                                          "msm/adsp/audio_pd";
2687                                                 q6apmdai: dais {
2688                                                         compatible = "qcom,q6apm-dais";
2689                                                         iommus = <&apps_smmu 0x0c01 0x0>;
2690                                                 };
2691
2692                                                 q6apmbedai: bedais {
2693                                                         compatible = "qcom,q6apm-lpass-dais";
2694                                                         #sound-dai-cells = <1>;
2695                                                 };
2696                                         };
2697
2698                                         q6prm: service@2 {
2699                                                 compatible = "qcom,q6prm";
2700                                                 reg = <GPR_PRM_MODULE_IID>;
2701                                                 qcom,protection-domain = "avs/audio",
2702                                                                          "msm/adsp/audio_pd";
2703                                                 q6prmcc: clock-controller {
2704                                                         compatible = "qcom,q6prm-lpass-clocks";
2705                                                         #clock-cells = <2>;
2706                                                 };
2707                                         };
2708                                 };
2709                         };
2710                 };
2711
2712                 rxmacro: rxmacro@3200000 {
2713                         compatible = "qcom,sc8280xp-lpass-rx-macro";
2714                         reg = <0 0x03200000 0 0x1000>;
2715                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2716                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2717                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2718                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2719                                  <&vamacro>;
2720                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2721                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2722                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2723                         assigned-clock-rates = <19200000>, <19200000>;
2724
2725                         clock-output-names = "mclk";
2726                         #clock-cells = <0>;
2727                         #sound-dai-cells = <1>;
2728
2729                         pinctrl-names = "default";
2730                         pinctrl-0 = <&rx_swr_default>;
2731
2732                         status = "disabled";
2733                 };
2734
2735                 swr1: soundwire@3210000 {
2736                         compatible = "qcom,soundwire-v1.6.0";
2737                         reg = <0 0x03210000 0 0x2000>;
2738                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2739                         clocks = <&rxmacro>;
2740                         clock-names = "iface";
2741                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2742                         reset-names = "swr_audio_cgcr";
2743                         label = "RX";
2744
2745                         qcom,din-ports = <0>;
2746                         qcom,dout-ports = <5>;
2747
2748                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2749                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2750                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2751                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2752                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2753                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2754                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2755                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2756                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2757
2758                         #sound-dai-cells = <1>;
2759                         #address-cells = <2>;
2760                         #size-cells = <0>;
2761
2762                         status = "disabled";
2763                 };
2764
2765                 txmacro: txmacro@3220000 {
2766                         compatible = "qcom,sc8280xp-lpass-tx-macro";
2767                         reg = <0 0x03220000 0 0x1000>;
2768                         pinctrl-names = "default";
2769                         pinctrl-0 = <&tx_swr_default>;
2770                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2771                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2772                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2773                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2774                                  <&vamacro>;
2775
2776                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2777                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2778                                           <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2779                         assigned-clock-rates = <19200000>, <19200000>;
2780                         clock-output-names = "mclk";
2781
2782                         #clock-cells = <0>;
2783                         #sound-dai-cells = <1>;
2784
2785                         status = "disabled";
2786                 };
2787
2788                 wsamacro: codec@3240000 {
2789                         compatible = "qcom,sc8280xp-lpass-wsa-macro";
2790                         reg = <0 0x03240000 0 0x1000>;
2791                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2792                                  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2793                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2794                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2795                                  <&vamacro>;
2796                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2797                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2798                                           <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2799                         assigned-clock-rates = <19200000>, <19200000>;
2800
2801                         #clock-cells = <0>;
2802                         clock-output-names = "mclk";
2803                         #sound-dai-cells = <1>;
2804
2805                         pinctrl-names = "default";
2806                         pinctrl-0 = <&wsa_swr_default>;
2807
2808                         status = "disabled";
2809                 };
2810
2811                 swr0: soundwire@3250000 {
2812                         reg = <0 0x03250000 0 0x2000>;
2813                         compatible = "qcom,soundwire-v1.6.0";
2814                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2815                         clocks = <&wsamacro>;
2816                         clock-names = "iface";
2817                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
2818                         reset-names = "swr_audio_cgcr";
2819                         label = "WSA";
2820
2821                         qcom,din-ports = <2>;
2822                         qcom,dout-ports = <6>;
2823
2824                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2825                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2826                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2827                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2828                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2829                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2830                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2831                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2832                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2833
2834                         #sound-dai-cells = <1>;
2835                         #address-cells = <2>;
2836                         #size-cells = <0>;
2837
2838                         status = "disabled";
2839                 };
2840
2841                 lpass_audiocc: clock-controller@32a9000 {
2842                         compatible = "qcom,sc8280xp-lpassaudiocc";
2843                         reg = <0 0x032a9000 0 0x1000>;
2844                         #clock-cells = <1>;
2845                         #reset-cells = <1>;
2846                 };
2847
2848                 swr2: soundwire@3330000 {
2849                         compatible = "qcom,soundwire-v1.6.0";
2850                         reg = <0 0x03330000 0 0x2000>;
2851                         interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2852                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2853                         interrupt-names = "core", "wakeup";
2854
2855                         clocks = <&txmacro>;
2856                         clock-names = "iface";
2857                         resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
2858                         reset-names = "swr_audio_cgcr";
2859                         label = "TX";
2860                         #sound-dai-cells = <1>;
2861                         #address-cells = <2>;
2862                         #size-cells = <0>;
2863
2864                         qcom,din-ports = <4>;
2865                         qcom,dout-ports = <0>;
2866                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2867                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x00 0x02 0x00>;
2868                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2869                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2870                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2871                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2872                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2873                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2874                         qcom,ports-lane-control =       /bits/ 8 <0x00 0x01 0x00 0x01>;
2875
2876                         status = "disabled";
2877                 };
2878
2879                 vamacro: codec@3370000 {
2880                         compatible = "qcom,sc8280xp-lpass-va-macro";
2881                         reg = <0 0x03370000 0 0x1000>;
2882                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2883                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2884                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2885                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2886                         clock-names = "mclk", "macro", "dcodec", "npl";
2887                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2888                         assigned-clock-rates = <19200000>;
2889
2890                         #clock-cells = <0>;
2891                         clock-output-names = "fsgen";
2892                         #sound-dai-cells = <1>;
2893
2894                         status = "disabled";
2895                 };
2896
2897                 lpass_tlmm: pinctrl@33c0000 {
2898                         compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2899                         reg = <0 0x33c0000 0x0 0x20000>,
2900                               <0 0x3550000 0x0 0x10000>;
2901                         gpio-controller;
2902                         #gpio-cells = <2>;
2903                         gpio-ranges = <&lpass_tlmm 0 0 19>;
2904
2905                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2906                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2907                         clock-names = "core", "audio";
2908
2909                         status = "disabled";
2910
2911                         tx_swr_default: tx-swr-default-state {
2912                                 clk-pins {
2913                                         pins = "gpio0";
2914                                         function = "swr_tx_clk";
2915                                         drive-strength = <2>;
2916                                         slew-rate = <1>;
2917                                         bias-disable;
2918                                 };
2919
2920                                 data-pins {
2921                                         pins = "gpio1", "gpio2";
2922                                         function = "swr_tx_data";
2923                                         drive-strength = <2>;
2924                                         slew-rate = <1>;
2925                                         bias-bus-hold;
2926                                 };
2927                         };
2928
2929                         rx_swr_default: rx-swr-default-state {
2930                                 clk-pins {
2931                                         pins = "gpio3";
2932                                         function = "swr_rx_clk";
2933                                         drive-strength = <2>;
2934                                         slew-rate = <1>;
2935                                         bias-disable;
2936                                 };
2937
2938                                 data-pins {
2939                                         pins = "gpio4", "gpio5";
2940                                         function = "swr_rx_data";
2941                                         drive-strength = <2>;
2942                                         slew-rate = <1>;
2943                                         bias-bus-hold;
2944                                 };
2945                         };
2946
2947                         dmic01_default: dmic01-default-state {
2948                                 clk-pins {
2949                                         pins = "gpio6";
2950                                         function = "dmic1_clk";
2951                                         drive-strength = <8>;
2952                                         output-high;
2953                                 };
2954
2955                                 data-pins {
2956                                         pins = "gpio7";
2957                                         function = "dmic1_data";
2958                                         drive-strength = <8>;
2959                                         input-enable;
2960                                 };
2961                         };
2962
2963                         dmic01_sleep: dmic01-sleep-state {
2964                                 clk-pins {
2965                                         pins = "gpio6";
2966                                         function = "dmic1_clk";
2967                                         drive-strength = <2>;
2968                                         bias-disable;
2969                                         output-low;
2970                                 };
2971
2972                                 data-pins {
2973                                         pins = "gpio7";
2974                                         function = "dmic1_data";
2975                                         drive-strength = <2>;
2976                                         bias-pull-down;
2977                                         input-enable;
2978                                 };
2979                         };
2980
2981                         dmic02_default: dmic02-default-state {
2982                                 clk-pins {
2983                                         pins = "gpio8";
2984                                         function = "dmic2_clk";
2985                                         drive-strength = <8>;
2986                                         output-high;
2987                                 };
2988
2989                                 data-pins {
2990                                         pins = "gpio9";
2991                                         function = "dmic2_data";
2992                                         drive-strength = <8>;
2993                                         input-enable;
2994                                 };
2995                         };
2996
2997                         dmic02_sleep: dmic02-sleep-state {
2998                                 clk-pins {
2999                                         pins = "gpio8";
3000                                         function = "dmic2_clk";
3001                                         drive-strength = <2>;
3002                                         bias-disable;
3003                                         output-low;
3004                                 };
3005
3006                                 data-pins {
3007                                         pins = "gpio9";
3008                                         function = "dmic2_data";
3009                                         drive-strength = <2>;
3010                                         bias-pull-down;
3011                                         input-enable;
3012                                 };
3013                         };
3014
3015                         wsa_swr_default: wsa-swr-default-state {
3016                                 clk-pins {
3017                                         pins = "gpio10";
3018                                         function = "wsa_swr_clk";
3019                                         drive-strength = <2>;
3020                                         slew-rate = <1>;
3021                                         bias-disable;
3022                                 };
3023
3024                                 data-pins {
3025                                         pins = "gpio11";
3026                                         function = "wsa_swr_data";
3027                                         drive-strength = <2>;
3028                                         slew-rate = <1>;
3029                                         bias-bus-hold;
3030                                 };
3031                         };
3032
3033                         wsa2_swr_default: wsa2-swr-default-state {
3034                                 clk-pins {
3035                                         pins = "gpio15";
3036                                         function = "wsa2_swr_clk";
3037                                         drive-strength = <2>;
3038                                         slew-rate = <1>;
3039                                         bias-disable;
3040                                 };
3041
3042                                 data-pins {
3043                                         pins = "gpio16";
3044                                         function = "wsa2_swr_data";
3045                                         drive-strength = <2>;
3046                                         slew-rate = <1>;
3047                                         bias-bus-hold;
3048                                 };
3049                         };
3050                 };
3051
3052                 lpasscc: clock-controller@33e0000 {
3053                         compatible = "qcom,sc8280xp-lpasscc";
3054                         reg = <0 0x033e0000 0 0x12000>;
3055                         #clock-cells = <1>;
3056                         #reset-cells = <1>;
3057                 };
3058
3059                 sdc2: mmc@8804000 {
3060                         compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3061                         reg = <0 0x08804000 0 0x1000>;
3062
3063                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3064                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3065                         interrupt-names = "hc_irq", "pwr_irq";
3066
3067                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3068                                  <&gcc GCC_SDCC2_APPS_CLK>,
3069                                  <&rpmhcc RPMH_CXO_CLK>;
3070                         clock-names = "iface", "core", "xo";
3071                         resets = <&gcc GCC_SDCC2_BCR>;
3072                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3073                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3074                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3075                         iommus = <&apps_smmu 0x4e0 0x0>;
3076                         power-domains = <&rpmhpd SC8280XP_CX>;
3077                         operating-points-v2 = <&sdc2_opp_table>;
3078                         bus-width = <4>;
3079                         dma-coherent;
3080
3081                         status = "disabled";
3082
3083                         sdc2_opp_table: opp-table {
3084                                 compatible = "operating-points-v2";
3085
3086                                 opp-100000000 {
3087                                         opp-hz = /bits/ 64 <100000000>;
3088                                         required-opps = <&rpmhpd_opp_low_svs>;
3089                                         opp-peak-kBps = <1800000 400000>;
3090                                         opp-avg-kBps = <100000 0>;
3091                                 };
3092
3093                                 opp-202000000 {
3094                                         opp-hz = /bits/ 64 <202000000>;
3095                                         required-opps = <&rpmhpd_opp_svs_l1>;
3096                                         opp-peak-kBps = <5400000 1600000>;
3097                                         opp-avg-kBps = <200000 0>;
3098                                 };
3099                         };
3100                 };
3101
3102                 usb_0_qmpphy: phy@88eb000 {
3103                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3104                         reg = <0 0x088eb000 0 0x4000>;
3105
3106                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3107                                  <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3108                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3109                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3110                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3111
3112                         power-domains = <&gcc USB30_PRIM_GDSC>;
3113
3114                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3115                                  <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3116                         reset-names = "phy", "common";
3117
3118                         #clock-cells = <1>;
3119                         #phy-cells = <1>;
3120
3121                         status = "disabled";
3122
3123                         ports {
3124                                 #address-cells = <1>;
3125                                 #size-cells = <0>;
3126
3127                                 port@0 {
3128                                         reg = <0>;
3129
3130                                         usb_0_qmpphy_out: endpoint {};
3131                                 };
3132
3133                                 port@2 {
3134                                         reg = <2>;
3135
3136                                         usb_0_qmpphy_dp_in: endpoint {};
3137                                 };
3138                         };
3139                 };
3140
3141                 usb_1_hsphy: phy@8902000 {
3142                         compatible = "qcom,sc8280xp-usb-hs-phy",
3143                                      "qcom,usb-snps-hs-5nm-phy";
3144                         reg = <0 0x08902000 0 0x400>;
3145                         #phy-cells = <0>;
3146
3147                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3148                         clock-names = "ref";
3149
3150                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3151
3152                         status = "disabled";
3153                 };
3154
3155                 usb_1_qmpphy: phy@8903000 {
3156                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3157                         reg = <0 0x08903000 0 0x4000>;
3158
3159                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3160                                  <&gcc GCC_USB4_CLKREF_CLK>,
3161                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3162                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3163                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3164
3165                         power-domains = <&gcc USB30_SEC_GDSC>;
3166
3167                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3168                                  <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3169                         reset-names = "phy", "common";
3170
3171                         #clock-cells = <1>;
3172                         #phy-cells = <1>;
3173
3174                         status = "disabled";
3175
3176                         ports {
3177                                 #address-cells = <1>;
3178                                 #size-cells = <0>;
3179
3180                                 port@0 {
3181                                         reg = <0>;
3182
3183                                         usb_1_qmpphy_out: endpoint {};
3184                                 };
3185
3186                                 port@2 {
3187                                         reg = <2>;
3188
3189                                         usb_1_qmpphy_dp_in: endpoint {};
3190                                 };
3191                         };
3192                 };
3193
3194                 mdss1_dp0_phy: phy@8909a00 {
3195                         compatible = "qcom,sc8280xp-dp-phy";
3196                         reg = <0 0x08909a00 0 0x19c>,
3197                               <0 0x08909200 0 0xec>,
3198                               <0 0x08909600 0 0xec>,
3199                               <0 0x08909000 0 0x1c8>;
3200
3201                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3202                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3203                         clock-names = "aux", "cfg_ahb";
3204                         power-domains = <&rpmhpd SC8280XP_MX>;
3205
3206                         #clock-cells = <1>;
3207                         #phy-cells = <0>;
3208
3209                         status = "disabled";
3210                 };
3211
3212                 mdss1_dp1_phy: phy@890ca00 {
3213                         compatible = "qcom,sc8280xp-dp-phy";
3214                         reg = <0 0x0890ca00 0 0x19c>,
3215                               <0 0x0890c200 0 0xec>,
3216                               <0 0x0890c600 0 0xec>,
3217                               <0 0x0890c000 0 0x1c8>;
3218
3219                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3220                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3221                         clock-names = "aux", "cfg_ahb";
3222                         power-domains = <&rpmhpd SC8280XP_MX>;
3223
3224                         #clock-cells = <1>;
3225                         #phy-cells = <0>;
3226
3227                         status = "disabled";
3228                 };
3229
3230                 pmu@9091000 {
3231                         compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3232                         reg = <0 0x09091000 0 0x1000>;
3233
3234                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3235
3236                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3237
3238                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3239
3240                         llcc_bwmon_opp_table: opp-table {
3241                                 compatible = "operating-points-v2";
3242
3243                                 opp-0 {
3244                                         opp-peak-kBps = <762000>;
3245                                 };
3246                                 opp-1 {
3247                                         opp-peak-kBps = <1720000>;
3248                                 };
3249                                 opp-2 {
3250                                         opp-peak-kBps = <2086000>;
3251                                 };
3252                                 opp-3 {
3253                                         opp-peak-kBps = <2597000>;
3254                                 };
3255                                 opp-4 {
3256                                         opp-peak-kBps = <2929000>;
3257                                 };
3258                                 opp-5 {
3259                                         opp-peak-kBps = <3879000>;
3260                                 };
3261                                 opp-6 {
3262                                         opp-peak-kBps = <5161000>;
3263                                 };
3264                                 opp-7 {
3265                                         opp-peak-kBps = <5931000>;
3266                                 };
3267                                 opp-8 {
3268                                         opp-peak-kBps = <6515000>;
3269                                 };
3270                                 opp-9 {
3271                                         opp-peak-kBps = <7980000>;
3272                                 };
3273                                 opp-10 {
3274                                         opp-peak-kBps = <8136000>;
3275                                 };
3276                                 opp-11 {
3277                                         opp-peak-kBps = <10437000>;
3278                                 };
3279                                 opp-12 {
3280                                         opp-peak-kBps = <12191000>;
3281                                 };
3282                         };
3283                 };
3284
3285                 pmu@90b6400 {
3286                         compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3287                         reg = <0 0x090b6400 0 0x600>;
3288
3289                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3290
3291                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3292                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3293
3294                         cpu_bwmon_opp_table: opp-table {
3295                                 compatible = "operating-points-v2";
3296
3297                                 opp-0 {
3298                                         opp-peak-kBps = <2288000>;
3299                                 };
3300                                 opp-1 {
3301                                         opp-peak-kBps = <4577000>;
3302                                 };
3303                                 opp-2 {
3304                                         opp-peak-kBps = <7110000>;
3305                                 };
3306                                 opp-3 {
3307                                         opp-peak-kBps = <9155000>;
3308                                 };
3309                                 opp-4 {
3310                                         opp-peak-kBps = <12298000>;
3311                                 };
3312                                 opp-5 {
3313                                         opp-peak-kBps = <14236000>;
3314                                 };
3315                                 opp-6 {
3316                                         opp-peak-kBps = <15258001>;
3317                                 };
3318                         };
3319                 };
3320
3321                 system-cache-controller@9200000 {
3322                         compatible = "qcom,sc8280xp-llcc";
3323                         reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3324                               <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3325                               <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3326                               <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3327                               <0 0x09600000 0 0x58000>;
3328                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3329                                     "llcc3_base", "llcc4_base", "llcc5_base",
3330                                     "llcc6_base", "llcc7_base",  "llcc_broadcast_base";
3331                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3332                 };
3333
3334                 usb_0: usb@a6f8800 {
3335                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3336                         reg = <0 0x0a6f8800 0 0x400>;
3337                         #address-cells = <2>;
3338                         #size-cells = <2>;
3339                         ranges;
3340
3341                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3342                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3343                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3344                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3345                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3346                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3347                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3348                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3349                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3350                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3351                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3352
3353                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3354                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3355                         assigned-clock-rates = <19200000>, <200000000>;
3356
3357                         interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3358                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3359                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3360                                               <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3361                         interrupt-names = "pwr_event",
3362                                           "dp_hs_phy_irq",
3363                                           "dm_hs_phy_irq",
3364                                           "ss_phy_irq";
3365
3366                         power-domains = <&gcc USB30_PRIM_GDSC>;
3367                         required-opps = <&rpmhpd_opp_nom>;
3368
3369                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3370
3371                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3372                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3373                         interconnect-names = "usb-ddr", "apps-usb";
3374
3375                         wakeup-source;
3376
3377                         status = "disabled";
3378
3379                         usb_0_dwc3: usb@a600000 {
3380                                 compatible = "snps,dwc3";
3381                                 reg = <0 0x0a600000 0 0xcd00>;
3382                                 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3383                                 iommus = <&apps_smmu 0x820 0x0>;
3384                                 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3385                                 phy-names = "usb2-phy", "usb3-phy";
3386
3387                                 port {
3388                                         usb_0_role_switch: endpoint {
3389                                         };
3390                                 };
3391                         };
3392                 };
3393
3394                 usb_1: usb@a8f8800 {
3395                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3396                         reg = <0 0x0a8f8800 0 0x400>;
3397                         #address-cells = <2>;
3398                         #size-cells = <2>;
3399                         ranges;
3400
3401                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3402                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3403                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3404                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3405                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3406                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3407                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3408                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3409                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3410                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3411                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3412
3413                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3414                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3415                         assigned-clock-rates = <19200000>, <200000000>;
3416
3417                         interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3418                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3419                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3420                                               <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3421                         interrupt-names = "pwr_event",
3422                                           "dp_hs_phy_irq",
3423                                           "dm_hs_phy_irq",
3424                                           "ss_phy_irq";
3425
3426                         power-domains = <&gcc USB30_SEC_GDSC>;
3427                         required-opps = <&rpmhpd_opp_nom>;
3428
3429                         resets = <&gcc GCC_USB30_SEC_BCR>;
3430
3431                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3432                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3433                         interconnect-names = "usb-ddr", "apps-usb";
3434
3435                         wakeup-source;
3436
3437                         status = "disabled";
3438
3439                         usb_1_dwc3: usb@a800000 {
3440                                 compatible = "snps,dwc3";
3441                                 reg = <0 0x0a800000 0 0xcd00>;
3442                                 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3443                                 iommus = <&apps_smmu 0x860 0x0>;
3444                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3445                                 phy-names = "usb2-phy", "usb3-phy";
3446
3447                                 port {
3448                                         usb_1_role_switch: endpoint {
3449                                         };
3450                                 };
3451                         };
3452                 };
3453
3454                 camcc: clock-controller@ad00000 {
3455                         compatible = "qcom,sc8280xp-camcc";
3456                         reg = <0 0x0ad00000 0 0x20000>;
3457                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3458                                  <&rpmhcc RPMH_CXO_CLK>,
3459                                  <&rpmhcc RPMH_CXO_CLK_A>,
3460                                  <&sleep_clk>;
3461                         power-domains = <&rpmhpd SC8280XP_MMCX>;
3462                         required-opps = <&rpmhpd_opp_low_svs>;
3463                         #clock-cells = <1>;
3464                         #reset-cells = <1>;
3465                         #power-domain-cells = <1>;
3466                 };
3467
3468                 mdss0: display-subsystem@ae00000 {
3469                         compatible = "qcom,sc8280xp-mdss";
3470                         reg = <0 0x0ae00000 0 0x1000>;
3471                         reg-names = "mdss";
3472
3473                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3474                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3475                                  <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
3476                         clock-names = "iface",
3477                                       "ahb",
3478                                       "core";
3479                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3480                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
3481                                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
3482                         interconnect-names = "mdp0-mem", "mdp1-mem";
3483                         iommus = <&apps_smmu 0x1000 0x402>;
3484                         power-domains = <&dispcc0 MDSS_GDSC>;
3485                         resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
3486
3487                         interrupt-controller;
3488                         #interrupt-cells = <1>;
3489                         #address-cells = <2>;
3490                         #size-cells = <2>;
3491                         ranges;
3492
3493                         status = "disabled";
3494
3495                         mdss0_mdp: display-controller@ae01000 {
3496                                 compatible = "qcom,sc8280xp-dpu";
3497                                 reg = <0 0x0ae01000 0 0x8f000>,
3498                                       <0 0x0aeb0000 0 0x2008>;
3499                                 reg-names = "mdp", "vbif";
3500
3501                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3502                                          <&gcc GCC_DISP_SF_AXI_CLK>,
3503                                          <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3504                                          <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
3505                                          <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
3506                                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
3507                                 clock-names = "bus",
3508                                               "nrt_bus",
3509                                               "iface",
3510                                               "lut",
3511                                               "core",
3512                                               "vsync";
3513                                 interrupt-parent = <&mdss0>;
3514                                 interrupts = <0>;
3515                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3516
3517                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
3518                                 assigned-clock-rates = <19200000>;
3519                                 operating-points-v2 = <&mdss0_mdp_opp_table>;
3520
3521                                 ports {
3522                                         #address-cells = <1>;
3523                                         #size-cells = <0>;
3524
3525                                         port@0 {
3526                                                 reg = <0>;
3527                                                 mdss0_intf0_out: endpoint {
3528                                                         remote-endpoint = <&mdss0_dp0_in>;
3529                                                 };
3530                                         };
3531
3532                                         port@4 {
3533                                                 reg = <4>;
3534                                                 mdss0_intf4_out: endpoint {
3535                                                         remote-endpoint = <&mdss0_dp1_in>;
3536                                                 };
3537                                         };
3538
3539                                         port@5 {
3540                                                 reg = <5>;
3541                                                 mdss0_intf5_out: endpoint {
3542                                                         remote-endpoint = <&mdss0_dp3_in>;
3543                                                 };
3544                                         };
3545
3546                                         port@6 {
3547                                                 reg = <6>;
3548                                                 mdss0_intf6_out: endpoint {
3549                                                         remote-endpoint = <&mdss0_dp2_in>;
3550                                                 };
3551                                         };
3552                                 };
3553
3554                                 mdss0_mdp_opp_table: opp-table {
3555                                         compatible = "operating-points-v2";
3556
3557                                         opp-200000000 {
3558                                                 opp-hz = /bits/ 64 <200000000>;
3559                                                 required-opps = <&rpmhpd_opp_low_svs>;
3560                                         };
3561
3562                                         opp-300000000 {
3563                                                 opp-hz = /bits/ 64 <300000000>;
3564                                                 required-opps = <&rpmhpd_opp_svs>;
3565                                         };
3566
3567                                         opp-375000000 {
3568                                                 opp-hz = /bits/ 64 <375000000>;
3569                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3570                                         };
3571
3572                                         opp-500000000 {
3573                                                 opp-hz = /bits/ 64 <500000000>;
3574                                                 required-opps = <&rpmhpd_opp_nom>;
3575                                         };
3576                                         opp-600000000 {
3577                                                 opp-hz = /bits/ 64 <600000000>;
3578                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
3579                                         };
3580                                 };
3581                         };
3582
3583                         mdss0_dp0: displayport-controller@ae90000 {
3584                                 compatible = "qcom,sc8280xp-dp";
3585                                 reg = <0 0xae90000 0 0x200>,
3586                                       <0 0xae90200 0 0x200>,
3587                                       <0 0xae90400 0 0x600>,
3588                                       <0 0xae91000 0 0x400>,
3589                                       <0 0xae91400 0 0x400>;
3590                                 interrupt-parent = <&mdss0>;
3591                                 interrupts = <12>;
3592                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3593                                          <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3594                                          <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
3595                                          <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
3596                                          <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
3597                                 clock-names = "core_iface", "core_aux",
3598                                               "ctrl_link",
3599                                               "ctrl_link_iface",
3600                                               "stream_pixel";
3601
3602                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
3603                                                   <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
3604                                 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3605                                                          <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3606
3607                                 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
3608                                 phy-names = "dp";
3609
3610                                 #sound-dai-cells = <0>;
3611
3612                                 operating-points-v2 = <&mdss0_dp0_opp_table>;
3613                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3614
3615                                 status = "disabled";
3616
3617                                 ports {
3618                                         #address-cells = <1>;
3619                                         #size-cells = <0>;
3620
3621                                         port@0 {
3622                                                 reg = <0>;
3623
3624                                                 mdss0_dp0_in: endpoint {
3625                                                         remote-endpoint = <&mdss0_intf0_out>;
3626                                                 };
3627                                         };
3628
3629                                         port@1 {
3630                                                 reg = <1>;
3631
3632                                                 mdss0_dp0_out: endpoint {
3633                                                 };
3634                                         };
3635                                 };
3636
3637                                 mdss0_dp0_opp_table: opp-table {
3638                                         compatible = "operating-points-v2";
3639
3640                                         opp-160000000 {
3641                                                 opp-hz = /bits/ 64 <160000000>;
3642                                                 required-opps = <&rpmhpd_opp_low_svs>;
3643                                         };
3644
3645                                         opp-270000000 {
3646                                                 opp-hz = /bits/ 64 <270000000>;
3647                                                 required-opps = <&rpmhpd_opp_svs>;
3648                                         };
3649
3650                                         opp-540000000 {
3651                                                 opp-hz = /bits/ 64 <540000000>;
3652                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3653                                         };
3654
3655                                         opp-810000000 {
3656                                                 opp-hz = /bits/ 64 <810000000>;
3657                                                 required-opps = <&rpmhpd_opp_nom>;
3658                                         };
3659                                 };
3660                         };
3661
3662                         mdss0_dp1: displayport-controller@ae98000 {
3663                                 compatible = "qcom,sc8280xp-dp";
3664                                 reg = <0 0xae98000 0 0x200>,
3665                                       <0 0xae98200 0 0x200>,
3666                                       <0 0xae98400 0 0x600>,
3667                                       <0 0xae99000 0 0x400>,
3668                                       <0 0xae99400 0 0x400>;
3669                                 interrupt-parent = <&mdss0>;
3670                                 interrupts = <13>;
3671                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3672                                          <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3673                                          <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
3674                                          <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
3675                                          <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
3676                                 clock-names = "core_iface", "core_aux",
3677                                               "ctrl_link",
3678                                               "ctrl_link_iface", "stream_pixel";
3679
3680                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
3681                                                   <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
3682                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3683                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
3684
3685                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
3686                                 phy-names = "dp";
3687
3688                                 #sound-dai-cells = <0>;
3689
3690                                 operating-points-v2 = <&mdss0_dp1_opp_table>;
3691                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3692
3693                                 status = "disabled";
3694
3695                                 ports {
3696                                         #address-cells = <1>;
3697                                         #size-cells = <0>;
3698
3699                                         port@0 {
3700                                                 reg = <0>;
3701
3702                                                 mdss0_dp1_in: endpoint {
3703                                                         remote-endpoint = <&mdss0_intf4_out>;
3704                                                 };
3705                                         };
3706
3707                                         port@1 {
3708                                                 reg = <1>;
3709
3710                                                 mdss0_dp1_out: endpoint {
3711                                                 };
3712                                         };
3713                                 };
3714
3715                                 mdss0_dp1_opp_table: opp-table {
3716                                         compatible = "operating-points-v2";
3717
3718                                         opp-160000000 {
3719                                                 opp-hz = /bits/ 64 <160000000>;
3720                                                 required-opps = <&rpmhpd_opp_low_svs>;
3721                                         };
3722
3723                                         opp-270000000 {
3724                                                 opp-hz = /bits/ 64 <270000000>;
3725                                                 required-opps = <&rpmhpd_opp_svs>;
3726                                         };
3727
3728                                         opp-540000000 {
3729                                                 opp-hz = /bits/ 64 <540000000>;
3730                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3731                                         };
3732
3733                                         opp-810000000 {
3734                                                 opp-hz = /bits/ 64 <810000000>;
3735                                                 required-opps = <&rpmhpd_opp_nom>;
3736                                         };
3737                                 };
3738                         };
3739
3740                         mdss0_dp2: displayport-controller@ae9a000 {
3741                                 compatible = "qcom,sc8280xp-dp";
3742                                 reg = <0 0xae9a000 0 0x200>,
3743                                       <0 0xae9a200 0 0x200>,
3744                                       <0 0xae9a400 0 0x600>,
3745                                       <0 0xae9b000 0 0x400>,
3746                                       <0 0xae9b400 0 0x400>;
3747
3748                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3749                                          <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
3750                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
3751                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
3752                                          <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
3753                                 clock-names = "core_iface", "core_aux",
3754                                               "ctrl_link",
3755                                               "ctrl_link_iface", "stream_pixel";
3756                                 interrupt-parent = <&mdss0>;
3757                                 interrupts = <14>;
3758                                 phys = <&mdss0_dp2_phy>;
3759                                 phy-names = "dp";
3760                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3761
3762                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
3763                                                   <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
3764                                 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
3765                                 operating-points-v2 = <&mdss0_dp2_opp_table>;
3766
3767                                 #sound-dai-cells = <0>;
3768
3769                                 status = "disabled";
3770
3771                                 ports {
3772                                         #address-cells = <1>;
3773                                         #size-cells = <0>;
3774
3775                                         port@0 {
3776                                                 reg = <0>;
3777                                                 mdss0_dp2_in: endpoint {
3778                                                         remote-endpoint = <&mdss0_intf6_out>;
3779                                                 };
3780                                         };
3781
3782                                         port@1 {
3783                                                 reg = <1>;
3784                                         };
3785                                 };
3786
3787                                 mdss0_dp2_opp_table: opp-table {
3788                                         compatible = "operating-points-v2";
3789
3790                                         opp-160000000 {
3791                                                 opp-hz = /bits/ 64 <160000000>;
3792                                                 required-opps = <&rpmhpd_opp_low_svs>;
3793                                         };
3794
3795                                         opp-270000000 {
3796                                                 opp-hz = /bits/ 64 <270000000>;
3797                                                 required-opps = <&rpmhpd_opp_svs>;
3798                                         };
3799
3800                                         opp-540000000 {
3801                                                 opp-hz = /bits/ 64 <540000000>;
3802                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3803                                         };
3804
3805                                         opp-810000000 {
3806                                                 opp-hz = /bits/ 64 <810000000>;
3807                                                 required-opps = <&rpmhpd_opp_nom>;
3808                                         };
3809                                 };
3810                         };
3811
3812                         mdss0_dp3: displayport-controller@aea0000 {
3813                                 compatible = "qcom,sc8280xp-dp";
3814                                 reg = <0 0xaea0000 0 0x200>,
3815                                       <0 0xaea0200 0 0x200>,
3816                                       <0 0xaea0400 0 0x600>,
3817                                       <0 0xaea1000 0 0x400>,
3818                                       <0 0xaea1400 0 0x400>;
3819
3820                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3821                                          <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
3822                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
3823                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
3824                                          <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
3825                                 clock-names = "core_iface", "core_aux",
3826                                               "ctrl_link",
3827                                               "ctrl_link_iface", "stream_pixel";
3828                                 interrupt-parent = <&mdss0>;
3829                                 interrupts = <15>;
3830                                 phys = <&mdss0_dp3_phy>;
3831                                 phy-names = "dp";
3832                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3833
3834                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
3835                                                   <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
3836                                 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
3837                                 operating-points-v2 = <&mdss0_dp3_opp_table>;
3838
3839                                 #sound-dai-cells = <0>;
3840
3841                                 status = "disabled";
3842
3843                                 ports {
3844                                         #address-cells = <1>;
3845                                         #size-cells = <0>;
3846
3847                                         port@0 {
3848                                                 reg = <0>;
3849                                                 mdss0_dp3_in: endpoint {
3850                                                         remote-endpoint = <&mdss0_intf5_out>;
3851                                                 };
3852                                         };
3853
3854                                         port@1 {
3855                                                 reg = <1>;
3856                                         };
3857                                 };
3858
3859                                 mdss0_dp3_opp_table: opp-table {
3860                                         compatible = "operating-points-v2";
3861
3862                                         opp-160000000 {
3863                                                 opp-hz = /bits/ 64 <160000000>;
3864                                                 required-opps = <&rpmhpd_opp_low_svs>;
3865                                         };
3866
3867                                         opp-270000000 {
3868                                                 opp-hz = /bits/ 64 <270000000>;
3869                                                 required-opps = <&rpmhpd_opp_svs>;
3870                                         };
3871
3872                                         opp-540000000 {
3873                                                 opp-hz = /bits/ 64 <540000000>;
3874                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3875                                         };
3876
3877                                         opp-810000000 {
3878                                                 opp-hz = /bits/ 64 <810000000>;
3879                                                 required-opps = <&rpmhpd_opp_nom>;
3880                                         };
3881                                 };
3882                         };
3883                 };
3884
3885                 mdss0_dp2_phy: phy@aec2a00 {
3886                         compatible = "qcom,sc8280xp-dp-phy";
3887                         reg = <0 0x0aec2a00 0 0x19c>,
3888                               <0 0x0aec2200 0 0xec>,
3889                               <0 0x0aec2600 0 0xec>,
3890                               <0 0x0aec2000 0 0x1c8>;
3891
3892                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
3893                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
3894                         clock-names = "aux", "cfg_ahb";
3895                         power-domains = <&rpmhpd SC8280XP_MX>;
3896
3897                         #clock-cells = <1>;
3898                         #phy-cells = <0>;
3899
3900                         status = "disabled";
3901                 };
3902
3903                 mdss0_dp3_phy: phy@aec5a00 {
3904                         compatible = "qcom,sc8280xp-dp-phy";
3905                         reg = <0 0x0aec5a00 0 0x19c>,
3906                               <0 0x0aec5200 0 0xec>,
3907                               <0 0x0aec5600 0 0xec>,
3908                               <0 0x0aec5000 0 0x1c8>;
3909
3910                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
3911                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
3912                         clock-names = "aux", "cfg_ahb";
3913                         power-domains = <&rpmhpd SC8280XP_MX>;
3914
3915                         #clock-cells = <1>;
3916                         #phy-cells = <0>;
3917
3918                         status = "disabled";
3919                 };
3920
3921                 dispcc0: clock-controller@af00000 {
3922                         compatible = "qcom,sc8280xp-dispcc0";
3923                         reg = <0 0x0af00000 0 0x20000>;
3924
3925                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3926                                  <&rpmhcc RPMH_CXO_CLK>,
3927                                  <&sleep_clk>,
3928                                  <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3929                                  <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3930                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
3931                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
3932                                  <&mdss0_dp2_phy 0>,
3933                                  <&mdss0_dp2_phy 1>,
3934                                  <&mdss0_dp3_phy 0>,
3935                                  <&mdss0_dp3_phy 1>,
3936                                  <0>,
3937                                  <0>,
3938                                  <0>,
3939                                  <0>;
3940                         power-domains = <&rpmhpd SC8280XP_MMCX>;
3941
3942                         #clock-cells = <1>;
3943                         #power-domain-cells = <1>;
3944                         #reset-cells = <1>;
3945
3946                         status = "disabled";
3947                 };
3948
3949                 pdc: interrupt-controller@b220000 {
3950                         compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
3951                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
3952                         qcom,pdc-ranges = <0 480 40>,
3953                                           <40 140 14>,
3954                                           <54 263 1>,
3955                                           <55 306 4>,
3956                                           <59 312 3>,
3957                                           <62 374 2>,
3958                                           <64 434 2>,
3959                                           <66 438 3>,
3960                                           <69 86 1>,
3961                                           <70 520 54>,
3962                                           <124 609 28>,
3963                                           <159 638 1>,
3964                                           <160 720 8>,
3965                                           <168 801 1>,
3966                                           <169 728 30>,
3967                                           <199 416 2>,
3968                                           <201 449 1>,
3969                                           <202 89 1>,
3970                                           <203 451 1>,
3971                                           <204 462 1>,
3972                                           <205 264 1>,
3973                                           <206 579 1>,
3974                                           <207 653 1>,
3975                                           <208 656 1>,
3976                                           <209 659 1>,
3977                                           <210 122 1>,
3978                                           <211 699 1>,
3979                                           <212 705 1>,
3980                                           <213 450 1>,
3981                                           <214 643 1>,
3982                                           <216 646 5>,
3983                                           <221 390 5>,
3984                                           <226 700 3>,
3985                                           <229 240 3>,
3986                                           <232 269 1>,
3987                                           <233 377 1>,
3988                                           <234 372 1>,
3989                                           <235 138 1>,
3990                                           <236 857 1>,
3991                                           <237 860 1>,
3992                                           <238 137 1>,
3993                                           <239 668 1>,
3994                                           <240 366 1>,
3995                                           <241 949 1>,
3996                                           <242 815 5>,
3997                                           <247 769 1>,
3998                                           <248 768 1>,
3999                                           <249 663 1>,
4000                                           <250 799 2>,
4001                                           <252 798 1>,
4002                                           <253 765 1>,
4003                                           <254 763 1>,
4004                                           <255 454 1>,
4005                                           <258 139 1>,
4006                                           <259 786 2>,
4007                                           <261 370 2>,
4008                                           <263 158 2>;
4009                         #interrupt-cells = <2>;
4010                         interrupt-parent = <&intc>;
4011                         interrupt-controller;
4012                 };
4013
4014                 tsens0: thermal-sensor@c263000 {
4015                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4016                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4017                               <0 0x0c222000 0 0x8>; /* SROT */
4018                         #qcom,sensors = <14>;
4019                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4020                                               <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4021                         interrupt-names = "uplow", "critical";
4022                         #thermal-sensor-cells = <1>;
4023                 };
4024
4025                 tsens1: thermal-sensor@c265000 {
4026                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4027                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4028                               <0 0x0c223000 0 0x8>; /* SROT */
4029                         #qcom,sensors = <16>;
4030                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4031                                               <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4032                         interrupt-names = "uplow", "critical";
4033                         #thermal-sensor-cells = <1>;
4034                 };
4035
4036                 aoss_qmp: power-management@c300000 {
4037                         compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4038                         reg = <0 0x0c300000 0 0x400>;
4039                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4040                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4041
4042                         #clock-cells = <0>;
4043                 };
4044
4045                 sram@c3f0000 {
4046                         compatible = "qcom,rpmh-stats";
4047                         reg = <0 0x0c3f0000 0 0x400>;
4048                         qcom,qmp = <&aoss_qmp>;
4049                 };
4050
4051                 spmi_bus: spmi@c440000 {
4052                         compatible = "qcom,spmi-pmic-arb";
4053                         reg = <0 0x0c440000 0 0x1100>,
4054                               <0 0x0c600000 0 0x2000000>,
4055                               <0 0x0e600000 0 0x100000>,
4056                               <0 0x0e700000 0 0xa0000>,
4057                               <0 0x0c40a000 0 0x26000>;
4058                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4059                         interrupt-names = "periph_irq";
4060                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4061                         qcom,ee = <0>;
4062                         qcom,channel = <0>;
4063                         #address-cells = <2>;
4064                         #size-cells = <0>;
4065                         interrupt-controller;
4066                         #interrupt-cells = <4>;
4067                 };
4068
4069                 tlmm: pinctrl@f100000 {
4070                         compatible = "qcom,sc8280xp-tlmm";
4071                         reg = <0 0x0f100000 0 0x300000>;
4072                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4073                         gpio-controller;
4074                         #gpio-cells = <2>;
4075                         interrupt-controller;
4076                         #interrupt-cells = <2>;
4077                         gpio-ranges = <&tlmm 0 0 230>;
4078                         wakeup-parent = <&pdc>;
4079                 };
4080
4081                 apps_smmu: iommu@15000000 {
4082                         compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4083                         reg = <0 0x15000000 0 0x100000>;
4084                         #iommu-cells = <2>;
4085                         #global-interrupts = <2>;
4086                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4087                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4088                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4089                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4090                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4091                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4092                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4093                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4094                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4095                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4096                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4097                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4098                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4099                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4100                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4101                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4102                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4103                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4104                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4105                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4106                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4107                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4108                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4109                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4110                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4111                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4112                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4113                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4114                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4115                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4116                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4117                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4118                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4119                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4120                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4121                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4122                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4123                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4124                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4125                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4126                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4127                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4128                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4129                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4130                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4131                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4132                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4133                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4134                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4135                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4136                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4137                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4138                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4139                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4140                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4141                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4142                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4143                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4144                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4145                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4146                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4147                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4148                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4149                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4150                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4151                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4152                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4153                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4154                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4155                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4156                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4157                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4158                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4159                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4160                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4161                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4162                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4163                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4164                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4165                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4166                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4167                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4168                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4169                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4170                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4171                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4172                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4173                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4174                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4175                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4176                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4177                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4178                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4179                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4180                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4181                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4182                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4183                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4184                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4185                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4186                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4187                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4188                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4189                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4190                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4191                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4192                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4193                                      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4194                                      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4195                                      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4196                                      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4197                                      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4198                                      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4199                                      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4200                                      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4201                                      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4202                                      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4203                                      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4204                                      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
4205                                      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
4206                                      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
4207                                      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
4208                                      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
4209                                      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
4210                                      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
4211                                      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
4212                                      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
4213                                      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
4214                                      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
4215                                      <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
4216                 };
4217
4218                 intc: interrupt-controller@17a00000 {
4219                         compatible = "arm,gic-v3";
4220                         interrupt-controller;
4221                         #interrupt-cells = <3>;
4222                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
4223                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
4224                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4225                         #redistributor-regions = <1>;
4226                         redistributor-stride = <0 0x20000>;
4227
4228                         #address-cells = <2>;
4229                         #size-cells = <2>;
4230                         ranges;
4231
4232                         msi-controller@17a40000 {
4233                                 compatible = "arm,gic-v3-its";
4234                                 reg = <0 0x17a40000 0 0x20000>;
4235                                 msi-controller;
4236                                 #msi-cells = <1>;
4237                         };
4238                 };
4239
4240                 watchdog@17c10000 {
4241                         compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
4242                         reg = <0 0x17c10000 0 0x1000>;
4243                         clocks = <&sleep_clk>;
4244                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4245                 };
4246
4247                 timer@17c20000 {
4248                         compatible = "arm,armv7-timer-mem";
4249                         reg = <0x0 0x17c20000 0x0 0x1000>;
4250                         #address-cells = <1>;
4251                         #size-cells = <1>;
4252                         ranges = <0x0 0x0 0x0 0x20000000>;
4253
4254                         frame@17c21000 {
4255                                 frame-number = <0>;
4256                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4257                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4258                                 reg = <0x17c21000 0x1000>,
4259                                       <0x17c22000 0x1000>;
4260                         };
4261
4262                         frame@17c23000 {
4263                                 frame-number = <1>;
4264                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4265                                 reg = <0x17c23000 0x1000>;
4266                                 status = "disabled";
4267                         };
4268
4269                         frame@17c25000 {
4270                                 frame-number = <2>;
4271                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4272                                 reg = <0x17c25000 0x1000>;
4273                                 status = "disabled";
4274                         };
4275
4276                         frame@17c27000 {
4277                                 frame-number = <3>;
4278                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4279                                 reg = <0x17c26000 0x1000>;
4280                                 status = "disabled";
4281                         };
4282
4283                         frame@17c29000 {
4284                                 frame-number = <4>;
4285                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4286                                 reg = <0x17c29000 0x1000>;
4287                                 status = "disabled";
4288                         };
4289
4290                         frame@17c2b000 {
4291                                 frame-number = <5>;
4292                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4293                                 reg = <0x17c2b000 0x1000>;
4294                                 status = "disabled";
4295                         };
4296
4297                         frame@17c2d000 {
4298                                 frame-number = <6>;
4299                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4300                                 reg = <0x17c2d000 0x1000>;
4301                                 status = "disabled";
4302                         };
4303                 };
4304
4305                 apps_rsc: rsc@18200000 {
4306                         compatible = "qcom,rpmh-rsc";
4307                         reg = <0x0 0x18200000 0x0 0x10000>,
4308                                 <0x0 0x18210000 0x0 0x10000>,
4309                                 <0x0 0x18220000 0x0 0x10000>;
4310                         reg-names = "drv-0", "drv-1", "drv-2";
4311                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4312                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4313                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4314                         qcom,tcs-offset = <0xd00>;
4315                         qcom,drv-id = <2>;
4316                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
4317                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
4318                         label = "apps_rsc";
4319                         power-domains = <&CLUSTER_PD>;
4320
4321                         apps_bcm_voter: bcm-voter {
4322                                 compatible = "qcom,bcm-voter";
4323                         };
4324
4325                         rpmhcc: clock-controller {
4326                                 compatible = "qcom,sc8280xp-rpmh-clk";
4327                                 #clock-cells = <1>;
4328                                 clock-names = "xo";
4329                                 clocks = <&xo_board_clk>;
4330                         };
4331
4332                         rpmhpd: power-controller {
4333                                 compatible = "qcom,sc8280xp-rpmhpd";
4334                                 #power-domain-cells = <1>;
4335                                 operating-points-v2 = <&rpmhpd_opp_table>;
4336
4337                                 rpmhpd_opp_table: opp-table {
4338                                         compatible = "operating-points-v2";
4339
4340                                         rpmhpd_opp_ret: opp1 {
4341                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4342                                         };
4343
4344                                         rpmhpd_opp_min_svs: opp2 {
4345                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4346                                         };
4347
4348                                         rpmhpd_opp_low_svs: opp3 {
4349                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4350                                         };
4351
4352                                         rpmhpd_opp_svs: opp4 {
4353                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4354                                         };
4355
4356                                         rpmhpd_opp_svs_l1: opp5 {
4357                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4358                                         };
4359
4360                                         rpmhpd_opp_nom: opp6 {
4361                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4362                                         };
4363
4364                                         rpmhpd_opp_nom_l1: opp7 {
4365                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4366                                         };
4367
4368                                         rpmhpd_opp_nom_l2: opp8 {
4369                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4370                                         };
4371
4372                                         rpmhpd_opp_turbo: opp9 {
4373                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4374                                         };
4375
4376                                         rpmhpd_opp_turbo_l1: opp10 {
4377                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4378                                         };
4379                                 };
4380                         };
4381                 };
4382
4383                 epss_l3: interconnect@18590000 {
4384                         compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
4385                         reg = <0 0x18590000 0 0x1000>;
4386
4387                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4388                         clock-names = "xo", "alternate";
4389
4390                         #interconnect-cells = <1>;
4391                 };
4392
4393                 cpufreq_hw: cpufreq@18591000 {
4394                         compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
4395                         reg = <0 0x18591000 0 0x1000>,
4396                               <0 0x18592000 0 0x1000>;
4397                         reg-names = "freq-domain0", "freq-domain1";
4398
4399                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4400                         clock-names = "xo", "alternate";
4401
4402                         #freq-domain-cells = <1>;
4403                         #clock-cells = <1>;
4404                 };
4405
4406                 remoteproc_nsp0: remoteproc@1b300000 {
4407                         compatible = "qcom,sc8280xp-nsp0-pas";
4408                         reg = <0 0x1b300000 0 0x100>;
4409
4410                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
4411                                               <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
4412                                               <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
4413                                               <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
4414                                               <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
4415                         interrupt-names = "wdog", "fatal", "ready",
4416                                           "handover", "stop-ack";
4417
4418                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4419                         clock-names = "xo";
4420
4421                         power-domains = <&rpmhpd SC8280XP_NSP>;
4422                         power-domain-names = "nsp";
4423
4424                         memory-region = <&pil_nsp0_mem>;
4425
4426                         qcom,smem-states = <&smp2p_nsp0_out 0>;
4427                         qcom,smem-state-names = "stop";
4428
4429                         interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
4430
4431                         status = "disabled";
4432
4433                         glink-edge {
4434                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
4435                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4436                                                              IRQ_TYPE_EDGE_RISING>;
4437                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
4438                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4439
4440                                 label = "nsp0";
4441                                 qcom,remote-pid = <5>;
4442
4443                                 fastrpc {
4444                                         compatible = "qcom,fastrpc";
4445                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
4446                                         label = "cdsp";
4447                                         #address-cells = <1>;
4448                                         #size-cells = <0>;
4449
4450                                         compute-cb@1 {
4451                                                 compatible = "qcom,fastrpc-compute-cb";
4452                                                 reg = <1>;
4453                                                 iommus = <&apps_smmu 0x3181 0x0420>;
4454                                         };
4455
4456                                         compute-cb@2 {
4457                                                 compatible = "qcom,fastrpc-compute-cb";
4458                                                 reg = <2>;
4459                                                 iommus = <&apps_smmu 0x3182 0x0420>;
4460                                         };
4461
4462                                         compute-cb@3 {
4463                                                 compatible = "qcom,fastrpc-compute-cb";
4464                                                 reg = <3>;
4465                                                 iommus = <&apps_smmu 0x3183 0x0420>;
4466                                         };
4467
4468                                         compute-cb@4 {
4469                                                 compatible = "qcom,fastrpc-compute-cb";
4470                                                 reg = <4>;
4471                                                 iommus = <&apps_smmu 0x3184 0x0420>;
4472                                         };
4473
4474                                         compute-cb@5 {
4475                                                 compatible = "qcom,fastrpc-compute-cb";
4476                                                 reg = <5>;
4477                                                 iommus = <&apps_smmu 0x3185 0x0420>;
4478                                         };
4479
4480                                         compute-cb@6 {
4481                                                 compatible = "qcom,fastrpc-compute-cb";
4482                                                 reg = <6>;
4483                                                 iommus = <&apps_smmu 0x3186 0x0420>;
4484                                         };
4485
4486                                         compute-cb@7 {
4487                                                 compatible = "qcom,fastrpc-compute-cb";
4488                                                 reg = <7>;
4489                                                 iommus = <&apps_smmu 0x3187 0x0420>;
4490                                         };
4491
4492                                         compute-cb@8 {
4493                                                 compatible = "qcom,fastrpc-compute-cb";
4494                                                 reg = <8>;
4495                                                 iommus = <&apps_smmu 0x3188 0x0420>;
4496                                         };
4497
4498                                         compute-cb@9 {
4499                                                 compatible = "qcom,fastrpc-compute-cb";
4500                                                 reg = <9>;
4501                                                 iommus = <&apps_smmu 0x318b 0x0420>;
4502                                         };
4503
4504                                         compute-cb@10 {
4505                                                 compatible = "qcom,fastrpc-compute-cb";
4506                                                 reg = <10>;
4507                                                 iommus = <&apps_smmu 0x318b 0x0420>;
4508                                         };
4509
4510                                         compute-cb@11 {
4511                                                 compatible = "qcom,fastrpc-compute-cb";
4512                                                 reg = <11>;
4513                                                 iommus = <&apps_smmu 0x318c 0x0420>;
4514                                         };
4515
4516                                         compute-cb@12 {
4517                                                 compatible = "qcom,fastrpc-compute-cb";
4518                                                 reg = <12>;
4519                                                 iommus = <&apps_smmu 0x318d 0x0420>;
4520                                         };
4521
4522                                         compute-cb@13 {
4523                                                 compatible = "qcom,fastrpc-compute-cb";
4524                                                 reg = <13>;
4525                                                 iommus = <&apps_smmu 0x318e 0x0420>;
4526                                         };
4527
4528                                         compute-cb@14 {
4529                                                 compatible = "qcom,fastrpc-compute-cb";
4530                                                 reg = <14>;
4531                                                 iommus = <&apps_smmu 0x318f 0x0420>;
4532                                         };
4533                                 };
4534                         };
4535                 };
4536
4537                 remoteproc_nsp1: remoteproc@21300000 {
4538                         compatible = "qcom,sc8280xp-nsp1-pas";
4539                         reg = <0 0x21300000 0 0x100>;
4540
4541                         interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
4542                                               <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
4543                                               <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
4544                                               <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
4545                                               <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
4546                         interrupt-names = "wdog", "fatal", "ready",
4547                                           "handover", "stop-ack";
4548
4549                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4550                         clock-names = "xo";
4551
4552                         power-domains = <&rpmhpd SC8280XP_NSP>;
4553                         power-domain-names = "nsp";
4554
4555                         memory-region = <&pil_nsp1_mem>;
4556
4557                         qcom,smem-states = <&smp2p_nsp1_out 0>;
4558                         qcom,smem-state-names = "stop";
4559
4560                         interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
4561
4562                         status = "disabled";
4563
4564                         glink-edge {
4565                                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
4566                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
4567                                                              IRQ_TYPE_EDGE_RISING>;
4568                                 mboxes = <&ipcc IPCC_CLIENT_NSP1
4569                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
4570
4571                                 label = "nsp1";
4572                                 qcom,remote-pid = <12>;
4573                         };
4574                 };
4575
4576                 mdss1: display-subsystem@22000000 {
4577                         compatible = "qcom,sc8280xp-mdss";
4578                         reg = <0 0x22000000 0 0x1000>;
4579                         reg-names = "mdss";
4580
4581                         clocks = <&gcc GCC_DISP_AHB_CLK>,
4582                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
4583                                  <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
4584                         clock-names = "iface",
4585                                       "ahb",
4586                                       "core";
4587                         interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
4588                                         <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
4589                         interconnect-names = "mdp0-mem", "mdp1-mem";
4590                         interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
4591
4592                         iommus = <&apps_smmu 0x1800 0x402>;
4593                         power-domains = <&dispcc1 MDSS_GDSC>;
4594                         resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
4595
4596                         interrupt-controller;
4597                         #interrupt-cells = <1>;
4598                         #address-cells = <2>;
4599                         #size-cells = <2>;
4600                         ranges;
4601
4602                         status = "disabled";
4603
4604                         mdss1_mdp: display-controller@22001000 {
4605                                 compatible = "qcom,sc8280xp-dpu";
4606                                 reg = <0 0x22001000 0 0x8f000>,
4607                                       <0 0x220b0000 0 0x2008>;
4608                                 reg-names = "mdp", "vbif";
4609
4610                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
4611                                          <&gcc GCC_DISP_SF_AXI_CLK>,
4612                                          <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
4613                                          <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
4614                                          <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
4615                                          <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
4616                                 clock-names = "bus",
4617                                               "nrt_bus",
4618                                               "iface",
4619                                               "lut",
4620                                               "core",
4621                                               "vsync";
4622                                 interrupt-parent = <&mdss1>;
4623                                 interrupts = <0>;
4624                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4625
4626                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
4627                                 assigned-clock-rates = <19200000>;
4628                                 operating-points-v2 = <&mdss1_mdp_opp_table>;
4629
4630                                 ports {
4631                                         #address-cells = <1>;
4632                                         #size-cells = <0>;
4633
4634                                         port@0 {
4635                                                 reg = <0>;
4636                                                 mdss1_intf0_out: endpoint {
4637                                                         remote-endpoint = <&mdss1_dp0_in>;
4638                                                 };
4639                                         };
4640
4641                                         port@4 {
4642                                                 reg = <4>;
4643                                                 mdss1_intf4_out: endpoint {
4644                                                         remote-endpoint = <&mdss1_dp1_in>;
4645                                                 };
4646                                         };
4647
4648                                         port@5 {
4649                                                 reg = <5>;
4650                                                 mdss1_intf5_out: endpoint {
4651                                                         remote-endpoint = <&mdss1_dp3_in>;
4652                                                 };
4653                                         };
4654
4655                                         port@6 {
4656                                                 reg = <6>;
4657                                                 mdss1_intf6_out: endpoint {
4658                                                         remote-endpoint = <&mdss1_dp2_in>;
4659                                                 };
4660                                         };
4661                                 };
4662
4663                                 mdss1_mdp_opp_table: opp-table {
4664                                         compatible = "operating-points-v2";
4665
4666                                         opp-200000000 {
4667                                                 opp-hz = /bits/ 64 <200000000>;
4668                                                 required-opps = <&rpmhpd_opp_low_svs>;
4669                                         };
4670
4671                                         opp-300000000 {
4672                                                 opp-hz = /bits/ 64 <300000000>;
4673                                                 required-opps = <&rpmhpd_opp_svs>;
4674                                         };
4675
4676                                         opp-375000000 {
4677                                                 opp-hz = /bits/ 64 <375000000>;
4678                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4679                                         };
4680
4681                                         opp-500000000 {
4682                                                 opp-hz = /bits/ 64 <500000000>;
4683                                                 required-opps = <&rpmhpd_opp_nom>;
4684                                         };
4685                                         opp-600000000 {
4686                                                 opp-hz = /bits/ 64 <600000000>;
4687                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
4688                                         };
4689                                 };
4690                         };
4691
4692                         mdss1_dp0: displayport-controller@22090000 {
4693                                 compatible = "qcom,sc8280xp-dp";
4694                                 reg = <0 0x22090000 0 0x200>,
4695                                       <0 0x22090200 0 0x200>,
4696                                       <0 0x22090400 0 0x600>,
4697                                       <0 0x22091000 0 0x400>,
4698                                       <0 0x22091400 0 0x400>;
4699
4700                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
4701                                          <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
4702                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
4703                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4704                                          <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4705                                 clock-names = "core_iface", "core_aux",
4706                                               "ctrl_link",
4707                                               "ctrl_link_iface", "stream_pixel";
4708                                 interrupt-parent = <&mdss1>;
4709                                 interrupts = <12>;
4710                                 phys = <&mdss1_dp0_phy>;
4711                                 phy-names = "dp";
4712                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4713
4714                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4715                                                   <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4716                                 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
4717                                 operating-points-v2 = <&mdss1_dp0_opp_table>;
4718
4719                                 #sound-dai-cells = <0>;
4720
4721                                 status = "disabled";
4722
4723                                 ports {
4724                                         #address-cells = <1>;
4725                                         #size-cells = <0>;
4726
4727                                         port@0 {
4728                                                 reg = <0>;
4729                                                 mdss1_dp0_in: endpoint {
4730                                                         remote-endpoint = <&mdss1_intf0_out>;
4731                                                 };
4732                                         };
4733
4734                                         port@1 {
4735                                                 reg = <1>;
4736                                         };
4737                                 };
4738
4739                                 mdss1_dp0_opp_table: opp-table {
4740                                         compatible = "operating-points-v2";
4741
4742                                         opp-160000000 {
4743                                                 opp-hz = /bits/ 64 <160000000>;
4744                                                 required-opps = <&rpmhpd_opp_low_svs>;
4745                                         };
4746
4747                                         opp-270000000 {
4748                                                 opp-hz = /bits/ 64 <270000000>;
4749                                                 required-opps = <&rpmhpd_opp_svs>;
4750                                         };
4751
4752                                         opp-540000000 {
4753                                                 opp-hz = /bits/ 64 <540000000>;
4754                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4755                                         };
4756
4757                                         opp-810000000 {
4758                                                 opp-hz = /bits/ 64 <810000000>;
4759                                                 required-opps = <&rpmhpd_opp_nom>;
4760                                         };
4761                                 };
4762                         };
4763
4764                         mdss1_dp1: displayport-controller@22098000 {
4765                                 compatible = "qcom,sc8280xp-dp";
4766                                 reg = <0 0x22098000 0 0x200>,
4767                                       <0 0x22098200 0 0x200>,
4768                                       <0 0x22098400 0 0x600>,
4769                                       <0 0x22099000 0 0x400>,
4770                                       <0 0x22099400 0 0x400>;
4771
4772                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
4773                                          <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4774                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4775                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4776                                          <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4777                                 clock-names = "core_iface", "core_aux",
4778                                               "ctrl_link",
4779                                               "ctrl_link_iface", "stream_pixel";
4780                                 interrupt-parent = <&mdss1>;
4781                                 interrupts = <13>;
4782                                 phys = <&mdss1_dp1_phy>;
4783                                 phy-names = "dp";
4784                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4785
4786                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4787                                                   <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4788                                 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
4789                                 operating-points-v2 = <&mdss1_dp1_opp_table>;
4790
4791                                 #sound-dai-cells = <0>;
4792
4793                                 status = "disabled";
4794
4795                                 ports {
4796                                         #address-cells = <1>;
4797                                         #size-cells = <0>;
4798
4799                                         port@0 {
4800                                                 reg = <0>;
4801                                                 mdss1_dp1_in: endpoint {
4802                                                         remote-endpoint = <&mdss1_intf4_out>;
4803                                                 };
4804                                         };
4805
4806                                         port@1 {
4807                                                 reg = <1>;
4808                                         };
4809                                 };
4810
4811                                 mdss1_dp1_opp_table: opp-table {
4812                                         compatible = "operating-points-v2";
4813
4814                                         opp-160000000 {
4815                                                 opp-hz = /bits/ 64 <160000000>;
4816                                                 required-opps = <&rpmhpd_opp_low_svs>;
4817                                         };
4818
4819                                         opp-270000000 {
4820                                                 opp-hz = /bits/ 64 <270000000>;
4821                                                 required-opps = <&rpmhpd_opp_svs>;
4822                                         };
4823
4824                                         opp-540000000 {
4825                                                 opp-hz = /bits/ 64 <540000000>;
4826                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4827                                         };
4828
4829                                         opp-810000000 {
4830                                                 opp-hz = /bits/ 64 <810000000>;
4831                                                 required-opps = <&rpmhpd_opp_nom>;
4832                                         };
4833                                 };
4834                         };
4835
4836                         mdss1_dp2: displayport-controller@2209a000 {
4837                                 compatible = "qcom,sc8280xp-dp";
4838                                 reg = <0 0x2209a000 0 0x200>,
4839                                       <0 0x2209a200 0 0x200>,
4840                                       <0 0x2209a400 0 0x600>,
4841                                       <0 0x2209b000 0 0x400>,
4842                                       <0 0x2209b400 0 0x400>;
4843
4844                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
4845                                          <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4846                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4847                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4848                                          <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4849                                 clock-names = "core_iface", "core_aux",
4850                                               "ctrl_link",
4851                                               "ctrl_link_iface", "stream_pixel";
4852                                 interrupt-parent = <&mdss1>;
4853                                 interrupts = <14>;
4854                                 phys = <&mdss1_dp2_phy>;
4855                                 phy-names = "dp";
4856                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4857
4858                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4859                                                   <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4860                                 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
4861                                 operating-points-v2 = <&mdss1_dp2_opp_table>;
4862
4863                                 #sound-dai-cells = <0>;
4864
4865                                 status = "disabled";
4866
4867                                 ports {
4868                                         #address-cells = <1>;
4869                                         #size-cells = <0>;
4870
4871                                         port@0 {
4872                                                 reg = <0>;
4873                                                 mdss1_dp2_in: endpoint {
4874                                                         remote-endpoint = <&mdss1_intf6_out>;
4875                                                 };
4876                                         };
4877
4878                                         port@1 {
4879                                                 reg = <1>;
4880                                         };
4881                                 };
4882
4883                                 mdss1_dp2_opp_table: opp-table {
4884                                         compatible = "operating-points-v2";
4885
4886                                         opp-160000000 {
4887                                                 opp-hz = /bits/ 64 <160000000>;
4888                                                 required-opps = <&rpmhpd_opp_low_svs>;
4889                                         };
4890
4891                                         opp-270000000 {
4892                                                 opp-hz = /bits/ 64 <270000000>;
4893                                                 required-opps = <&rpmhpd_opp_svs>;
4894                                         };
4895
4896                                         opp-540000000 {
4897                                                 opp-hz = /bits/ 64 <540000000>;
4898                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4899                                         };
4900
4901                                         opp-810000000 {
4902                                                 opp-hz = /bits/ 64 <810000000>;
4903                                                 required-opps = <&rpmhpd_opp_nom>;
4904                                         };
4905                                 };
4906                         };
4907
4908                         mdss1_dp3: displayport-controller@220a0000 {
4909                                 compatible = "qcom,sc8280xp-dp";
4910                                 reg = <0 0x220a0000 0 0x200>,
4911                                       <0 0x220a0200 0 0x200>,
4912                                       <0 0x220a0400 0 0x600>,
4913                                       <0 0x220a1000 0 0x400>,
4914                                       <0 0x220a1400 0 0x400>;
4915
4916                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
4917                                          <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4918                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4919                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4920                                          <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4921                                 clock-names = "core_iface", "core_aux",
4922                                               "ctrl_link",
4923                                               "ctrl_link_iface", "stream_pixel";
4924                                 interrupt-parent = <&mdss1>;
4925                                 interrupts = <15>;
4926                                 phys = <&mdss1_dp3_phy>;
4927                                 phy-names = "dp";
4928                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4929
4930                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4931                                                   <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4932                                 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
4933                                 operating-points-v2 = <&mdss1_dp3_opp_table>;
4934
4935                                 #sound-dai-cells = <0>;
4936
4937                                 status = "disabled";
4938
4939                                 ports {
4940                                         #address-cells = <1>;
4941                                         #size-cells = <0>;
4942
4943                                         port@0 {
4944                                                 reg = <0>;
4945                                                 mdss1_dp3_in: endpoint {
4946                                                         remote-endpoint = <&mdss1_intf5_out>;
4947                                                 };
4948                                         };
4949
4950                                         port@1 {
4951                                                 reg = <1>;
4952                                         };
4953                                 };
4954
4955                                 mdss1_dp3_opp_table: opp-table {
4956                                         compatible = "operating-points-v2";
4957
4958                                         opp-160000000 {
4959                                                 opp-hz = /bits/ 64 <160000000>;
4960                                                 required-opps = <&rpmhpd_opp_low_svs>;
4961                                         };
4962
4963                                         opp-270000000 {
4964                                                 opp-hz = /bits/ 64 <270000000>;
4965                                                 required-opps = <&rpmhpd_opp_svs>;
4966                                         };
4967
4968                                         opp-540000000 {
4969                                                 opp-hz = /bits/ 64 <540000000>;
4970                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4971                                         };
4972
4973                                         opp-810000000 {
4974                                                 opp-hz = /bits/ 64 <810000000>;
4975                                                 required-opps = <&rpmhpd_opp_nom>;
4976                                         };
4977                                 };
4978                         };
4979                 };
4980
4981                 mdss1_dp2_phy: phy@220c2a00 {
4982                         compatible = "qcom,sc8280xp-dp-phy";
4983                         reg = <0 0x220c2a00 0 0x19c>,
4984                               <0 0x220c2200 0 0xec>,
4985                               <0 0x220c2600 0 0xec>,
4986                               <0 0x220c2000 0 0x1c8>;
4987
4988                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4989                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
4990                         clock-names = "aux", "cfg_ahb";
4991                         power-domains = <&rpmhpd SC8280XP_MX>;
4992
4993                         #clock-cells = <1>;
4994                         #phy-cells = <0>;
4995
4996                         status = "disabled";
4997                 };
4998
4999                 mdss1_dp3_phy: phy@220c5a00 {
5000                         compatible = "qcom,sc8280xp-dp-phy";
5001                         reg = <0 0x220c5a00 0 0x19c>,
5002                               <0 0x220c5200 0 0xec>,
5003                               <0 0x220c5600 0 0xec>,
5004                               <0 0x220c5000 0 0x1c8>;
5005
5006                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5007                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5008                         clock-names = "aux", "cfg_ahb";
5009                         power-domains = <&rpmhpd SC8280XP_MX>;
5010
5011                         #clock-cells = <1>;
5012                         #phy-cells = <0>;
5013
5014                         status = "disabled";
5015                 };
5016
5017                 dispcc1: clock-controller@22100000 {
5018                         compatible = "qcom,sc8280xp-dispcc1";
5019                         reg = <0 0x22100000 0 0x20000>;
5020
5021                         clocks = <&gcc GCC_DISP_AHB_CLK>,
5022                                  <&rpmhcc RPMH_CXO_CLK>,
5023                                  <0>,
5024                                  <&mdss1_dp0_phy 0>,
5025                                  <&mdss1_dp0_phy 1>,
5026                                  <&mdss1_dp1_phy 0>,
5027                                  <&mdss1_dp1_phy 1>,
5028                                  <&mdss1_dp2_phy 0>,
5029                                  <&mdss1_dp2_phy 1>,
5030                                  <&mdss1_dp3_phy 0>,
5031                                  <&mdss1_dp3_phy 1>,
5032                                  <0>,
5033                                  <0>,
5034                                  <0>,
5035                                  <0>;
5036                         power-domains = <&rpmhpd SC8280XP_MMCX>;
5037
5038                         #clock-cells = <1>;
5039                         #power-domain-cells = <1>;
5040                         #reset-cells = <1>;
5041
5042                         status = "disabled";
5043                 };
5044
5045                 ethernet1: ethernet@23000000 {
5046                         compatible = "qcom,sc8280xp-ethqos";
5047                         reg = <0x0 0x23000000 0x0 0x10000>,
5048                               <0x0 0x23016000 0x0 0x100>;
5049                         reg-names = "stmmaceth", "rgmii";
5050
5051                         clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5052                                  <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5053                                  <&gcc GCC_EMAC1_PTP_CLK>,
5054                                  <&gcc GCC_EMAC1_RGMII_CLK>;
5055                         clock-names = "stmmaceth",
5056                                       "pclk",
5057                                       "ptp_ref",
5058                                       "rgmii";
5059
5060                         interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
5061                                      <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>;
5062                         interrupt-names = "macirq", "eth_lpi";
5063
5064                         iommus = <&apps_smmu 0x40 0xf>;
5065                         power-domains = <&gcc EMAC_1_GDSC>;
5066
5067                         snps,tso;
5068                         snps,pbl = <32>;
5069                         rx-fifo-depth = <4096>;
5070                         tx-fifo-depth = <4096>;
5071
5072                         status = "disabled";
5073                 };
5074         };
5075
5076         sound: sound {
5077         };
5078
5079         thermal-zones {
5080                 cpu0-thermal {
5081                         polling-delay-passive = <250>;
5082                         polling-delay = <1000>;
5083
5084                         thermal-sensors = <&tsens0 1>;
5085
5086                         trips {
5087                                 cpu-crit {
5088                                         temperature = <110000>;
5089                                         hysteresis = <1000>;
5090                                         type = "critical";
5091                                 };
5092                         };
5093                 };
5094
5095                 cpu1-thermal {
5096                         polling-delay-passive = <250>;
5097                         polling-delay = <1000>;
5098
5099                         thermal-sensors = <&tsens0 2>;
5100
5101                         trips {
5102                                 cpu-crit {
5103                                         temperature = <110000>;
5104                                         hysteresis = <1000>;
5105                                         type = "critical";
5106                                 };
5107                         };
5108                 };
5109
5110                 cpu2-thermal {
5111                         polling-delay-passive = <250>;
5112                         polling-delay = <1000>;
5113
5114                         thermal-sensors = <&tsens0 3>;
5115
5116                         trips {
5117                                 cpu-crit {
5118                                         temperature = <110000>;
5119                                         hysteresis = <1000>;
5120                                         type = "critical";
5121                                 };
5122                         };
5123                 };
5124
5125                 cpu3-thermal {
5126                         polling-delay-passive = <250>;
5127                         polling-delay = <1000>;
5128
5129                         thermal-sensors = <&tsens0 4>;
5130
5131                         trips {
5132                                 cpu-crit {
5133                                         temperature = <110000>;
5134                                         hysteresis = <1000>;
5135                                         type = "critical";
5136                                 };
5137                         };
5138                 };
5139
5140                 cpu4-thermal {
5141                         polling-delay-passive = <250>;
5142                         polling-delay = <1000>;
5143
5144                         thermal-sensors = <&tsens0 5>;
5145
5146                         trips {
5147                                 cpu-crit {
5148                                         temperature = <110000>;
5149                                         hysteresis = <1000>;
5150                                         type = "critical";
5151                                 };
5152                         };
5153                 };
5154
5155                 cpu5-thermal {
5156                         polling-delay-passive = <250>;
5157                         polling-delay = <1000>;
5158
5159                         thermal-sensors = <&tsens0 6>;
5160
5161                         trips {
5162                                 cpu-crit {
5163                                         temperature = <110000>;
5164                                         hysteresis = <1000>;
5165                                         type = "critical";
5166                                 };
5167                         };
5168                 };
5169
5170                 cpu6-thermal {
5171                         polling-delay-passive = <250>;
5172                         polling-delay = <1000>;
5173
5174                         thermal-sensors = <&tsens0 7>;
5175
5176                         trips {
5177                                 cpu-crit {
5178                                         temperature = <110000>;
5179                                         hysteresis = <1000>;
5180                                         type = "critical";
5181                                 };
5182                         };
5183                 };
5184
5185                 cpu7-thermal {
5186                         polling-delay-passive = <250>;
5187                         polling-delay = <1000>;
5188
5189                         thermal-sensors = <&tsens0 8>;
5190
5191                         trips {
5192                                 cpu-crit {
5193                                         temperature = <110000>;
5194                                         hysteresis = <1000>;
5195                                         type = "critical";
5196                                 };
5197                         };
5198                 };
5199
5200                 cluster0-thermal {
5201                         polling-delay-passive = <250>;
5202                         polling-delay = <1000>;
5203
5204                         thermal-sensors = <&tsens0 9>;
5205
5206                         trips {
5207                                 cpu-crit {
5208                                         temperature = <110000>;
5209                                         hysteresis = <1000>;
5210                                         type = "critical";
5211                                 };
5212                         };
5213                 };
5214
5215                 mem-thermal {
5216                         polling-delay-passive = <250>;
5217                         polling-delay = <1000>;
5218
5219                         thermal-sensors = <&tsens1 15>;
5220
5221                         trips {
5222                                 trip-point0 {
5223                                         temperature = <90000>;
5224                                         hysteresis = <2000>;
5225                                         type = "hot";
5226                                 };
5227                         };
5228                 };
5229         };
5230
5231         timer {
5232                 compatible = "arm,armv8-timer";
5233                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5234                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5235                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5236                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5237         };
5238 };