arch/arm64/boot/dts/qcom/sc8280xp.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * Copyright (c) 2021, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Linaro Limited
   5  */
   6
   7 #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h>
   8 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
   9 #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h>
  10 #include <dt-bindings/clock/qcom,rpmh.h>
  11 #include <dt-bindings/clock/qcom,sc8280xp-camcc.h>
  12 #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
  13 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  14 #include <dt-bindings/interconnect/qcom,sc8280xp.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16 #include <dt-bindings/mailbox/qcom-ipcc.h>
  17 #include <dt-bindings/phy/phy-qcom-qmp.h>
  18 #include <dt-bindings/power/qcom-rpmpd.h>
  19 #include <dt-bindings/soc/qcom,gpr.h>
  20 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  21 #include <dt-bindings/sound/qcom,q6afe.h>
  22 #include <dt-bindings/thermal/thermal.h>
  23
  24 / {
  25         interrupt-parent = <&intc>;
  26
  27         #address-cells = <2>;
  28         #size-cells = <2>;
  29
  30         clocks {
  31                 xo_board_clk: xo-board-clk {
  32                         compatible = "fixed-clock";
  33                         #clock-cells = <0>;
  34                 };
  35
  36                 sleep_clk: sleep-clk {
  37                         compatible = "fixed-clock";
  38                         #clock-cells = <0>;
  39                         clock-frequency = <32764>;
  40                 };
  41         };
  42
  43         cpus {
  44                 #address-cells = <2>;
  45                 #size-cells = <0>;
  46
  47                 CPU0: cpu@0 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a78c";
  50                         reg = <0x0 0x0>;
  51                         clocks = <&cpufreq_hw 0>;
  52                         enable-method = "psci";
  53                         capacity-dmips-mhz = <602>;
  54                         next-level-cache = <&L2_0>;
  55                         power-domains = <&CPU_PD0>;
  56                         power-domain-names = "psci";
  57                         qcom,freq-domain = <&cpufreq_hw 0>;
  58                         operating-points-v2 = <&cpu0_opp_table>;
  59                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  60                         #cooling-cells = <2>;
  61                         L2_0: l2-cache {
  62                                 compatible = "cache";
  63                                 cache-level = <2>;
  64                                 cache-unified;
  65                                 next-level-cache = <&L3_0>;
  66                                 L3_0: l3-cache {
  67                                         compatible = "cache";
  68                                         cache-level = <3>;
  69                                         cache-unified;
  70                                 };
  71                         };
  72                 };
  73
  74                 CPU1: cpu@100 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a78c";
  77                         reg = <0x0 0x100>;
  78                         clocks = <&cpufreq_hw 0>;
  79                         enable-method = "psci";
  80                         capacity-dmips-mhz = <602>;
  81                         next-level-cache = <&L2_100>;
  82                         power-domains = <&CPU_PD1>;
  83                         power-domain-names = "psci";
  84                         qcom,freq-domain = <&cpufreq_hw 0>;
  85                         operating-points-v2 = <&cpu0_opp_table>;
  86                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
  87                         #cooling-cells = <2>;
  88                         L2_100: l2-cache {
  89                                 compatible = "cache";
  90                                 cache-level = <2>;
  91                                 cache-unified;
  92                                 next-level-cache = <&L3_0>;
  93                         };
  94                 };
  95
  96                 CPU2: cpu@200 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a78c";
  99                         reg = <0x0 0x200>;
 100                         clocks = <&cpufreq_hw 0>;
 101                         enable-method = "psci";
 102                         capacity-dmips-mhz = <602>;
 103                         next-level-cache = <&L2_200>;
 104                         power-domains = <&CPU_PD2>;
 105                         power-domain-names = "psci";
 106                         qcom,freq-domain = <&cpufreq_hw 0>;
 107                         operating-points-v2 = <&cpu0_opp_table>;
 108                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 109                         #cooling-cells = <2>;
 110                         L2_200: l2-cache {
 111                                 compatible = "cache";
 112                                 cache-level = <2>;
 113                                 cache-unified;
 114                                 next-level-cache = <&L3_0>;
 115                         };
 116                 };
 117
 118                 CPU3: cpu@300 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a78c";
 121                         reg = <0x0 0x300>;
 122                         clocks = <&cpufreq_hw 0>;
 123                         enable-method = "psci";
 124                         capacity-dmips-mhz = <602>;
 125                         next-level-cache = <&L2_300>;
 126                         power-domains = <&CPU_PD3>;
 127                         power-domain-names = "psci";
 128                         qcom,freq-domain = <&cpufreq_hw 0>;
 129                         operating-points-v2 = <&cpu0_opp_table>;
 130                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 131                         #cooling-cells = <2>;
 132                         L2_300: l2-cache {
 133                                 compatible = "cache";
 134                                 cache-level = <2>;
 135                                 cache-unified;
 136                                 next-level-cache = <&L3_0>;
 137                         };
 138                 };
 139
 140                 CPU4: cpu@400 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-x1c";
 143                         reg = <0x0 0x400>;
 144                         clocks = <&cpufreq_hw 1>;
 145                         enable-method = "psci";
 146                         capacity-dmips-mhz = <1024>;
 147                         next-level-cache = <&L2_400>;
 148                         power-domains = <&CPU_PD4>;
 149                         power-domain-names = "psci";
 150                         qcom,freq-domain = <&cpufreq_hw 1>;
 151                         operating-points-v2 = <&cpu4_opp_table>;
 152                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 153                         #cooling-cells = <2>;
 154                         L2_400: l2-cache {
 155                                 compatible = "cache";
 156                                 cache-level = <2>;
 157                                 cache-unified;
 158                                 next-level-cache = <&L3_0>;
 159                         };
 160                 };
 161
 162                 CPU5: cpu@500 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-x1c";
 165                         reg = <0x0 0x500>;
 166                         clocks = <&cpufreq_hw 1>;
 167                         enable-method = "psci";
 168                         capacity-dmips-mhz = <1024>;
 169                         next-level-cache = <&L2_500>;
 170                         power-domains = <&CPU_PD5>;
 171                         power-domain-names = "psci";
 172                         qcom,freq-domain = <&cpufreq_hw 1>;
 173                         operating-points-v2 = <&cpu4_opp_table>;
 174                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 175                         #cooling-cells = <2>;
 176                         L2_500: l2-cache {
 177                                 compatible = "cache";
 178                                 cache-level = <2>;
 179                                 cache-unified;
 180                                 next-level-cache = <&L3_0>;
 181                         };
 182                 };
 183
 184                 CPU6: cpu@600 {
 185                         device_type = "cpu";
 186                         compatible = "arm,cortex-x1c";
 187                         reg = <0x0 0x600>;
 188                         clocks = <&cpufreq_hw 1>;
 189                         enable-method = "psci";
 190                         capacity-dmips-mhz = <1024>;
 191                         next-level-cache = <&L2_600>;
 192                         power-domains = <&CPU_PD6>;
 193                         power-domain-names = "psci";
 194                         qcom,freq-domain = <&cpufreq_hw 1>;
 195                         operating-points-v2 = <&cpu4_opp_table>;
 196                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 197                         #cooling-cells = <2>;
 198                         L2_600: l2-cache {
 199                                 compatible = "cache";
 200                                 cache-level = <2>;
 201                                 cache-unified;
 202                                 next-level-cache = <&L3_0>;
 203                         };
 204                 };
 205
 206                 CPU7: cpu@700 {
 207                         device_type = "cpu";
 208                         compatible = "arm,cortex-x1c";
 209                         reg = <0x0 0x700>;
 210                         clocks = <&cpufreq_hw 1>;
 211                         enable-method = "psci";
 212                         capacity-dmips-mhz = <1024>;
 213                         next-level-cache = <&L2_700>;
 214                         power-domains = <&CPU_PD7>;
 215                         power-domain-names = "psci";
 216                         qcom,freq-domain = <&cpufreq_hw 1>;
 217                         operating-points-v2 = <&cpu4_opp_table>;
 218                         interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
 219                         #cooling-cells = <2>;
 220                         L2_700: l2-cache {
 221                                 compatible = "cache";
 222                                 cache-level = <2>;
 223                                 cache-unified;
 224                                 next-level-cache = <&L3_0>;
 225                         };
 226                 };
 227
 228                 cpu-map {
 229                         cluster0 {
 230                                 core0 {
 231                                         cpu = <&CPU0>;
 232                                 };
 233
 234                                 core1 {
 235                                         cpu = <&CPU1>;
 236                                 };
 237
 238                                 core2 {
 239                                         cpu = <&CPU2>;
 240                                 };
 241
 242                                 core3 {
 243                                         cpu = <&CPU3>;
 244                                 };
 245
 246                                 core4 {
 247                                         cpu = <&CPU4>;
 248                                 };
 249
 250                                 core5 {
 251                                         cpu = <&CPU5>;
 252                                 };
 253
 254                                 core6 {
 255                                         cpu = <&CPU6>;
 256                                 };
 257
 258                                 core7 {
 259                                         cpu = <&CPU7>;
 260                                 };
 261                         };
 262                 };
 263
 264                 idle-states {
 265                         entry-method = "psci";
 266
 267                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 268                                 compatible = "arm,idle-state";
 269                                 idle-state-name = "little-rail-power-collapse";
 270                                 arm,psci-suspend-param = <0x40000004>;
 271                                 entry-latency-us = <355>;
 272                                 exit-latency-us = <909>;
 273                                 min-residency-us = <3934>;
 274                                 local-timer-stop;
 275                         };
 276
 277                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 278                                 compatible = "arm,idle-state";
 279                                 idle-state-name = "big-rail-power-collapse";
 280                                 arm,psci-suspend-param = <0x40000004>;
 281                                 entry-latency-us = <241>;
 282                                 exit-latency-us = <1461>;
 283                                 min-residency-us = <4488>;
 284                                 local-timer-stop;
 285                         };
 286                 };
 287
 288                 domain-idle-states {
 289                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 290                                 compatible = "domain-idle-state";
 291                                 arm,psci-suspend-param = <0x4100c344>;
 292                                 entry-latency-us = <3263>;
 293                                 exit-latency-us = <6562>;
 294                                 min-residency-us = <9987>;
 295                         };
 296                 };
 297         };
 298
 299         firmware {
 300                 scm: scm {
 301                         compatible = "qcom,scm-sc8280xp", "qcom,scm";
 302                         interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
 303                 };
 304         };
 305
 306         aggre1_noc: interconnect-aggre1-noc {
 307                 compatible = "qcom,sc8280xp-aggre1-noc";
 308                 #interconnect-cells = <2>;
 309                 qcom,bcm-voters = <&apps_bcm_voter>;
 310         };
 311
 312         aggre2_noc: interconnect-aggre2-noc {
 313                 compatible = "qcom,sc8280xp-aggre2-noc";
 314                 #interconnect-cells = <2>;
 315                 qcom,bcm-voters = <&apps_bcm_voter>;
 316         };
 317
 318         clk_virt: interconnect-clk-virt {
 319                 compatible = "qcom,sc8280xp-clk-virt";
 320                 #interconnect-cells = <2>;
 321                 qcom,bcm-voters = <&apps_bcm_voter>;
 322         };
 323
 324         config_noc: interconnect-config-noc {
 325                 compatible = "qcom,sc8280xp-config-noc";
 326                 #interconnect-cells = <2>;
 327                 qcom,bcm-voters = <&apps_bcm_voter>;
 328         };
 329
 330         dc_noc: interconnect-dc-noc {
 331                 compatible = "qcom,sc8280xp-dc-noc";
 332                 #interconnect-cells = <2>;
 333                 qcom,bcm-voters = <&apps_bcm_voter>;
 334         };
 335
 336         gem_noc: interconnect-gem-noc {
 337                 compatible = "qcom,sc8280xp-gem-noc";
 338                 #interconnect-cells = <2>;
 339                 qcom,bcm-voters = <&apps_bcm_voter>;
 340         };
 341
 342         lpass_noc: interconnect-lpass-ag-noc {
 343                 compatible = "qcom,sc8280xp-lpass-ag-noc";
 344                 #interconnect-cells = <2>;
 345                 qcom,bcm-voters = <&apps_bcm_voter>;
 346         };
 347
 348         mc_virt: interconnect-mc-virt {
 349                 compatible = "qcom,sc8280xp-mc-virt";
 350                 #interconnect-cells = <2>;
 351                 qcom,bcm-voters = <&apps_bcm_voter>;
 352         };
 353
 354         mmss_noc: interconnect-mmss-noc {
 355                 compatible = "qcom,sc8280xp-mmss-noc";
 356                 #interconnect-cells = <2>;
 357                 qcom,bcm-voters = <&apps_bcm_voter>;
 358         };
 359
 360         nspa_noc: interconnect-nspa-noc {
 361                 compatible = "qcom,sc8280xp-nspa-noc";
 362                 #interconnect-cells = <2>;
 363                 qcom,bcm-voters = <&apps_bcm_voter>;
 364         };
 365
 366         nspb_noc: interconnect-nspb-noc {
 367                 compatible = "qcom,sc8280xp-nspb-noc";
 368                 #interconnect-cells = <2>;
 369                 qcom,bcm-voters = <&apps_bcm_voter>;
 370         };
 371
 372         system_noc: interconnect-system-noc {
 373                 compatible = "qcom,sc8280xp-system-noc";
 374                 #interconnect-cells = <2>;
 375                 qcom,bcm-voters = <&apps_bcm_voter>;
 376         };
 377
 378         memory@80000000 {
 379                 device_type = "memory";
 380                 /* We expect the bootloader to fill in the size */
 381                 reg = <0x0 0x80000000 0x0 0x0>;
 382         };
 383
 384         cpu0_opp_table: opp-table-cpu0 {
 385                 compatible = "operating-points-v2";
 386                 opp-shared;
 387
 388                 opp-300000000 {
 389                         opp-hz = /bits/ 64 <300000000>;
 390                         opp-peak-kBps = <(300000 * 32)>;
 391                 };
 392                 opp-403200000 {
 393                         opp-hz = /bits/ 64 <403200000>;
 394                         opp-peak-kBps = <(384000 * 32)>;
 395                 };
 396                 opp-499200000 {
 397                         opp-hz = /bits/ 64 <499200000>;
 398                         opp-peak-kBps = <(480000 * 32)>;
 399                 };
 400                 opp-595200000 {
 401                         opp-hz = /bits/ 64 <595200000>;
 402                         opp-peak-kBps = <(576000 * 32)>;
 403                 };
 404                 opp-691200000 {
 405                         opp-hz = /bits/ 64 <691200000>;
 406                         opp-peak-kBps = <(672000 * 32)>;
 407                 };
 408                 opp-806400000 {
 409                         opp-hz = /bits/ 64 <806400000>;
 410                         opp-peak-kBps = <(768000 * 32)>;
 411                 };
 412                 opp-902400000 {
 413                         opp-hz = /bits/ 64 <902400000>;
 414                         opp-peak-kBps = <(864000 * 32)>;
 415                 };
 416                 opp-1017600000 {
 417                         opp-hz = /bits/ 64 <1017600000>;
 418                         opp-peak-kBps = <(960000 * 32)>;
 419                 };
 420                 opp-1113600000 {
 421                         opp-hz = /bits/ 64 <1113600000>;
 422                         opp-peak-kBps = <(1075200 * 32)>;
 423                 };
 424                 opp-1209600000 {
 425                         opp-hz = /bits/ 64 <1209600000>;
 426                         opp-peak-kBps = <(1171200 * 32)>;
 427                 };
 428                 opp-1324800000 {
 429                         opp-hz = /bits/ 64 <1324800000>;
 430                         opp-peak-kBps = <(1267200 * 32)>;
 431                 };
 432                 opp-1440000000 {
 433                         opp-hz = /bits/ 64 <1440000000>;
 434                         opp-peak-kBps = <(1363200 * 32)>;
 435                 };
 436                 opp-1555200000 {
 437                         opp-hz = /bits/ 64 <1555200000>;
 438                         opp-peak-kBps = <(1536000 * 32)>;
 439                 };
 440                 opp-1670400000 {
 441                         opp-hz = /bits/ 64 <1670400000>;
 442                         opp-peak-kBps = <(1612800 * 32)>;
 443                 };
 444                 opp-1785600000 {
 445                         opp-hz = /bits/ 64 <1785600000>;
 446                         opp-peak-kBps = <(1689600 * 32)>;
 447                 };
 448                 opp-1881600000 {
 449                         opp-hz = /bits/ 64 <1881600000>;
 450                         opp-peak-kBps = <(1689600 * 32)>;
 451                 };
 452                 opp-1996800000 {
 453                         opp-hz = /bits/ 64 <1996800000>;
 454                         opp-peak-kBps = <(1689600 * 32)>;
 455                 };
 456                 opp-2112000000 {
 457                         opp-hz = /bits/ 64 <2112000000>;
 458                         opp-peak-kBps = <(1689600 * 32)>;
 459                 };
 460                 opp-2227200000 {
 461                         opp-hz = /bits/ 64 <2227200000>;
 462                         opp-peak-kBps = <(1689600 * 32)>;
 463                 };
 464                 opp-2342400000 {
 465                         opp-hz = /bits/ 64 <2342400000>;
 466                         opp-peak-kBps = <(1689600 * 32)>;
 467                 };
 468                 opp-2438400000 {
 469                         opp-hz = /bits/ 64 <2438400000>;
 470                         opp-peak-kBps = <(1689600 * 32)>;
 471                 };
 472         };
 473
 474         cpu4_opp_table: opp-table-cpu4 {
 475                 compatible = "operating-points-v2";
 476                 opp-shared;
 477
 478                 opp-825600000 {
 479                         opp-hz = /bits/ 64 <825600000>;
 480                         opp-peak-kBps = <(768000 * 32)>;
 481                 };
 482                 opp-940800000 {
 483                         opp-hz = /bits/ 64 <940800000>;
 484                         opp-peak-kBps = <(864000 * 32)>;
 485                 };
 486                 opp-1056000000 {
 487                         opp-hz = /bits/ 64 <1056000000>;
 488                         opp-peak-kBps = <(960000 * 32)>;
 489                 };
 490                 opp-1171200000 {
 491                         opp-hz = /bits/ 64 <1171200000>;
 492                         opp-peak-kBps = <(1171200 * 32)>;
 493                 };
 494                 opp-1286400000 {
 495                         opp-hz = /bits/ 64 <1286400000>;
 496                         opp-peak-kBps = <(1267200 * 32)>;
 497                 };
 498                 opp-1401600000 {
 499                         opp-hz = /bits/ 64 <1401600000>;
 500                         opp-peak-kBps = <(1363200 * 32)>;
 501                 };
 502                 opp-1516800000 {
 503                         opp-hz = /bits/ 64 <1516800000>;
 504                         opp-peak-kBps = <(1459200 * 32)>;
 505                 };
 506                 opp-1632000000 {
 507                         opp-hz = /bits/ 64 <1632000000>;
 508                         opp-peak-kBps = <(1612800 * 32)>;
 509                 };
 510                 opp-1747200000 {
 511                         opp-hz = /bits/ 64 <1747200000>;
 512                         opp-peak-kBps = <(1689600 * 32)>;
 513                 };
 514                 opp-1862400000 {
 515                         opp-hz = /bits/ 64 <1862400000>;
 516                         opp-peak-kBps = <(1689600 * 32)>;
 517                 };
 518                 opp-1977600000 {
 519                         opp-hz = /bits/ 64 <1977600000>;
 520                         opp-peak-kBps = <(1689600 * 32)>;
 521                 };
 522                 opp-2073600000 {
 523                         opp-hz = /bits/ 64 <2073600000>;
 524                         opp-peak-kBps = <(1689600 * 32)>;
 525                 };
 526                 opp-2169600000 {
 527                         opp-hz = /bits/ 64 <2169600000>;
 528                         opp-peak-kBps = <(1689600 * 32)>;
 529                 };
 530                 opp-2284800000 {
 531                         opp-hz = /bits/ 64 <2284800000>;
 532                         opp-peak-kBps = <(1689600 * 32)>;
 533                 };
 534                 opp-2400000000 {
 535                         opp-hz = /bits/ 64 <2400000000>;
 536                         opp-peak-kBps = <(1689600 * 32)>;
 537                 };
 538                 opp-2496000000 {
 539                         opp-hz = /bits/ 64 <2496000000>;
 540                         opp-peak-kBps = <(1689600 * 32)>;
 541                 };
 542                 opp-2592000000 {
 543                         opp-hz = /bits/ 64 <2592000000>;
 544                         opp-peak-kBps = <(1689600 * 32)>;
 545                 };
 546                 opp-2688000000 {
 547                         opp-hz = /bits/ 64 <2688000000>;
 548                         opp-peak-kBps = <(1689600 * 32)>;
 549                 };
 550                 opp-2803200000 {
 551                         opp-hz = /bits/ 64 <2803200000>;
 552                         opp-peak-kBps = <(1689600 * 32)>;
 553                 };
 554                 opp-2899200000 {
 555                         opp-hz = /bits/ 64 <2899200000>;
 556                         opp-peak-kBps = <(1689600 * 32)>;
 557                 };
 558                 opp-2995200000 {
 559                         opp-hz = /bits/ 64 <2995200000>;
 560                         opp-peak-kBps = <(1689600 * 32)>;
 561                 };
 562         };
 563
 564         qup_opp_table_100mhz: opp-table-qup100mhz {
 565                 compatible = "operating-points-v2";
 566
 567                 opp-75000000 {
 568                         opp-hz = /bits/ 64 <75000000>;
 569                         required-opps = <&rpmhpd_opp_low_svs>;
 570                 };
 571
 572                 opp-100000000 {
 573                         opp-hz = /bits/ 64 <100000000>;
 574                         required-opps = <&rpmhpd_opp_svs>;
 575                 };
 576         };
 577
 578         pmu {
 579                 compatible = "arm,armv8-pmuv3";
 580                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 581         };
 582
 583         psci {
 584                 compatible = "arm,psci-1.0";
 585                 method = "smc";
 586
 587                 CPU_PD0: power-domain-cpu0 {
 588                         #power-domain-cells = <0>;
 589                         power-domains = <&CLUSTER_PD>;
 590                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 591                 };
 592
 593                 CPU_PD1: power-domain-cpu1 {
 594                         #power-domain-cells = <0>;
 595                         power-domains = <&CLUSTER_PD>;
 596                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 597                 };
 598
 599                 CPU_PD2: power-domain-cpu2 {
 600                         #power-domain-cells = <0>;
 601                         power-domains = <&CLUSTER_PD>;
 602                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 603                 };
 604
 605                 CPU_PD3: power-domain-cpu3 {
 606                         #power-domain-cells = <0>;
 607                         power-domains = <&CLUSTER_PD>;
 608                         domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
 609                 };
 610
 611                 CPU_PD4: power-domain-cpu4 {
 612                         #power-domain-cells = <0>;
 613                         power-domains = <&CLUSTER_PD>;
 614                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 615                 };
 616
 617                 CPU_PD5: power-domain-cpu5 {
 618                         #power-domain-cells = <0>;
 619                         power-domains = <&CLUSTER_PD>;
 620                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 621                 };
 622
 623                 CPU_PD6: power-domain-cpu6 {
 624                         #power-domain-cells = <0>;
 625                         power-domains = <&CLUSTER_PD>;
 626                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 627                 };
 628
 629                 CPU_PD7: power-domain-cpu7 {
 630                         #power-domain-cells = <0>;
 631                         power-domains = <&CLUSTER_PD>;
 632                         domain-idle-states = <&BIG_CPU_SLEEP_0>;
 633                 };
 634
 635                 CLUSTER_PD: power-domain-cpu-cluster0 {
 636                         #power-domain-cells = <0>;
 637                         domain-idle-states = <&CLUSTER_SLEEP_0>;
 638                 };
 639         };
 640
 641         reserved-memory {
 642                 #address-cells = <2>;
 643                 #size-cells = <2>;
 644                 ranges;
 645
 646                 reserved-region@80000000 {
 647                         reg = <0 0x80000000 0 0x860000>;
 648                         no-map;
 649                 };
 650
 651                 cmd_db: cmd-db-region@80860000 {
 652                         compatible = "qcom,cmd-db";
 653                         reg = <0 0x80860000 0 0x20000>;
 654                         no-map;
 655                 };
 656
 657                 reserved-region@80880000 {
 658                         reg = <0 0x80880000 0 0x80000>;
 659                         no-map;
 660                 };
 661
 662                 smem_mem: smem-region@80900000 {
 663                         compatible = "qcom,smem";
 664                         reg = <0 0x80900000 0 0x200000>;
 665                         no-map;
 666                         hwlocks = <&tcsr_mutex 3>;
 667                 };
 668
 669                 reserved-region@80b00000 {
 670                         reg = <0 0x80b00000 0 0x100000>;
 671                         no-map;
 672                 };
 673
 674                 reserved-region@83b00000 {
 675                         reg = <0 0x83b00000 0 0x1700000>;
 676                         no-map;
 677                 };
 678
 679                 reserved-region@85b00000 {
 680                         reg = <0 0x85b00000 0 0xc00000>;
 681                         no-map;
 682                 };
 683
 684                 pil_adsp_mem: adsp-region@86c00000 {
 685                         reg = <0 0x86c00000 0 0x2000000>;
 686                         no-map;
 687                 };
 688
 689                 pil_nsp0_mem: cdsp0-region@8a100000 {
 690                         reg = <0 0x8a100000 0 0x1e00000>;
 691                         no-map;
 692                 };
 693
 694                 pil_nsp1_mem: cdsp1-region@8c600000 {
 695                         reg = <0 0x8c600000 0 0x1e00000>;
 696                         no-map;
 697                 };
 698
 699                 reserved-region@aeb00000 {
 700                         reg = <0 0xaeb00000 0 0x16600000>;
 701                         no-map;
 702                 };
 703         };
 704
 705         smp2p-adsp {
 706                 compatible = "qcom,smp2p";
 707                 qcom,smem = <443>, <429>;
 708                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 709                                              IPCC_MPROC_SIGNAL_SMP2P
 710                                              IRQ_TYPE_EDGE_RISING>;
 711                 mboxes = <&ipcc IPCC_CLIENT_LPASS
 712                                 IPCC_MPROC_SIGNAL_SMP2P>;
 713
 714                 qcom,local-pid = <0>;
 715                 qcom,remote-pid = <2>;
 716
 717                 smp2p_adsp_out: master-kernel {
 718                         qcom,entry-name = "master-kernel";
 719                         #qcom,smem-state-cells = <1>;
 720                 };
 721
 722                 smp2p_adsp_in: slave-kernel {
 723                         qcom,entry-name = "slave-kernel";
 724                         interrupt-controller;
 725                         #interrupt-cells = <2>;
 726                 };
 727         };
 728
 729         smp2p-nsp0 {
 730                 compatible = "qcom,smp2p";
 731                 qcom,smem = <94>, <432>;
 732                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 733                                              IPCC_MPROC_SIGNAL_SMP2P
 734                                              IRQ_TYPE_EDGE_RISING>;
 735                 mboxes = <&ipcc IPCC_CLIENT_CDSP
 736                                 IPCC_MPROC_SIGNAL_SMP2P>;
 737
 738                 qcom,local-pid = <0>;
 739                 qcom,remote-pid = <5>;
 740
 741                 smp2p_nsp0_out: master-kernel {
 742                         qcom,entry-name = "master-kernel";
 743                         #qcom,smem-state-cells = <1>;
 744                 };
 745
 746                 smp2p_nsp0_in: slave-kernel {
 747                         qcom,entry-name = "slave-kernel";
 748                         interrupt-controller;
 749                         #interrupt-cells = <2>;
 750                 };
 751         };
 752
 753         smp2p-nsp1 {
 754                 compatible = "qcom,smp2p";
 755                 qcom,smem = <617>, <616>;
 756                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
 757                                              IPCC_MPROC_SIGNAL_SMP2P
 758                                              IRQ_TYPE_EDGE_RISING>;
 759                 mboxes = <&ipcc IPCC_CLIENT_NSP1
 760                                 IPCC_MPROC_SIGNAL_SMP2P>;
 761
 762                 qcom,local-pid = <0>;
 763                 qcom,remote-pid = <12>;
 764
 765                 smp2p_nsp1_out: master-kernel {
 766                         qcom,entry-name = "master-kernel";
 767                         #qcom,smem-state-cells = <1>;
 768                 };
 769
 770                 smp2p_nsp1_in: slave-kernel {
 771                         qcom,entry-name = "slave-kernel";
 772                         interrupt-controller;
 773                         #interrupt-cells = <2>;
 774                 };
 775         };
 776
 777         soc: soc@0 {
 778                 compatible = "simple-bus";
 779                 #address-cells = <2>;
 780                 #size-cells = <2>;
 781                 ranges = <0 0 0 0 0x10 0>;
 782                 dma-ranges = <0 0 0 0 0x10 0>;
 783
 784                 ethernet0: ethernet@20000 {
 785                         compatible = "qcom,sc8280xp-ethqos";
 786                         reg = <0x0 0x00020000 0x0 0x10000>,
 787                               <0x0 0x00036000 0x0 0x100>;
 788                         reg-names = "stmmaceth", "rgmii";
 789
 790                         clocks = <&gcc GCC_EMAC0_AXI_CLK>,
 791                                  <&gcc GCC_EMAC0_SLV_AHB_CLK>,
 792                                  <&gcc GCC_EMAC0_PTP_CLK>,
 793                                  <&gcc GCC_EMAC0_RGMII_CLK>;
 794                         clock-names = "stmmaceth",
 795                                       "pclk",
 796                                       "ptp_ref",
 797                                       "rgmii";
 798
 799                         interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
 800                                      <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
 801                         interrupt-names = "macirq", "eth_lpi";
 802
 803                         iommus = <&apps_smmu 0x4c0 0xf>;
 804                         power-domains = <&gcc EMAC_0_GDSC>;
 805
 806                         snps,tso;
 807                         snps,pbl = <32>;
 808                         rx-fifo-depth = <4096>;
 809                         tx-fifo-depth = <4096>;
 810
 811                         status = "disabled";
 812                 };
 813
 814                 gcc: clock-controller@100000 {
 815                         compatible = "qcom,gcc-sc8280xp";
 816                         reg = <0x0 0x00100000 0x0 0x1f0000>;
 817                         #clock-cells = <1>;
 818                         #reset-cells = <1>;
 819                         #power-domain-cells = <1>;
 820                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 821                                  <&sleep_clk>,
 822                                  <0>,
 823                                  <0>,
 824                                  <0>,
 825                                  <0>,
 826                                  <0>,
 827                                  <0>,
 828                                  <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 829                                  <0>,
 830                                  <0>,
 831                                  <0>,
 832                                  <0>,
 833                                  <0>,
 834                                  <0>,
 835                                  <0>,
 836                                  <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 837                                  <0>,
 838                                  <0>,
 839                                  <0>,
 840                                  <0>,
 841                                  <0>,
 842                                  <0>,
 843                                  <0>,
 844                                  <0>,
 845                                  <0>,
 846                                  <&pcie2a_phy>,
 847                                  <&pcie2b_phy>,
 848                                  <&pcie3a_phy>,
 849                                  <&pcie3b_phy>,
 850                                  <&pcie4_phy>,
 851                                  <0>,
 852                                  <0>;
 853                         power-domains = <&rpmhpd SC8280XP_CX>;
 854                 };
 855
 856                 ipcc: mailbox@408000 {
 857                         compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc";
 858                         reg = <0 0x00408000 0 0x1000>;
 859                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 860                         interrupt-controller;
 861                         #interrupt-cells = <3>;
 862                         #mbox-cells = <2>;
 863                 };
 864
 865                 qup2: geniqup@8c0000 {
 866                         compatible = "qcom,geni-se-qup";
 867                         reg = <0 0x008c0000 0 0x2000>;
 868                         clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 869                                  <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 870                         clock-names = "m-ahb", "s-ahb";
 871                         iommus = <&apps_smmu 0xa3 0>;
 872
 873                         #address-cells = <2>;
 874                         #size-cells = <2>;
 875                         ranges;
 876
 877                         status = "disabled";
 878
 879                         i2c16: i2c@880000 {
 880                                 compatible = "qcom,geni-i2c";
 881                                 reg = <0 0x00880000 0 0x4000>;
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 885                                 clock-names = "se";
 886                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 887                                 power-domains = <&rpmhpd SC8280XP_CX>;
 888                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 889                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 890                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 891                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 892                                 status = "disabled";
 893                         };
 894
 895                         spi16: spi@880000 {
 896                                 compatible = "qcom,geni-spi";
 897                                 reg = <0 0x00880000 0 0x4000>;
 898                                 #address-cells = <1>;
 899                                 #size-cells = <0>;
 900                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 901                                 clock-names = "se";
 902                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
 903                                 power-domains = <&rpmhpd SC8280XP_CX>;
 904                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 905                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 906                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 907                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 908                                 status = "disabled";
 909                         };
 910
 911                         i2c17: i2c@884000 {
 912                                 compatible = "qcom,geni-i2c";
 913                                 reg = <0 0x00884000 0 0x4000>;
 914                                 #address-cells = <1>;
 915                                 #size-cells = <0>;
 916                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 917                                 clock-names = "se";
 918                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 919                                 power-domains = <&rpmhpd SC8280XP_CX>;
 920                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 921                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 922                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 923                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 924                                 status = "disabled";
 925                         };
 926
 927                         spi17: spi@884000 {
 928                                 compatible = "qcom,geni-spi";
 929                                 reg = <0 0x00884000 0 0x4000>;
 930                                 #address-cells = <1>;
 931                                 #size-cells = <0>;
 932                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 933                                 clock-names = "se";
 934                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 935                                 power-domains = <&rpmhpd SC8280XP_CX>;
 936                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 937                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 938                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 939                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 940                                 status = "disabled";
 941                         };
 942
 943                         uart17: serial@884000 {
 944                                 compatible = "qcom,geni-uart";
 945                                 reg = <0 0x00884000 0 0x4000>;
 946                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 947                                 clock-names = "se";
 948                                 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
 949                                 operating-points-v2 = <&qup_opp_table_100mhz>;
 950                                 power-domains = <&rpmhpd SC8280XP_CX>;
 951                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 952                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>;
 953                                 interconnect-names = "qup-core", "qup-config";
 954                                 status = "disabled";
 955                         };
 956
 957                         i2c18: i2c@888000 {
 958                                 compatible = "qcom,geni-i2c";
 959                                 reg = <0 0x00888000 0 0x4000>;
 960                                 #address-cells = <1>;
 961                                 #size-cells = <0>;
 962                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 963                                 clock-names = "se";
 964                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 965                                 power-domains = <&rpmhpd SC8280XP_CX>;
 966                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 967                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 968                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 969                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 970                                 status = "disabled";
 971                         };
 972
 973                         spi18: spi@888000 {
 974                                 compatible = "qcom,geni-spi";
 975                                 reg = <0 0x00888000 0 0x4000>;
 976                                 #address-cells = <1>;
 977                                 #size-cells = <0>;
 978                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
 979                                 clock-names = "se";
 980                                 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
 981                                 power-domains = <&rpmhpd SC8280XP_CX>;
 982                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 983                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
 984                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
 985                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
 986                                 status = "disabled";
 987                         };
 988
 989                         i2c19: i2c@88c000 {
 990                                 compatible = "qcom,geni-i2c";
 991                                 reg = <0 0x0088c000 0 0x4000>;
 992                                 #address-cells = <1>;
 993                                 #size-cells = <0>;
 994                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
 995                                 clock-names = "se";
 996                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
 997                                 power-domains = <&rpmhpd SC8280XP_CX>;
 998                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
 999                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1000                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1001                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1002                                 status = "disabled";
1003                         };
1004
1005                         spi19: spi@88c000 {
1006                                 compatible = "qcom,geni-spi";
1007                                 reg = <0 0x0088c000 0 0x4000>;
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1011                                 clock-names = "se";
1012                                 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
1013                                 power-domains = <&rpmhpd SC8280XP_CX>;
1014                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1015                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1016                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1017                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1018                                 status = "disabled";
1019                         };
1020
1021                         i2c20: i2c@890000 {
1022                                 compatible = "qcom,geni-i2c";
1023                                 reg = <0 0x00890000 0 0x4000>;
1024                                 #address-cells = <1>;
1025                                 #size-cells = <0>;
1026                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1027                                 clock-names = "se";
1028                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1029                                 power-domains = <&rpmhpd SC8280XP_CX>;
1030                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1031                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1032                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1033                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1034                                 status = "disabled";
1035                         };
1036
1037                         spi20: spi@890000 {
1038                                 compatible = "qcom,geni-spi";
1039                                 reg = <0 0x00890000 0 0x4000>;
1040                                 #address-cells = <1>;
1041                                 #size-cells = <0>;
1042                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1043                                 clock-names = "se";
1044                                 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
1045                                 power-domains = <&rpmhpd SC8280XP_CX>;
1046                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1047                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1048                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1049                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1050                                 status = "disabled";
1051                         };
1052
1053                         i2c21: i2c@894000 {
1054                                 compatible = "qcom,geni-i2c";
1055                                 reg = <0 0x00894000 0 0x4000>;
1056                                 clock-names = "se";
1057                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1058                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1059                                 #address-cells = <1>;
1060                                 #size-cells = <0>;
1061                                 power-domains = <&rpmhpd SC8280XP_CX>;
1062                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1063                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1064                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1065                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1066                                 status = "disabled";
1067                         };
1068
1069                         spi21: spi@894000 {
1070                                 compatible = "qcom,geni-spi";
1071                                 reg = <0 0x00894000 0 0x4000>;
1072                                 #address-cells = <1>;
1073                                 #size-cells = <0>;
1074                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1075                                 clock-names = "se";
1076                                 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
1077                                 power-domains = <&rpmhpd SC8280XP_CX>;
1078                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1080                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1081                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1082                                 status = "disabled";
1083                         };
1084
1085                         i2c22: i2c@898000 {
1086                                 compatible = "qcom,geni-i2c";
1087                                 reg = <0 0x00898000 0 0x4000>;
1088                                 #address-cells = <1>;
1089                                 #size-cells = <0>;
1090                                 clock-names = "se";
1091                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1092                                 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1093                                 power-domains = <&rpmhpd SC8280XP_CX>;
1094                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1095                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1096                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1097                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1098                                 status = "disabled";
1099                         };
1100
1101                         spi22: spi@898000 {
1102                                 compatible = "qcom,geni-spi";
1103                                 reg = <0 0x00898000 0 0x4000>;
1104                                 #address-cells = <1>;
1105                                 #size-cells = <0>;
1106                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1107                                 clock-names = "se";
1108                                 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
1109                                 power-domains = <&rpmhpd SC8280XP_CX>;
1110                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1111                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1112                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1113                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1114                                 status = "disabled";
1115                         };
1116
1117                         i2c23: i2c@89c000 {
1118                                 compatible = "qcom,geni-i2c";
1119                                 reg = <0 0x0089c000 0 0x4000>;
1120                                 #address-cells = <1>;
1121                                 #size-cells = <0>;
1122                                 clock-names = "se";
1123                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1124                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1125                                 power-domains = <&rpmhpd SC8280XP_CX>;
1126                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1127                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1128                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1129                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1130                                 status = "disabled";
1131                         };
1132
1133                         spi23: spi@89c000 {
1134                                 compatible = "qcom,geni-spi";
1135                                 reg = <0 0x0089c000 0 0x4000>;
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1139                                 clock-names = "se";
1140                                 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
1141                                 power-domains = <&rpmhpd SC8280XP_CX>;
1142                                 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1143                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>,
1144                                                 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1145                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1146                                 status = "disabled";
1147                         };
1148                 };
1149
1150                 qup0: geniqup@9c0000 {
1151                         compatible = "qcom,geni-se-qup";
1152                         reg = <0 0x009c0000 0 0x6000>;
1153                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1154                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1155                         clock-names = "m-ahb", "s-ahb";
1156                         iommus = <&apps_smmu 0x563 0>;
1157
1158                         #address-cells = <2>;
1159                         #size-cells = <2>;
1160                         ranges;
1161
1162                         status = "disabled";
1163
1164                         i2c0: i2c@980000 {
1165                                 compatible = "qcom,geni-i2c";
1166                                 reg = <0 0x00980000 0 0x4000>;
1167                                 #address-cells = <1>;
1168                                 #size-cells = <0>;
1169                                 clock-names = "se";
1170                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1171                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1172                                 power-domains = <&rpmhpd SC8280XP_CX>;
1173                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1174                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1175                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1176                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1177                                 status = "disabled";
1178                         };
1179
1180                         spi0: spi@980000 {
1181                                 compatible = "qcom,geni-spi";
1182                                 reg = <0 0x00980000 0 0x4000>;
1183                                 #address-cells = <1>;
1184                                 #size-cells = <0>;
1185                                 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
1186                                 clock-names = "se";
1187                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
1188                                 power-domains = <&rpmhpd SC8280XP_CX>;
1189                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1190                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1191                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1192                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1193                                 status = "disabled";
1194                         };
1195
1196                         i2c1: i2c@984000 {
1197                                 compatible = "qcom,geni-i2c";
1198                                 reg = <0 0x00984000 0 0x4000>;
1199                                 #address-cells = <1>;
1200                                 #size-cells = <0>;
1201                                 clock-names = "se";
1202                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1203                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1204                                 power-domains = <&rpmhpd SC8280XP_CX>;
1205                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1206                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1207                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1208                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1209                                 status = "disabled";
1210                         };
1211
1212                         spi1: spi@984000 {
1213                                 compatible = "qcom,geni-spi";
1214                                 reg = <0 0x00984000 0 0x4000>;
1215                                 #address-cells = <1>;
1216                                 #size-cells = <0>;
1217                                 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1218                                 clock-names = "se";
1219                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
1220                                 power-domains = <&rpmhpd SC8280XP_CX>;
1221                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1222                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1223                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1224                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1225                                 status = "disabled";
1226                         };
1227
1228                         i2c2: i2c@988000 {
1229                                 compatible = "qcom,geni-i2c";
1230                                 reg = <0 0x00988000 0 0x4000>;
1231                                 #address-cells = <1>;
1232                                 #size-cells = <0>;
1233                                 clock-names = "se";
1234                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1235                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1236                                 power-domains = <&rpmhpd SC8280XP_CX>;
1237                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1238                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1239                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1240                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1241                                 status = "disabled";
1242                         };
1243
1244                         spi2: spi@988000 {
1245                                 compatible = "qcom,geni-spi";
1246                                 reg = <0 0x00988000 0 0x4000>;
1247                                 #address-cells = <1>;
1248                                 #size-cells = <0>;
1249                                 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1250                                 clock-names = "se";
1251                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1252                                 power-domains = <&rpmhpd SC8280XP_CX>;
1253                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1254                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1255                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1256                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1257                                 status = "disabled";
1258                         };
1259
1260                         uart2: serial@988000 {
1261                                 compatible = "qcom,geni-uart";
1262                                 reg = <0 0x00988000 0 0x4000>;
1263                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1264                                 clock-names = "se";
1265                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
1266                                 operating-points-v2 = <&qup_opp_table_100mhz>;
1267                                 power-domains = <&rpmhpd SC8280XP_CX>;
1268                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1269                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1270                                 interconnect-names = "qup-core", "qup-config";
1271                                 status = "disabled";
1272                         };
1273
1274                         i2c3: i2c@98c000 {
1275                                 compatible = "qcom,geni-i2c";
1276                                 reg = <0 0x0098c000 0 0x4000>;
1277                                 #address-cells = <1>;
1278                                 #size-cells = <0>;
1279                                 clock-names = "se";
1280                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1281                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1282                                 power-domains = <&rpmhpd SC8280XP_CX>;
1283                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1284                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1285                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1286                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1287                                 status = "disabled";
1288                         };
1289
1290                         spi3: spi@98c000 {
1291                                 compatible = "qcom,geni-spi";
1292                                 reg = <0 0x0098c000 0 0x4000>;
1293                                 #address-cells = <1>;
1294                                 #size-cells = <0>;
1295                                 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1296                                 clock-names = "se";
1297                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
1298                                 power-domains = <&rpmhpd SC8280XP_CX>;
1299                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1301                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1302                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1303                                 status = "disabled";
1304                         };
1305
1306                         i2c4: i2c@990000 {
1307                                 compatible = "qcom,geni-i2c";
1308                                 reg = <0 0x00990000 0 0x4000>;
1309                                 clock-names = "se";
1310                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1311                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1312                                 #address-cells = <1>;
1313                                 #size-cells = <0>;
1314                                 power-domains = <&rpmhpd SC8280XP_CX>;
1315                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1316                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1317                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1318                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1319                                 status = "disabled";
1320                         };
1321
1322                         spi4: spi@990000 {
1323                                 compatible = "qcom,geni-spi";
1324                                 reg = <0 0x00990000 0 0x4000>;
1325                                 #address-cells = <1>;
1326                                 #size-cells = <0>;
1327                                 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1328                                 clock-names = "se";
1329                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1330                                 power-domains = <&rpmhpd SC8280XP_CX>;
1331                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1332                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1333                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1334                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1335                                 status = "disabled";
1336                         };
1337
1338                         i2c5: i2c@994000 {
1339                                 compatible = "qcom,geni-i2c";
1340                                 reg = <0 0x00994000 0 0x4000>;
1341                                 #address-cells = <1>;
1342                                 #size-cells = <0>;
1343                                 clock-names = "se";
1344                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1345                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1346                                 power-domains = <&rpmhpd SC8280XP_CX>;
1347                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1348                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1349                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1350                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1351                                 status = "disabled";
1352                         };
1353
1354                         spi5: spi@994000 {
1355                                 compatible = "qcom,geni-spi";
1356                                 reg = <0 0x00994000 0 0x4000>;
1357                                 #address-cells = <1>;
1358                                 #size-cells = <0>;
1359                                 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1360                                 clock-names = "se";
1361                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1362                                 power-domains = <&rpmhpd SC8280XP_CX>;
1363                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1364                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1365                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1366                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1367                                 status = "disabled";
1368                         };
1369
1370                         i2c6: i2c@998000 {
1371                                 compatible = "qcom,geni-i2c";
1372                                 reg = <0 0x00998000 0 0x4000>;
1373                                 #address-cells = <1>;
1374                                 #size-cells = <0>;
1375                                 clock-names = "se";
1376                                 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
1377                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1378                                 power-domains = <&rpmhpd SC8280XP_CX>;
1379                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1380                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1381                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1382                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1383                                 status = "disabled";
1384                         };
1385
1386                         spi6: spi@998000 {
1387                                 compatible = "qcom,geni-spi";
1388                                 reg = <0 0x00998000 0 0x4000>;
1389                                 #address-cells = <1>;
1390                                 #size-cells = <0>;
1391                                 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1392                                 clock-names = "se";
1393                                 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
1394                                 power-domains = <&rpmhpd SC8280XP_CX>;
1395                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1396                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1397                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1398                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1399                                 status = "disabled";
1400                         };
1401
1402                         i2c7: i2c@99c000 {
1403                                 compatible = "qcom,geni-i2c";
1404                                 reg = <0 0x0099c000 0 0x4000>;
1405                                 #address-cells = <1>;
1406                                 #size-cells = <0>;
1407                                 clock-names = "se";
1408                                 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
1409                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1410                                 power-domains = <&rpmhpd SC8280XP_CX>;
1411                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1412                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1413                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1414                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1415                                 status = "disabled";
1416                         };
1417
1418                         spi7: spi@99c000 {
1419                                 compatible = "qcom,geni-spi";
1420                                 reg = <0 0x0099c000 0 0x4000>;
1421                                 #address-cells = <1>;
1422                                 #size-cells = <0>;
1423                                 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1424                                 clock-names = "se";
1425                                 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
1426                                 power-domains = <&rpmhpd SC8280XP_CX>;
1427                                 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1428                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1429                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1430                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1431                                 status = "disabled";
1432                         };
1433                 };
1434
1435                 qup1: geniqup@ac0000 {
1436                         compatible = "qcom,geni-se-qup";
1437                         reg = <0 0x00ac0000 0 0x6000>;
1438                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1439                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1440                         clock-names = "m-ahb", "s-ahb";
1441                         iommus = <&apps_smmu 0x83 0>;
1442
1443                         #address-cells = <2>;
1444                         #size-cells = <2>;
1445                         ranges;
1446
1447                         status = "disabled";
1448
1449                         i2c8: i2c@a80000 {
1450                                 compatible = "qcom,geni-i2c";
1451                                 reg = <0 0x00a80000 0 0x4000>;
1452                                 #address-cells = <1>;
1453                                 #size-cells = <0>;
1454                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1455                                 clock-names = "se";
1456                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1457                                 power-domains = <&rpmhpd SC8280XP_CX>;
1458                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1459                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1460                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1461                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1462                                 status = "disabled";
1463                         };
1464
1465                         spi8: spi@a80000 {
1466                                 compatible = "qcom,geni-spi";
1467                                 reg = <0 0x00a80000 0 0x4000>;
1468                                 #address-cells = <1>;
1469                                 #size-cells = <0>;
1470                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1471                                 clock-names = "se";
1472                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1473                                 power-domains = <&rpmhpd SC8280XP_CX>;
1474                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1475                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1476                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1477                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1478                                 status = "disabled";
1479                         };
1480
1481                         i2c9: i2c@a84000 {
1482                                 compatible = "qcom,geni-i2c";
1483                                 reg = <0 0x00a84000 0 0x4000>;
1484                                 #address-cells = <1>;
1485                                 #size-cells = <0>;
1486                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1487                                 clock-names = "se";
1488                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1489                                 power-domains = <&rpmhpd SC8280XP_CX>;
1490                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1491                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1492                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1493                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1494                                 status = "disabled";
1495                         };
1496
1497                         spi9: spi@a84000 {
1498                                 compatible = "qcom,geni-spi";
1499                                 reg = <0 0x00a84000 0 0x4000>;
1500                                 #address-cells = <1>;
1501                                 #size-cells = <0>;
1502                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1503                                 clock-names = "se";
1504                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1505                                 power-domains = <&rpmhpd SC8280XP_CX>;
1506                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1507                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1508                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1509                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1510                                 status = "disabled";
1511                         };
1512
1513                         i2c10: i2c@a88000 {
1514                                 compatible = "qcom,geni-i2c";
1515                                 reg = <0 0x00a88000 0 0x4000>;
1516                                 #address-cells = <1>;
1517                                 #size-cells = <0>;
1518                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1519                                 clock-names = "se";
1520                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1521                                 power-domains = <&rpmhpd SC8280XP_CX>;
1522                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1523                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1524                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1525                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1526                                 status = "disabled";
1527                         };
1528
1529                         spi10: spi@a88000 {
1530                                 compatible = "qcom,geni-spi";
1531                                 reg = <0 0x00a88000 0 0x4000>;
1532                                 #address-cells = <1>;
1533                                 #size-cells = <0>;
1534                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1535                                 clock-names = "se";
1536                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1537                                 power-domains = <&rpmhpd SC8280XP_CX>;
1538                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1539                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1540                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1541                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1542                                 status = "disabled";
1543                         };
1544
1545                         i2c11: i2c@a8c000 {
1546                                 compatible = "qcom,geni-i2c";
1547                                 reg = <0 0x00a8c000 0 0x4000>;
1548                                 #address-cells = <1>;
1549                                 #size-cells = <0>;
1550                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1551                                 clock-names = "se";
1552                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1553                                 power-domains = <&rpmhpd SC8280XP_CX>;
1554                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1555                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1556                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1557                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1558                                 status = "disabled";
1559                         };
1560
1561                         spi11: spi@a8c000 {
1562                                 compatible = "qcom,geni-spi";
1563                                 reg = <0 0x00a8c000 0 0x4000>;
1564                                 #address-cells = <1>;
1565                                 #size-cells = <0>;
1566                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1567                                 clock-names = "se";
1568                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1569                                 power-domains = <&rpmhpd SC8280XP_CX>;
1570                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1571                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1572                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1573                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1574                                 status = "disabled";
1575                         };
1576
1577                         i2c12: i2c@a90000 {
1578                                 compatible = "qcom,geni-i2c";
1579                                 reg = <0 0x00a90000 0 0x4000>;
1580                                 #address-cells = <1>;
1581                                 #size-cells = <0>;
1582                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1583                                 clock-names = "se";
1584                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1585                                 power-domains = <&rpmhpd SC8280XP_CX>;
1586                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1587                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1588                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1589                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1590                                 status = "disabled";
1591                         };
1592
1593                         spi12: spi@a90000 {
1594                                 compatible = "qcom,geni-spi";
1595                                 reg = <0 0x00a90000 0 0x4000>;
1596                                 #address-cells = <1>;
1597                                 #size-cells = <0>;
1598                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1599                                 clock-names = "se";
1600                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1601                                 power-domains = <&rpmhpd SC8280XP_CX>;
1602                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1603                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1604                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1605                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1606                                 status = "disabled";
1607                         };
1608
1609                         i2c13: i2c@a94000 {
1610                                 compatible = "qcom,geni-i2c";
1611                                 reg = <0 0x00a94000 0 0x4000>;
1612                                 #address-cells = <1>;
1613                                 #size-cells = <0>;
1614                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1615                                 clock-names = "se";
1616                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1617                                 power-domains = <&rpmhpd SC8280XP_CX>;
1618                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1619                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1620                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1621                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1622                                 status = "disabled";
1623                         };
1624
1625                         spi13: spi@a94000 {
1626                                 compatible = "qcom,geni-spi";
1627                                 reg = <0 0x00a94000 0 0x4000>;
1628                                 #address-cells = <1>;
1629                                 #size-cells = <0>;
1630                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1631                                 clock-names = "se";
1632                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1633                                 power-domains = <&rpmhpd SC8280XP_CX>;
1634                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1635                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1636                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1637                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1638                                 status = "disabled";
1639                         };
1640
1641                         i2c14: i2c@a98000 {
1642                                 compatible = "qcom,geni-i2c";
1643                                 reg = <0 0x00a98000 0 0x4000>;
1644                                 #address-cells = <1>;
1645                                 #size-cells = <0>;
1646                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1647                                 clock-names = "se";
1648                                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1649                                 power-domains = <&rpmhpd SC8280XP_CX>;
1650                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1651                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1652                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1653                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1654                                 status = "disabled";
1655                         };
1656
1657                         spi14: spi@a98000 {
1658                                 compatible = "qcom,geni-spi";
1659                                 reg = <0 0x00a98000 0 0x4000>;
1660                                 #address-cells = <1>;
1661                                 #size-cells = <0>;
1662                                 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1663                                 clock-names = "se";
1664                                 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>;
1665                                 power-domains = <&rpmhpd SC8280XP_CX>;
1666                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1667                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1668                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1669                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1670                                 status = "disabled";
1671                         };
1672
1673                         i2c15: i2c@a9c000 {
1674                                 compatible = "qcom,geni-i2c";
1675                                 reg = <0 0x00a9c000 0 0x4000>;
1676                                 #address-cells = <1>;
1677                                 #size-cells = <0>;
1678                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1679                                 clock-names = "se";
1680                                 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1681                                 power-domains = <&rpmhpd SC8280XP_CX>;
1682                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1683                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1684                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1685                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1686                                 status = "disabled";
1687                         };
1688
1689                         spi15: spi@a9c000 {
1690                                 compatible = "qcom,geni-spi";
1691                                 reg = <0 0x00a9c000 0 0x4000>;
1692                                 #address-cells = <1>;
1693                                 #size-cells = <0>;
1694                                 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
1695                                 clock-names = "se";
1696                                 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
1697                                 power-domains = <&rpmhpd SC8280XP_CX>;
1698                                 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1699                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1700                                                 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1701                                 interconnect-names = "qup-core", "qup-config", "qup-memory";
1702                                 status = "disabled";
1703                         };
1704                 };
1705
1706                 rng: rng@10d3000 {
1707                         compatible = "qcom,prng-ee";
1708                         reg = <0 0x010d3000 0 0x1000>;
1709                         clocks = <&rpmhcc RPMH_HWKM_CLK>;
1710                         clock-names = "core";
1711                 };
1712
1713                 pcie4: pcie@1c00000 {
1714                         device_type = "pci";
1715                         compatible = "qcom,pcie-sc8280xp";
1716                         reg = <0x0 0x01c00000 0x0 0x3000>,
1717                               <0x0 0x30000000 0x0 0xf1d>,
1718                               <0x0 0x30000f20 0x0 0xa8>,
1719                               <0x0 0x30001000 0x0 0x1000>,
1720                               <0x0 0x30100000 0x0 0x100000>,
1721                               <0x0 0x01c03000 0x0 0x1000>;
1722                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1723                         #address-cells = <3>;
1724                         #size-cells = <2>;
1725                         ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
1726                                  <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
1727                         bus-range = <0x00 0xff>;
1728
1729                         dma-coherent;
1730
1731                         linux,pci-domain = <6>;
1732                         num-lanes = <1>;
1733
1734                         interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1735                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1736                                      <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1738                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1739
1740                         #interrupt-cells = <1>;
1741                         interrupt-map-mask = <0 0 0 0x7>;
1742                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1743                                         <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1744                                         <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1745                                         <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1746
1747                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1748                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1749                                  <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
1750                                  <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
1751                                  <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
1752                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1753                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1754                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
1755                                  <&gcc GCC_CNOC_PCIE4_QX_CLK>;
1756                         clock-names = "aux",
1757                                       "cfg",
1758                                       "bus_master",
1759                                       "bus_slave",
1760                                       "slave_q2a",
1761                                       "ddrss_sf_tbu",
1762                                       "noc_aggr_4",
1763                                       "noc_aggr_south_sf",
1764                                       "cnoc_qx";
1765
1766                         assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
1767                         assigned-clock-rates = <19200000>;
1768
1769                         interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
1770                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
1771                         interconnect-names = "pcie-mem", "cpu-pcie";
1772
1773                         resets = <&gcc GCC_PCIE_4_BCR>;
1774                         reset-names = "pci";
1775
1776                         power-domains = <&gcc PCIE_4_GDSC>;
1777
1778                         phys = <&pcie4_phy>;
1779                         phy-names = "pciephy";
1780
1781                         status = "disabled";
1782                 };
1783
1784                 pcie4_phy: phy@1c06000 {
1785                         compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
1786                         reg = <0x0 0x01c06000 0x0 0x2000>;
1787
1788                         clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
1789                                  <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
1790                                  <&gcc GCC_PCIE_4_CLKREF_CLK>,
1791                                  <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
1792                                  <&gcc GCC_PCIE_4_PIPE_CLK>,
1793                                  <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
1794                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1795                                       "pipe", "pipediv2";
1796
1797                         assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
1798                         assigned-clock-rates = <100000000>;
1799
1800                         power-domains = <&gcc PCIE_4_GDSC>;
1801
1802                         resets = <&gcc GCC_PCIE_4_PHY_BCR>;
1803                         reset-names = "phy";
1804
1805                         #clock-cells = <0>;
1806                         clock-output-names = "pcie_4_pipe_clk";
1807
1808                         #phy-cells = <0>;
1809
1810                         status = "disabled";
1811                 };
1812
1813                 pcie3b: pcie@1c08000 {
1814                         device_type = "pci";
1815                         compatible = "qcom,pcie-sc8280xp";
1816                         reg = <0x0 0x01c08000 0x0 0x3000>,
1817                               <0x0 0x32000000 0x0 0xf1d>,
1818                               <0x0 0x32000f20 0x0 0xa8>,
1819                               <0x0 0x32001000 0x0 0x1000>,
1820                               <0x0 0x32100000 0x0 0x100000>,
1821                               <0x0 0x01c0b000 0x0 0x1000>;
1822                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1823                         #address-cells = <3>;
1824                         #size-cells = <2>;
1825                         ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
1826                                  <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
1827                         bus-range = <0x00 0xff>;
1828
1829                         dma-coherent;
1830
1831                         linux,pci-domain = <5>;
1832                         num-lanes = <2>;
1833
1834                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1835                                      <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1836                                      <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1837                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1838                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1839
1840                         #interrupt-cells = <1>;
1841                         interrupt-map-mask = <0 0 0 0x7>;
1842                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
1843                                         <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
1844                                         <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
1845                                         <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
1846
1847                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1848                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1849                                  <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
1850                                  <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
1851                                  <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
1852                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1853                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1854                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1855                         clock-names = "aux",
1856                                       "cfg",
1857                                       "bus_master",
1858                                       "bus_slave",
1859                                       "slave_q2a",
1860                                       "ddrss_sf_tbu",
1861                                       "noc_aggr_4",
1862                                       "noc_aggr_south_sf";
1863
1864                         assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
1865                         assigned-clock-rates = <19200000>;
1866
1867                         interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
1868                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
1869                         interconnect-names = "pcie-mem", "cpu-pcie";
1870
1871                         resets = <&gcc GCC_PCIE_3B_BCR>;
1872                         reset-names = "pci";
1873
1874                         power-domains = <&gcc PCIE_3B_GDSC>;
1875
1876                         phys = <&pcie3b_phy>;
1877                         phy-names = "pciephy";
1878
1879                         status = "disabled";
1880                 };
1881
1882                 pcie3b_phy: phy@1c0e000 {
1883                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
1884                         reg = <0x0 0x01c0e000 0x0 0x2000>;
1885
1886                         clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
1887                                  <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
1888                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1889                                  <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
1890                                  <&gcc GCC_PCIE_3B_PIPE_CLK>,
1891                                  <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
1892                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1893                                       "pipe", "pipediv2";
1894
1895                         assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
1896                         assigned-clock-rates = <100000000>;
1897
1898                         power-domains = <&gcc PCIE_3B_GDSC>;
1899
1900                         resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
1901                         reset-names = "phy";
1902
1903                         #clock-cells = <0>;
1904                         clock-output-names = "pcie_3b_pipe_clk";
1905
1906                         #phy-cells = <0>;
1907
1908                         status = "disabled";
1909                 };
1910
1911                 pcie3a: pcie@1c10000 {
1912                         device_type = "pci";
1913                         compatible = "qcom,pcie-sc8280xp";
1914                         reg = <0x0 0x01c10000 0x0 0x3000>,
1915                               <0x0 0x34000000 0x0 0xf1d>,
1916                               <0x0 0x34000f20 0x0 0xa8>,
1917                               <0x0 0x34001000 0x0 0x1000>,
1918                               <0x0 0x34100000 0x0 0x100000>,
1919                               <0x0 0x01c13000 0x0 0x1000>;
1920                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
1921                         #address-cells = <3>;
1922                         #size-cells = <2>;
1923                         ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
1924                                  <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
1925                         bus-range = <0x00 0xff>;
1926
1927                         dma-coherent;
1928
1929                         linux,pci-domain = <4>;
1930                         num-lanes = <4>;
1931
1932                         interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
1933                                      <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
1934                                      <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
1935                                      <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1936                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
1937
1938                         #interrupt-cells = <1>;
1939                         interrupt-map-mask = <0 0 0 0x7>;
1940                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
1941                                         <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
1942                                         <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
1943                                         <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
1944
1945                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1946                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1947                                  <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
1948                                  <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
1949                                  <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
1950                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
1951                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
1952                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
1953                         clock-names = "aux",
1954                                       "cfg",
1955                                       "bus_master",
1956                                       "bus_slave",
1957                                       "slave_q2a",
1958                                       "ddrss_sf_tbu",
1959                                       "noc_aggr_4",
1960                                       "noc_aggr_south_sf";
1961
1962                         assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
1963                         assigned-clock-rates = <19200000>;
1964
1965                         interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
1966                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
1967                         interconnect-names = "pcie-mem", "cpu-pcie";
1968
1969                         resets = <&gcc GCC_PCIE_3A_BCR>;
1970                         reset-names = "pci";
1971
1972                         power-domains = <&gcc PCIE_3A_GDSC>;
1973
1974                         phys = <&pcie3a_phy>;
1975                         phy-names = "pciephy";
1976
1977                         status = "disabled";
1978                 };
1979
1980                 pcie3a_phy: phy@1c14000 {
1981                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
1982                         reg = <0x0 0x01c14000 0x0 0x2000>,
1983                               <0x0 0x01c16000 0x0 0x2000>;
1984
1985                         clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
1986                                  <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
1987                                  <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
1988                                  <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
1989                                  <&gcc GCC_PCIE_3A_PIPE_CLK>,
1990                                  <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
1991                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
1992                                       "pipe", "pipediv2";
1993
1994                         assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
1995                         assigned-clock-rates = <100000000>;
1996
1997                         power-domains = <&gcc PCIE_3A_GDSC>;
1998
1999                         resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
2000                         reset-names = "phy";
2001
2002                         qcom,4ln-config-sel = <&tcsr 0xa044 1>;
2003
2004                         #clock-cells = <0>;
2005                         clock-output-names = "pcie_3a_pipe_clk";
2006
2007                         #phy-cells = <0>;
2008
2009                         status = "disabled";
2010                 };
2011
2012                 pcie2b: pcie@1c18000 {
2013                         device_type = "pci";
2014                         compatible = "qcom,pcie-sc8280xp";
2015                         reg = <0x0 0x01c18000 0x0 0x3000>,
2016                               <0x0 0x38000000 0x0 0xf1d>,
2017                               <0x0 0x38000f20 0x0 0xa8>,
2018                               <0x0 0x38001000 0x0 0x1000>,
2019                               <0x0 0x38100000 0x0 0x100000>,
2020                               <0x0 0x01c1b000 0x0 0x1000>;
2021                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2022                         #address-cells = <3>;
2023                         #size-cells = <2>;
2024                         ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
2025                                  <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
2026                         bus-range = <0x00 0xff>;
2027
2028                         dma-coherent;
2029
2030                         linux,pci-domain = <3>;
2031                         num-lanes = <2>;
2032
2033                         interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
2034                                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
2035                                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
2036                                      <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
2037                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
2038
2039                         #interrupt-cells = <1>;
2040                         interrupt-map-mask = <0 0 0 0x7>;
2041                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
2042                                         <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
2043                                         <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
2044                                         <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
2045
2046                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2047                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2048                                  <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
2049                                  <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
2050                                  <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
2051                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2052                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2053                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2054                         clock-names = "aux",
2055                                       "cfg",
2056                                       "bus_master",
2057                                       "bus_slave",
2058                                       "slave_q2a",
2059                                       "ddrss_sf_tbu",
2060                                       "noc_aggr_4",
2061                                       "noc_aggr_south_sf";
2062
2063                         assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
2064                         assigned-clock-rates = <19200000>;
2065
2066                         interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
2067                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
2068                         interconnect-names = "pcie-mem", "cpu-pcie";
2069
2070                         resets = <&gcc GCC_PCIE_2B_BCR>;
2071                         reset-names = "pci";
2072
2073                         power-domains = <&gcc PCIE_2B_GDSC>;
2074
2075                         phys = <&pcie2b_phy>;
2076                         phy-names = "pciephy";
2077
2078                         status = "disabled";
2079                 };
2080
2081                 pcie2b_phy: phy@1c1e000 {
2082                         compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
2083                         reg = <0x0 0x01c1e000 0x0 0x2000>;
2084
2085                         clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
2086                                  <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
2087                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2088                                  <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
2089                                  <&gcc GCC_PCIE_2B_PIPE_CLK>,
2090                                  <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
2091                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
2092                                       "pipe", "pipediv2";
2093
2094                         assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
2095                         assigned-clock-rates = <100000000>;
2096
2097                         power-domains = <&gcc PCIE_2B_GDSC>;
2098
2099                         resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
2100                         reset-names = "phy";
2101
2102                         #clock-cells = <0>;
2103                         clock-output-names = "pcie_2b_pipe_clk";
2104
2105                         #phy-cells = <0>;
2106
2107                         status = "disabled";
2108                 };
2109
2110                 pcie2a: pcie@1c20000 {
2111                         device_type = "pci";
2112                         compatible = "qcom,pcie-sc8280xp";
2113                         reg = <0x0 0x01c20000 0x0 0x3000>,
2114                               <0x0 0x3c000000 0x0 0xf1d>,
2115                               <0x0 0x3c000f20 0x0 0xa8>,
2116                               <0x0 0x3c001000 0x0 0x1000>,
2117                               <0x0 0x3c100000 0x0 0x100000>,
2118                               <0x0 0x01c23000 0x0 0x1000>;
2119                         reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
2120                         #address-cells = <3>;
2121                         #size-cells = <2>;
2122                         ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
2123                                  <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
2124                         bus-range = <0x00 0xff>;
2125
2126                         dma-coherent;
2127
2128                         linux,pci-domain = <2>;
2129                         num-lanes = <4>;
2130
2131                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
2132                                      <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
2133                                      <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
2134                                      <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
2135                         interrupt-names = "msi0", "msi1", "msi2", "msi3";
2136
2137                         #interrupt-cells = <1>;
2138                         interrupt-map-mask = <0 0 0 0x7>;
2139                         interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
2140                                         <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
2141                                         <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
2142                                         <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
2143
2144                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2145                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2146                                  <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
2147                                  <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
2148                                  <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
2149                                  <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
2150                                  <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
2151                                  <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
2152                         clock-names = "aux",
2153                                       "cfg",
2154                                       "bus_master",
2155                                       "bus_slave",
2156                                       "slave_q2a",
2157                                       "ddrss_sf_tbu",
2158                                       "noc_aggr_4",
2159                                       "noc_aggr_south_sf";
2160
2161                         assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
2162                         assigned-clock-rates = <19200000>;
2163
2164                         interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
2165                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
2166                         interconnect-names = "pcie-mem", "cpu-pcie";
2167
2168                         resets = <&gcc GCC_PCIE_2A_BCR>;
2169                         reset-names = "pci";
2170
2171                         power-domains = <&gcc PCIE_2A_GDSC>;
2172
2173                         phys = <&pcie2a_phy>;
2174                         phy-names = "pciephy";
2175
2176                         status = "disabled";
2177                 };
2178
2179                 pcie2a_phy: phy@1c24000 {
2180                         compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
2181                         reg = <0x0 0x01c24000 0x0 0x2000>,
2182                               <0x0 0x01c26000 0x0 0x2000>;
2183
2184                         clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
2185                                  <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
2186                                  <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
2187                                  <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
2188                                  <&gcc GCC_PCIE_2A_PIPE_CLK>,
2189                                  <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
2190                         clock-names = "aux", "cfg_ahb", "ref", "rchng",
2191                                       "pipe", "pipediv2";
2192
2193                         assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
2194                         assigned-clock-rates = <100000000>;
2195
2196                         power-domains = <&gcc PCIE_2A_GDSC>;
2197
2198                         resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
2199                         reset-names = "phy";
2200
2201                         qcom,4ln-config-sel = <&tcsr 0xa044 0>;
2202
2203                         #clock-cells = <0>;
2204                         clock-output-names = "pcie_2a_pipe_clk";
2205
2206                         #phy-cells = <0>;
2207
2208                         status = "disabled";
2209                 };
2210
2211                 ufs_mem_hc: ufs@1d84000 {
2212                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2213                                      "jedec,ufs-2.0";
2214                         reg = <0 0x01d84000 0 0x3000>;
2215                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
2216                         phys = <&ufs_mem_phy>;
2217                         phy-names = "ufsphy";
2218                         lanes-per-direction = <2>;
2219                         #reset-cells = <1>;
2220                         resets = <&gcc GCC_UFS_PHY_BCR>;
2221                         reset-names = "rst";
2222
2223                         power-domains = <&gcc UFS_PHY_GDSC>;
2224                         required-opps = <&rpmhpd_opp_nom>;
2225
2226                         iommus = <&apps_smmu 0xe0 0x0>;
2227                         dma-coherent;
2228
2229                         clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
2230                                  <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
2231                                  <&gcc GCC_UFS_PHY_AHB_CLK>,
2232                                  <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
2233                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
2234                                  <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
2235                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
2236                                  <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
2237                         clock-names = "core_clk",
2238                                       "bus_aggr_clk",
2239                                       "iface_clk",
2240                                       "core_clk_unipro",
2241                                       "ref_clk",
2242                                       "tx_lane0_sync_clk",
2243                                       "rx_lane0_sync_clk",
2244                                       "rx_lane1_sync_clk";
2245                         freq-table-hz = <75000000 300000000>,
2246                                         <0 0>,
2247                                         <0 0>,
2248                                         <75000000 300000000>,
2249                                         <0 0>,
2250                                         <0 0>,
2251                                         <0 0>,
2252                                         <0 0>;
2253                         status = "disabled";
2254                 };
2255
2256                 ufs_mem_phy: phy@1d87000 {
2257                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
2258                         reg = <0 0x01d87000 0 0x1000>;
2259
2260                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2261                                  <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
2262                                  <&gcc GCC_UFS_CARD_CLKREF_CLK>;
2263                         clock-names = "ref",
2264                                       "ref_aux",
2265                                       "qref";
2266
2267                         power-domains = <&gcc UFS_PHY_GDSC>;
2268
2269                         resets = <&ufs_mem_hc 0>;
2270                         reset-names = "ufsphy";
2271
2272                         #phy-cells = <0>;
2273
2274                         status = "disabled";
2275                 };
2276
2277                 ufs_card_hc: ufs@1da4000 {
2278                         compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
2279                                      "jedec,ufs-2.0";
2280                         reg = <0 0x01da4000 0 0x3000>;
2281                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
2282                         phys = <&ufs_card_phy>;
2283                         phy-names = "ufsphy";
2284                         lanes-per-direction = <2>;
2285                         #reset-cells = <1>;
2286                         resets = <&gcc GCC_UFS_CARD_BCR>;
2287                         reset-names = "rst";
2288
2289                         power-domains = <&gcc UFS_CARD_GDSC>;
2290
2291                         iommus = <&apps_smmu 0x4a0 0x0>;
2292                         dma-coherent;
2293
2294                         clocks = <&gcc GCC_UFS_CARD_AXI_CLK>,
2295                                  <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
2296                                  <&gcc GCC_UFS_CARD_AHB_CLK>,
2297                                  <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>,
2298                                  <&gcc GCC_UFS_REF_CLKREF_CLK>,
2299                                  <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>,
2300                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>,
2301                                  <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>;
2302                         clock-names = "core_clk",
2303                                       "bus_aggr_clk",
2304                                       "iface_clk",
2305                                       "core_clk_unipro",
2306                                       "ref_clk",
2307                                       "tx_lane0_sync_clk",
2308                                       "rx_lane0_sync_clk",
2309                                       "rx_lane1_sync_clk";
2310                         freq-table-hz = <75000000 300000000>,
2311                                         <0 0>,
2312                                         <0 0>,
2313                                         <75000000 300000000>,
2314                                         <0 0>,
2315                                         <0 0>,
2316                                         <0 0>,
2317                                         <0 0>;
2318                         status = "disabled";
2319                 };
2320
2321                 ufs_card_phy: phy@1da7000 {
2322                         compatible = "qcom,sc8280xp-qmp-ufs-phy";
2323                         reg = <0 0x01da7000 0 0x1000>;
2324
2325                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2326                                  <&gcc GCC_UFS_CARD_PHY_AUX_CLK>,
2327                                  <&gcc GCC_UFS_1_CARD_CLKREF_CLK>;
2328                         clock-names = "ref",
2329                                       "ref_aux",
2330                                       "qref";
2331
2332                         power-domains = <&gcc UFS_CARD_GDSC>;
2333
2334                         resets = <&ufs_card_hc 0>;
2335                         reset-names = "ufsphy";
2336
2337                         #phy-cells = <0>;
2338
2339                         status = "disabled";
2340                 };
2341
2342                 tcsr_mutex: hwlock@1f40000 {
2343                         compatible = "qcom,tcsr-mutex";
2344                         reg = <0x0 0x01f40000 0x0 0x20000>;
2345                         #hwlock-cells = <1>;
2346                 };
2347
2348                 tcsr: syscon@1fc0000 {
2349                         compatible = "qcom,sc8280xp-tcsr", "syscon";
2350                         reg = <0x0 0x01fc0000 0x0 0x30000>;
2351                 };
2352
2353                 gpu: gpu@3d00000 {
2354                         compatible = "qcom,adreno-690.0", "qcom,adreno";
2355
2356                         reg = <0 0x03d00000 0 0x40000>,
2357                               <0 0x03d9e000 0 0x1000>,
2358                               <0 0x03d61000 0 0x800>;
2359                         reg-names = "kgsl_3d0_reg_memory",
2360                                     "cx_mem",
2361                                     "cx_dbgc";
2362                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2363                         iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>;
2364                         operating-points-v2 = <&gpu_opp_table>;
2365
2366                         qcom,gmu = <&gmu>;
2367                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2368                         interconnect-names = "gfx-mem";
2369                         #cooling-cells = <2>;
2370
2371                         status = "disabled";
2372
2373                         gpu_opp_table: opp-table {
2374                                 compatible = "operating-points-v2";
2375
2376                                 opp-270000000 {
2377                                         opp-hz = /bits/ 64 <270000000>;
2378                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2379                                         opp-peak-kBps = <451000>;
2380                                 };
2381
2382                                 opp-410000000 {
2383                                         opp-hz = /bits/ 64 <410000000>;
2384                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2385                                         opp-peak-kBps = <1555000>;
2386                                 };
2387
2388                                 opp-500000000 {
2389                                         opp-hz = /bits/ 64 <500000000>;
2390                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2391                                         opp-peak-kBps = <1555000>;
2392                                 };
2393
2394                                 opp-547000000 {
2395                                         opp-hz = /bits/ 64 <547000000>;
2396                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2397                                         opp-peak-kBps = <1555000>;
2398                                 };
2399
2400                                 opp-606000000 {
2401                                         opp-hz = /bits/ 64 <606000000>;
2402                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2403                                         opp-peak-kBps = <2736000>;
2404                                 };
2405
2406                                 opp-640000000 {
2407                                         opp-hz = /bits/ 64 <640000000>;
2408                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2409                                         opp-peak-kBps = <2736000>;
2410                                 };
2411
2412                                 opp-655000000 {
2413                                         opp-hz = /bits/ 64 <655000000>;
2414                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2415                                         opp-peak-kBps = <2736000>;
2416                                 };
2417
2418                                 opp-690000000 {
2419                                         opp-hz = /bits/ 64 <690000000>;
2420                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2421                                         opp-peak-kBps = <2736000>;
2422                                 };
2423                         };
2424                 };
2425
2426                 gmu: gmu@3d6a000 {
2427                         compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
2428                         reg = <0 0x03d6a000 0 0x34000>,
2429                               <0 0x03de0000 0 0x10000>,
2430                               <0 0x0b290000 0 0x10000>;
2431                         reg-names = "gmu", "rscc", "gmu_pdc";
2432                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2433                                      <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2434                         interrupt-names = "hfi", "gmu";
2435                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2436                                  <&gpucc GPU_CC_CXO_CLK>,
2437                                  <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2438                                  <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2439                                  <&gpucc GPU_CC_AHB_CLK>,
2440                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2441                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
2442                         clock-names = "gmu",
2443                                       "cxo",
2444                                       "axi",
2445                                       "memnoc",
2446                                       "ahb",
2447                                       "hub",
2448                                       "smmu_vote";
2449                         power-domains = <&gpucc GPU_CC_CX_GDSC>,
2450                                         <&gpucc GPU_CC_GX_GDSC>;
2451                         power-domain-names = "cx",
2452                                              "gx";
2453                         iommus = <&gpu_smmu 5 0xc00>;
2454                         operating-points-v2 = <&gmu_opp_table>;
2455
2456                         gmu_opp_table: opp-table {
2457                                 compatible = "operating-points-v2";
2458
2459                                 opp-200000000 {
2460                                         opp-hz = /bits/ 64 <200000000>;
2461                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2462                                 };
2463
2464                                 opp-500000000 {
2465                                         opp-hz = /bits/ 64 <500000000>;
2466                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2467                                 };
2468                         };
2469                 };
2470
2471                 gpucc: clock-controller@3d90000 {
2472                         compatible = "qcom,sc8280xp-gpucc";
2473                         reg = <0 0x03d90000 0 0x9000>;
2474                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2475                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2476                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2477                         clock-names = "bi_tcxo",
2478                                       "gcc_gpu_gpll0_clk_src",
2479                                       "gcc_gpu_gpll0_div_clk_src";
2480
2481                         power-domains = <&rpmhpd SC8280XP_GFX>;
2482                         #clock-cells = <1>;
2483                         #reset-cells = <1>;
2484                         #power-domain-cells = <1>;
2485                 };
2486
2487                 gpu_smmu: iommu@3da0000 {
2488                         compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu",
2489                                      "qcom,smmu-500", "arm,mmu-500";
2490                         reg = <0 0x03da0000 0 0x20000>;
2491                         #iommu-cells = <2>;
2492                         #global-interrupts = <2>;
2493                         interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
2494                                      <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
2495                                      <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
2496                                      <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
2497                                      <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
2498                                      <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
2499                                      <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
2500                                      <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
2501                                      <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
2502                                      <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
2503                                      <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
2504                                      <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
2505                                      <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
2506                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
2507
2508                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2509                                  <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
2510                                  <&gpucc GPU_CC_AHB_CLK>,
2511                                  <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
2512                                  <&gpucc GPU_CC_CX_GMU_CLK>,
2513                                  <&gpucc GPU_CC_HUB_CX_INT_CLK>,
2514                                  <&gpucc GPU_CC_HUB_AON_CLK>;
2515                         clock-names = "gcc_gpu_memnoc_gfx_clk",
2516                                       "gcc_gpu_snoc_dvm_gfx_clk",
2517                                       "gpu_cc_ahb_clk",
2518                                       "gpu_cc_hlos1_vote_gpu_smmu_clk",
2519                                       "gpu_cc_cx_gmu_clk",
2520                                       "gpu_cc_hub_cx_int_clk",
2521                                       "gpu_cc_hub_aon_clk";
2522
2523                         power-domains = <&gpucc GPU_CC_CX_GDSC>;
2524                         dma-coherent;
2525                 };
2526
2527                 usb_0_hsphy: phy@88e5000 {
2528                         compatible = "qcom,sc8280xp-usb-hs-phy",
2529                                      "qcom,usb-snps-hs-5nm-phy";
2530                         reg = <0 0x088e5000 0 0x400>;
2531                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2532                         clock-names = "ref";
2533                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2534
2535                         #phy-cells = <0>;
2536
2537                         status = "disabled";
2538                 };
2539
2540                 usb_2_hsphy0: phy@88e7000 {
2541                         compatible = "qcom,sc8280xp-usb-hs-phy",
2542                                      "qcom,usb-snps-hs-5nm-phy";
2543                         reg = <0 0x088e7000 0 0x400>;
2544                         clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>;
2545                         clock-names = "ref";
2546                         resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
2547
2548                         #phy-cells = <0>;
2549
2550                         status = "disabled";
2551                 };
2552
2553                 usb_2_hsphy1: phy@88e8000 {
2554                         compatible = "qcom,sc8280xp-usb-hs-phy",
2555                                      "qcom,usb-snps-hs-5nm-phy";
2556                         reg = <0 0x088e8000 0 0x400>;
2557                         clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>;
2558                         clock-names = "ref";
2559                         resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
2560
2561                         #phy-cells = <0>;
2562
2563                         status = "disabled";
2564                 };
2565
2566                 usb_2_hsphy2: phy@88e9000 {
2567                         compatible = "qcom,sc8280xp-usb-hs-phy",
2568                                      "qcom,usb-snps-hs-5nm-phy";
2569                         reg = <0 0x088e9000 0 0x400>;
2570                         clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>;
2571                         clock-names = "ref";
2572                         resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>;
2573
2574                         #phy-cells = <0>;
2575
2576                         status = "disabled";
2577                 };
2578
2579                 usb_2_hsphy3: phy@88ea000 {
2580                         compatible = "qcom,sc8280xp-usb-hs-phy",
2581                                      "qcom,usb-snps-hs-5nm-phy";
2582                         reg = <0 0x088ea000 0 0x400>;
2583                         clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>;
2584                         clock-names = "ref";
2585                         resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>;
2586
2587                         #phy-cells = <0>;
2588
2589                         status = "disabled";
2590                 };
2591
2592                 usb_2_qmpphy0: phy@88ef000 {
2593                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2594                         reg = <0 0x088ef000 0 0x2000>;
2595
2596                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2597                                  <&gcc GCC_USB3_MP0_CLKREF_CLK>,
2598                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2599                                  <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
2600                         clock-names = "aux", "ref", "com_aux", "pipe";
2601
2602                         resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
2603                                  <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
2604                         reset-names = "phy", "phy_phy";
2605
2606                         power-domains = <&gcc USB30_MP_GDSC>;
2607
2608                         #clock-cells = <0>;
2609                         clock-output-names = "usb2_phy0_pipe_clk";
2610
2611                         #phy-cells = <0>;
2612
2613                         status = "disabled";
2614                 };
2615
2616                 usb_2_qmpphy1: phy@88f1000 {
2617                         compatible = "qcom,sc8280xp-qmp-usb3-uni-phy";
2618                         reg = <0 0x088f1000 0 0x2000>;
2619
2620                         clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
2621                                  <&gcc GCC_USB3_MP1_CLKREF_CLK>,
2622                                  <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
2623                                  <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
2624                         clock-names = "aux", "ref", "com_aux", "pipe";
2625
2626                         resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
2627                                  <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
2628                         reset-names = "phy", "phy_phy";
2629
2630                         power-domains = <&gcc USB30_MP_GDSC>;
2631
2632                         #clock-cells = <0>;
2633                         clock-output-names = "usb2_phy1_pipe_clk";
2634
2635                         #phy-cells = <0>;
2636
2637                         status = "disabled";
2638                 };
2639
2640                 remoteproc_adsp: remoteproc@3000000 {
2641                         compatible = "qcom,sc8280xp-adsp-pas";
2642                         reg = <0 0x03000000 0 0x100>;
2643
2644                         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
2645                                               <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2646                                               <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
2647                                               <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
2648                                               <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>,
2649                                               <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>;
2650                         interrupt-names = "wdog", "fatal", "ready",
2651                                           "handover", "stop-ack", "shutdown-ack";
2652
2653                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2654                         clock-names = "xo";
2655
2656                         power-domains = <&rpmhpd SC8280XP_LCX>,
2657                                         <&rpmhpd SC8280XP_LMX>;
2658                         power-domain-names = "lcx", "lmx";
2659
2660                         memory-region = <&pil_adsp_mem>;
2661
2662                         qcom,qmp = <&aoss_qmp>;
2663
2664                         qcom,smem-states = <&smp2p_adsp_out 0>;
2665                         qcom,smem-state-names = "stop";
2666
2667                         status = "disabled";
2668
2669                         remoteproc_adsp_glink: glink-edge {
2670                                 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2671                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
2672                                                              IRQ_TYPE_EDGE_RISING>;
2673                                 mboxes = <&ipcc IPCC_CLIENT_LPASS
2674                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
2675
2676                                 label = "lpass";
2677                                 qcom,remote-pid = <2>;
2678
2679                                 gpr {
2680                                         compatible = "qcom,gpr";
2681                                         qcom,glink-channels = "adsp_apps";
2682                                         qcom,domain = <GPR_DOMAIN_ID_ADSP>;
2683                                         qcom,intents = <512 20>;
2684                                         #address-cells = <1>;
2685                                         #size-cells = <0>;
2686
2687                                         q6apm: service@1 {
2688                                                 compatible = "qcom,q6apm";
2689                                                 reg = <GPR_APM_MODULE_IID>;
2690                                                 #sound-dai-cells = <0>;
2691                                                 qcom,protection-domain = "avs/audio",
2692                                                                          "msm/adsp/audio_pd";
2693                                                 q6apmdai: dais {
2694                                                         compatible = "qcom,q6apm-dais";
2695                                                         iommus = <&apps_smmu 0x0c01 0x0>;
2696                                                 };
2697
2698                                                 q6apmbedai: bedais {
2699                                                         compatible = "qcom,q6apm-lpass-dais";
2700                                                         #sound-dai-cells = <1>;
2701                                                 };
2702                                         };
2703
2704                                         q6prm: service@2 {
2705                                                 compatible = "qcom,q6prm";
2706                                                 reg = <GPR_PRM_MODULE_IID>;
2707                                                 qcom,protection-domain = "avs/audio",
2708                                                                          "msm/adsp/audio_pd";
2709                                                 q6prmcc: clock-controller {
2710                                                         compatible = "qcom,q6prm-lpass-clocks";
2711                                                         #clock-cells = <2>;
2712                                                 };
2713                                         };
2714                                 };
2715                         };
2716                 };
2717
2718                 rxmacro: rxmacro@3200000 {
2719                         compatible = "qcom,sc8280xp-lpass-rx-macro";
2720                         reg = <0 0x03200000 0 0x1000>;
2721                         clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2722                                  <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2723                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2724                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2725                                  <&vamacro>;
2726                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2727                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2728                                           <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2729                         assigned-clock-rates = <19200000>, <19200000>;
2730
2731                         clock-output-names = "mclk";
2732                         #clock-cells = <0>;
2733                         #sound-dai-cells = <1>;
2734
2735                         pinctrl-names = "default";
2736                         pinctrl-0 = <&rx_swr_default>;
2737
2738                         status = "disabled";
2739                 };
2740
2741                 swr1: soundwire@3210000 {
2742                         compatible = "qcom,soundwire-v1.6.0";
2743                         reg = <0 0x03210000 0 0x2000>;
2744                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
2745                         clocks = <&rxmacro>;
2746                         clock-names = "iface";
2747                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
2748                         reset-names = "swr_audio_cgcr";
2749                         label = "RX";
2750
2751                         qcom,din-ports = <0>;
2752                         qcom,dout-ports = <5>;
2753
2754                         qcom,ports-sinterval-low =      /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2755                         qcom,ports-offset1 =            /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
2756                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
2757                         qcom,ports-hstart =             /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
2758                         qcom,ports-hstop =              /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
2759                         qcom,ports-word-length =        /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2760                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
2761                         qcom,ports-lane-control =       /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2762                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
2763
2764                         #sound-dai-cells = <1>;
2765                         #address-cells = <2>;
2766                         #size-cells = <0>;
2767
2768                         status = "disabled";
2769                 };
2770
2771                 txmacro: txmacro@3220000 {
2772                         compatible = "qcom,sc8280xp-lpass-tx-macro";
2773                         reg = <0 0x03220000 0 0x1000>;
2774                         pinctrl-names = "default";
2775                         pinctrl-0 = <&tx_swr_default>;
2776                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2777                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2778                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2779                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2780                                  <&vamacro>;
2781
2782                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2783                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2784                                           <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2785                         assigned-clock-rates = <19200000>, <19200000>;
2786                         clock-output-names = "mclk";
2787
2788                         #clock-cells = <0>;
2789                         #sound-dai-cells = <1>;
2790
2791                         status = "disabled";
2792                 };
2793
2794                 wsamacro: codec@3240000 {
2795                         compatible = "qcom,sc8280xp-lpass-wsa-macro";
2796                         reg = <0 0x03240000 0 0x1000>;
2797                         clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2798                                  <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2799                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2800                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2801                                  <&vamacro>;
2802                         clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2803                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2804                                           <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2805                         assigned-clock-rates = <19200000>, <19200000>;
2806
2807                         #clock-cells = <0>;
2808                         clock-output-names = "mclk";
2809                         #sound-dai-cells = <1>;
2810
2811                         pinctrl-names = "default";
2812                         pinctrl-0 = <&wsa_swr_default>;
2813
2814                         status = "disabled";
2815                 };
2816
2817                 swr0: soundwire@3250000 {
2818                         reg = <0 0x03250000 0 0x2000>;
2819                         compatible = "qcom,soundwire-v1.6.0";
2820                         interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2821                         clocks = <&wsamacro>;
2822                         clock-names = "iface";
2823                         resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
2824                         reset-names = "swr_audio_cgcr";
2825                         label = "WSA";
2826
2827                         qcom,din-ports = <2>;
2828                         qcom,dout-ports = <6>;
2829
2830                         qcom,ports-sinterval-low =      /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2831                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2832                         qcom,ports-offset2 =            /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2833                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2834                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2835                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2836                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2837                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2838                         qcom,ports-lane-control =       /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2839
2840                         #sound-dai-cells = <1>;
2841                         #address-cells = <2>;
2842                         #size-cells = <0>;
2843
2844                         status = "disabled";
2845                 };
2846
2847                 lpass_audiocc: clock-controller@32a9000 {
2848                         compatible = "qcom,sc8280xp-lpassaudiocc";
2849                         reg = <0 0x032a9000 0 0x1000>;
2850                         #clock-cells = <1>;
2851                         #reset-cells = <1>;
2852                 };
2853
2854                 swr2: soundwire@3330000 {
2855                         compatible = "qcom,soundwire-v1.6.0";
2856                         reg = <0 0x03330000 0 0x2000>;
2857                         interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
2858                                      <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
2859                         interrupt-names = "core", "wakeup";
2860
2861                         clocks = <&txmacro>;
2862                         clock-names = "iface";
2863                         resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
2864                         reset-names = "swr_audio_cgcr";
2865                         label = "TX";
2866                         #sound-dai-cells = <1>;
2867                         #address-cells = <2>;
2868                         #size-cells = <0>;
2869
2870                         qcom,din-ports = <4>;
2871                         qcom,dout-ports = <0>;
2872                         qcom,ports-sinterval-low =      /bits/ 8 <0x01 0x01 0x03 0x03>;
2873                         qcom,ports-offset1 =            /bits/ 8 <0x01 0x00 0x02 0x00>;
2874                         qcom,ports-offset2 =            /bits/ 8 <0x00 0x00 0x00 0x00>;
2875                         qcom,ports-block-pack-mode =    /bits/ 8 <0xff 0xff 0xff 0xff>;
2876                         qcom,ports-hstart =             /bits/ 8 <0xff 0xff 0xff 0xff>;
2877                         qcom,ports-hstop =              /bits/ 8 <0xff 0xff 0xff 0xff>;
2878                         qcom,ports-word-length =        /bits/ 8 <0xff 0xff 0xff 0xff>;
2879                         qcom,ports-block-group-count =  /bits/ 8 <0xff 0xff 0xff 0xff>;
2880                         qcom,ports-lane-control =       /bits/ 8 <0x00 0x01 0x00 0x01>;
2881
2882                         status = "disabled";
2883                 };
2884
2885                 vamacro: codec@3370000 {
2886                         compatible = "qcom,sc8280xp-lpass-va-macro";
2887                         reg = <0 0x03370000 0 0x1000>;
2888                         clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2889                                  <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2890                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2891                                  <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2892                         clock-names = "mclk", "macro", "dcodec", "npl";
2893                         assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2894                         assigned-clock-rates = <19200000>;
2895
2896                         #clock-cells = <0>;
2897                         clock-output-names = "fsgen";
2898                         #sound-dai-cells = <1>;
2899
2900                         status = "disabled";
2901                 };
2902
2903                 lpass_tlmm: pinctrl@33c0000 {
2904                         compatible = "qcom,sc8280xp-lpass-lpi-pinctrl";
2905                         reg = <0 0x33c0000 0x0 0x20000>,
2906                               <0 0x3550000 0x0 0x10000>;
2907                         gpio-controller;
2908                         #gpio-cells = <2>;
2909                         gpio-ranges = <&lpass_tlmm 0 0 19>;
2910
2911                         clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2912                                  <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2913                         clock-names = "core", "audio";
2914
2915                         status = "disabled";
2916
2917                         tx_swr_default: tx-swr-default-state {
2918                                 clk-pins {
2919                                         pins = "gpio0";
2920                                         function = "swr_tx_clk";
2921                                         drive-strength = <2>;
2922                                         slew-rate = <1>;
2923                                         bias-disable;
2924                                 };
2925
2926                                 data-pins {
2927                                         pins = "gpio1", "gpio2";
2928                                         function = "swr_tx_data";
2929                                         drive-strength = <2>;
2930                                         slew-rate = <1>;
2931                                         bias-bus-hold;
2932                                 };
2933                         };
2934
2935                         rx_swr_default: rx-swr-default-state {
2936                                 clk-pins {
2937                                         pins = "gpio3";
2938                                         function = "swr_rx_clk";
2939                                         drive-strength = <2>;
2940                                         slew-rate = <1>;
2941                                         bias-disable;
2942                                 };
2943
2944                                 data-pins {
2945                                         pins = "gpio4", "gpio5";
2946                                         function = "swr_rx_data";
2947                                         drive-strength = <2>;
2948                                         slew-rate = <1>;
2949                                         bias-bus-hold;
2950                                 };
2951                         };
2952
2953                         dmic01_default: dmic01-default-state {
2954                                 clk-pins {
2955                                         pins = "gpio6";
2956                                         function = "dmic1_clk";
2957                                         drive-strength = <8>;
2958                                         output-high;
2959                                 };
2960
2961                                 data-pins {
2962                                         pins = "gpio7";
2963                                         function = "dmic1_data";
2964                                         drive-strength = <8>;
2965                                         input-enable;
2966                                 };
2967                         };
2968
2969                         dmic01_sleep: dmic01-sleep-state {
2970                                 clk-pins {
2971                                         pins = "gpio6";
2972                                         function = "dmic1_clk";
2973                                         drive-strength = <2>;
2974                                         bias-disable;
2975                                         output-low;
2976                                 };
2977
2978                                 data-pins {
2979                                         pins = "gpio7";
2980                                         function = "dmic1_data";
2981                                         drive-strength = <2>;
2982                                         bias-pull-down;
2983                                         input-enable;
2984                                 };
2985                         };
2986
2987                         dmic23_default: dmic23-default-state {
2988                                 clk-pins {
2989                                         pins = "gpio8";
2990                                         function = "dmic2_clk";
2991                                         drive-strength = <8>;
2992                                         output-high;
2993                                 };
2994
2995                                 data-pins {
2996                                         pins = "gpio9";
2997                                         function = "dmic2_data";
2998                                         drive-strength = <8>;
2999                                         input-enable;
3000                                 };
3001                         };
3002
3003                         dmic23_sleep: dmic23-sleep-state {
3004                                 clk-pins {
3005                                         pins = "gpio8";
3006                                         function = "dmic2_clk";
3007                                         drive-strength = <2>;
3008                                         bias-disable;
3009                                         output-low;
3010                                 };
3011
3012                                 data-pins {
3013                                         pins = "gpio9";
3014                                         function = "dmic2_data";
3015                                         drive-strength = <2>;
3016                                         bias-pull-down;
3017                                         input-enable;
3018                                 };
3019                         };
3020
3021                         wsa_swr_default: wsa-swr-default-state {
3022                                 clk-pins {
3023                                         pins = "gpio10";
3024                                         function = "wsa_swr_clk";
3025                                         drive-strength = <2>;
3026                                         slew-rate = <1>;
3027                                         bias-disable;
3028                                 };
3029
3030                                 data-pins {
3031                                         pins = "gpio11";
3032                                         function = "wsa_swr_data";
3033                                         drive-strength = <2>;
3034                                         slew-rate = <1>;
3035                                         bias-bus-hold;
3036                                 };
3037                         };
3038
3039                         wsa2_swr_default: wsa2-swr-default-state {
3040                                 clk-pins {
3041                                         pins = "gpio15";
3042                                         function = "wsa2_swr_clk";
3043                                         drive-strength = <2>;
3044                                         slew-rate = <1>;
3045                                         bias-disable;
3046                                 };
3047
3048                                 data-pins {
3049                                         pins = "gpio16";
3050                                         function = "wsa2_swr_data";
3051                                         drive-strength = <2>;
3052                                         slew-rate = <1>;
3053                                         bias-bus-hold;
3054                                 };
3055                         };
3056                 };
3057
3058                 lpasscc: clock-controller@33e0000 {
3059                         compatible = "qcom,sc8280xp-lpasscc";
3060                         reg = <0 0x033e0000 0 0x12000>;
3061                         #clock-cells = <1>;
3062                         #reset-cells = <1>;
3063                 };
3064
3065                 sdc2: mmc@8804000 {
3066                         compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5";
3067                         reg = <0 0x08804000 0 0x1000>;
3068
3069                         interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
3070                                      <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
3071                         interrupt-names = "hc_irq", "pwr_irq";
3072
3073                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
3074                                  <&gcc GCC_SDCC2_APPS_CLK>,
3075                                  <&rpmhcc RPMH_CXO_CLK>;
3076                         clock-names = "iface", "core", "xo";
3077                         resets = <&gcc GCC_SDCC2_BCR>;
3078                         interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3079                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
3080                         interconnect-names = "sdhc-ddr","cpu-sdhc";
3081                         iommus = <&apps_smmu 0x4e0 0x0>;
3082                         power-domains = <&rpmhpd SC8280XP_CX>;
3083                         operating-points-v2 = <&sdc2_opp_table>;
3084                         bus-width = <4>;
3085                         dma-coherent;
3086
3087                         status = "disabled";
3088
3089                         sdc2_opp_table: opp-table {
3090                                 compatible = "operating-points-v2";
3091
3092                                 opp-100000000 {
3093                                         opp-hz = /bits/ 64 <100000000>;
3094                                         required-opps = <&rpmhpd_opp_low_svs>;
3095                                         opp-peak-kBps = <1800000 400000>;
3096                                         opp-avg-kBps = <100000 0>;
3097                                 };
3098
3099                                 opp-202000000 {
3100                                         opp-hz = /bits/ 64 <202000000>;
3101                                         required-opps = <&rpmhpd_opp_svs_l1>;
3102                                         opp-peak-kBps = <5400000 1600000>;
3103                                         opp-avg-kBps = <200000 0>;
3104                                 };
3105                         };
3106                 };
3107
3108                 usb_0_qmpphy: phy@88eb000 {
3109                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3110                         reg = <0 0x088eb000 0 0x4000>;
3111
3112                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
3113                                  <&gcc GCC_USB4_EUD_CLKREF_CLK>,
3114                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
3115                                  <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
3116                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3117
3118                         power-domains = <&gcc USB30_PRIM_GDSC>;
3119
3120                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
3121                                  <&gcc GCC_USB4_DP_PHY_PRIM_BCR>;
3122                         reset-names = "phy", "common";
3123
3124                         #clock-cells = <1>;
3125                         #phy-cells = <1>;
3126
3127                         status = "disabled";
3128
3129                         ports {
3130                                 #address-cells = <1>;
3131                                 #size-cells = <0>;
3132
3133                                 port@0 {
3134                                         reg = <0>;
3135
3136                                         usb_0_qmpphy_out: endpoint {};
3137                                 };
3138
3139                                 port@2 {
3140                                         reg = <2>;
3141
3142                                         usb_0_qmpphy_dp_in: endpoint {};
3143                                 };
3144                         };
3145                 };
3146
3147                 usb_1_hsphy: phy@8902000 {
3148                         compatible = "qcom,sc8280xp-usb-hs-phy",
3149                                      "qcom,usb-snps-hs-5nm-phy";
3150                         reg = <0 0x08902000 0 0x400>;
3151                         #phy-cells = <0>;
3152
3153                         clocks = <&rpmhcc RPMH_CXO_CLK>;
3154                         clock-names = "ref";
3155
3156                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
3157
3158                         status = "disabled";
3159                 };
3160
3161                 usb_1_qmpphy: phy@8903000 {
3162                         compatible = "qcom,sc8280xp-qmp-usb43dp-phy";
3163                         reg = <0 0x08903000 0 0x4000>;
3164
3165                         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
3166                                  <&gcc GCC_USB4_CLKREF_CLK>,
3167                                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
3168                                  <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
3169                         clock-names = "aux", "ref", "com_aux", "usb3_pipe";
3170
3171                         power-domains = <&gcc USB30_SEC_GDSC>;
3172
3173                         resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
3174                                  <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>;
3175                         reset-names = "phy", "common";
3176
3177                         #clock-cells = <1>;
3178                         #phy-cells = <1>;
3179
3180                         status = "disabled";
3181
3182                         ports {
3183                                 #address-cells = <1>;
3184                                 #size-cells = <0>;
3185
3186                                 port@0 {
3187                                         reg = <0>;
3188
3189                                         usb_1_qmpphy_out: endpoint {};
3190                                 };
3191
3192                                 port@2 {
3193                                         reg = <2>;
3194
3195                                         usb_1_qmpphy_dp_in: endpoint {};
3196                                 };
3197                         };
3198                 };
3199
3200                 mdss1_dp0_phy: phy@8909a00 {
3201                         compatible = "qcom,sc8280xp-dp-phy";
3202                         reg = <0 0x08909a00 0 0x19c>,
3203                               <0 0x08909200 0 0xec>,
3204                               <0 0x08909600 0 0xec>,
3205                               <0 0x08909000 0 0x1c8>;
3206
3207                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3208                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3209                         clock-names = "aux", "cfg_ahb";
3210                         power-domains = <&rpmhpd SC8280XP_MX>;
3211
3212                         #clock-cells = <1>;
3213                         #phy-cells = <0>;
3214
3215                         status = "disabled";
3216                 };
3217
3218                 mdss1_dp1_phy: phy@890ca00 {
3219                         compatible = "qcom,sc8280xp-dp-phy";
3220                         reg = <0 0x0890ca00 0 0x19c>,
3221                               <0 0x0890c200 0 0xec>,
3222                               <0 0x0890c600 0 0xec>,
3223                               <0 0x0890c000 0 0x1c8>;
3224
3225                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
3226                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
3227                         clock-names = "aux", "cfg_ahb";
3228                         power-domains = <&rpmhpd SC8280XP_MX>;
3229
3230                         #clock-cells = <1>;
3231                         #phy-cells = <0>;
3232
3233                         status = "disabled";
3234                 };
3235
3236                 pmu@9091000 {
3237                         compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
3238                         reg = <0 0x09091000 0 0x1000>;
3239
3240                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3241
3242                         interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
3243
3244                         operating-points-v2 = <&llcc_bwmon_opp_table>;
3245
3246                         llcc_bwmon_opp_table: opp-table {
3247                                 compatible = "operating-points-v2";
3248
3249                                 opp-0 {
3250                                         opp-peak-kBps = <762000>;
3251                                 };
3252                                 opp-1 {
3253                                         opp-peak-kBps = <1720000>;
3254                                 };
3255                                 opp-2 {
3256                                         opp-peak-kBps = <2086000>;
3257                                 };
3258                                 opp-3 {
3259                                         opp-peak-kBps = <2597000>;
3260                                 };
3261                                 opp-4 {
3262                                         opp-peak-kBps = <2929000>;
3263                                 };
3264                                 opp-5 {
3265                                         opp-peak-kBps = <3879000>;
3266                                 };
3267                                 opp-6 {
3268                                         opp-peak-kBps = <5161000>;
3269                                 };
3270                                 opp-7 {
3271                                         opp-peak-kBps = <5931000>;
3272                                 };
3273                                 opp-8 {
3274                                         opp-peak-kBps = <6515000>;
3275                                 };
3276                                 opp-9 {
3277                                         opp-peak-kBps = <7980000>;
3278                                 };
3279                                 opp-10 {
3280                                         opp-peak-kBps = <8136000>;
3281                                 };
3282                                 opp-11 {
3283                                         opp-peak-kBps = <10437000>;
3284                                 };
3285                                 opp-12 {
3286                                         opp-peak-kBps = <12191000>;
3287                                 };
3288                         };
3289                 };
3290
3291                 pmu@90b6400 {
3292                         compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
3293                         reg = <0 0x090b6400 0 0x600>;
3294
3295                         interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
3296
3297                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>;
3298                         operating-points-v2 = <&cpu_bwmon_opp_table>;
3299
3300                         cpu_bwmon_opp_table: opp-table {
3301                                 compatible = "operating-points-v2";
3302
3303                                 opp-0 {
3304                                         opp-peak-kBps = <2288000>;
3305                                 };
3306                                 opp-1 {
3307                                         opp-peak-kBps = <4577000>;
3308                                 };
3309                                 opp-2 {
3310                                         opp-peak-kBps = <7110000>;
3311                                 };
3312                                 opp-3 {
3313                                         opp-peak-kBps = <9155000>;
3314                                 };
3315                                 opp-4 {
3316                                         opp-peak-kBps = <12298000>;
3317                                 };
3318                                 opp-5 {
3319                                         opp-peak-kBps = <14236000>;
3320                                 };
3321                                 opp-6 {
3322                                         opp-peak-kBps = <15258001>;
3323                                 };
3324                         };
3325                 };
3326
3327                 system-cache-controller@9200000 {
3328                         compatible = "qcom,sc8280xp-llcc";
3329                         reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3330                               <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
3331                               <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
3332                               <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
3333                               <0 0x09600000 0 0x58000>;
3334                         reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
3335                                     "llcc3_base", "llcc4_base", "llcc5_base",
3336                                     "llcc6_base", "llcc7_base",  "llcc_broadcast_base";
3337                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
3338                 };
3339
3340                 usb_0: usb@a6f8800 {
3341                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3342                         reg = <0 0x0a6f8800 0 0x400>;
3343                         #address-cells = <2>;
3344                         #size-cells = <2>;
3345                         ranges;
3346
3347                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
3348                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
3349                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
3350                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
3351                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3352                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3353                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3354                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3355                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3356                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3357                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3358
3359                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3360                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
3361                         assigned-clock-rates = <19200000>, <200000000>;
3362
3363                         interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>,
3364                                               <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
3365                                               <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
3366                                               <&pdc 138 IRQ_TYPE_LEVEL_HIGH>;
3367                         interrupt-names = "pwr_event",
3368                                           "dp_hs_phy_irq",
3369                                           "dm_hs_phy_irq",
3370                                           "ss_phy_irq";
3371
3372                         power-domains = <&gcc USB30_PRIM_GDSC>;
3373                         required-opps = <&rpmhpd_opp_nom>;
3374
3375                         resets = <&gcc GCC_USB30_PRIM_BCR>;
3376
3377                         interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3378                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
3379                         interconnect-names = "usb-ddr", "apps-usb";
3380
3381                         wakeup-source;
3382
3383                         status = "disabled";
3384
3385                         usb_0_dwc3: usb@a600000 {
3386                                 compatible = "snps,dwc3";
3387                                 reg = <0 0x0a600000 0 0xcd00>;
3388                                 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
3389                                 iommus = <&apps_smmu 0x820 0x0>;
3390                                 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
3391                                 phy-names = "usb2-phy", "usb3-phy";
3392
3393                                 port {
3394                                         usb_0_role_switch: endpoint {
3395                                         };
3396                                 };
3397                         };
3398                 };
3399
3400                 usb_1: usb@a8f8800 {
3401                         compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3";
3402                         reg = <0 0x0a8f8800 0 0x400>;
3403                         #address-cells = <2>;
3404                         #size-cells = <2>;
3405                         ranges;
3406
3407                         clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
3408                                  <&gcc GCC_USB30_SEC_MASTER_CLK>,
3409                                  <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
3410                                  <&gcc GCC_USB30_SEC_SLEEP_CLK>,
3411                                  <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3412                                  <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
3413                                  <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>,
3414                                  <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>,
3415                                  <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
3416                         clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi",
3417                                       "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys";
3418
3419                         assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3420                                           <&gcc GCC_USB30_SEC_MASTER_CLK>;
3421                         assigned-clock-rates = <19200000>, <200000000>;
3422
3423                         interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>,
3424                                               <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
3425                                               <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
3426                                               <&pdc 136 IRQ_TYPE_LEVEL_HIGH>;
3427                         interrupt-names = "pwr_event",
3428                                           "dp_hs_phy_irq",
3429                                           "dm_hs_phy_irq",
3430                                           "ss_phy_irq";
3431
3432                         power-domains = <&gcc USB30_SEC_GDSC>;
3433                         required-opps = <&rpmhpd_opp_nom>;
3434
3435                         resets = <&gcc GCC_USB30_SEC_BCR>;
3436
3437                         interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>,
3438                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>;
3439                         interconnect-names = "usb-ddr", "apps-usb";
3440
3441                         wakeup-source;
3442
3443                         status = "disabled";
3444
3445                         usb_1_dwc3: usb@a800000 {
3446                                 compatible = "snps,dwc3";
3447                                 reg = <0 0x0a800000 0 0xcd00>;
3448                                 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
3449                                 iommus = <&apps_smmu 0x860 0x0>;
3450                                 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
3451                                 phy-names = "usb2-phy", "usb3-phy";
3452
3453                                 port {
3454                                         usb_1_role_switch: endpoint {
3455                                         };
3456                                 };
3457                         };
3458                 };
3459
3460                 cci0: cci@ac4a000 {
3461                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3462                         reg = <0 0x0ac4a000 0 0x1000>;
3463
3464                         interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
3465
3466                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3467                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3468                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3469                                  <&camcc CAMCC_CCI_0_CLK>;
3470                         clock-names = "camnoc_axi",
3471                                       "slow_ahb_src",
3472                                       "cpas_ahb",
3473                                       "cci";
3474
3475                         power-domains = <&camcc TITAN_TOP_GDSC>;
3476
3477                         pinctrl-0 = <&cci0_default>;
3478                         pinctrl-1 = <&cci0_sleep>;
3479                         pinctrl-names = "default", "sleep";
3480
3481                         #address-cells = <1>;
3482                         #size-cells = <0>;
3483
3484                         status = "disabled";
3485
3486                         cci0_i2c0: i2c-bus@0 {
3487                                 reg = <0>;
3488                                 clock-frequency = <1000000>;
3489                                 #address-cells = <1>;
3490                                 #size-cells = <0>;
3491                         };
3492
3493                         cci0_i2c1: i2c-bus@1 {
3494                                 reg = <1>;
3495                                 clock-frequency = <1000000>;
3496                                 #address-cells = <1>;
3497                                 #size-cells = <0>;
3498                         };
3499                 };
3500
3501                 cci1: cci@ac4b000 {
3502                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3503                         reg = <0 0x0ac4b000 0 0x1000>;
3504
3505                         interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
3506
3507                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3508                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3509                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3510                                  <&camcc CAMCC_CCI_1_CLK>;
3511                         clock-names = "camnoc_axi",
3512                                       "slow_ahb_src",
3513                                       "cpas_ahb",
3514                                       "cci";
3515
3516                         power-domains = <&camcc TITAN_TOP_GDSC>;
3517
3518                         pinctrl-0 = <&cci1_default>;
3519                         pinctrl-1 = <&cci1_sleep>;
3520                         pinctrl-names = "default", "sleep";
3521
3522                         #address-cells = <1>;
3523                         #size-cells = <0>;
3524
3525                         status = "disabled";
3526
3527                         cci1_i2c0: i2c-bus@0 {
3528                                 reg = <0>;
3529                                 clock-frequency = <1000000>;
3530                                 #address-cells = <1>;
3531                                 #size-cells = <0>;
3532                         };
3533
3534                         cci1_i2c1: i2c-bus@1 {
3535                                 reg = <1>;
3536                                 clock-frequency = <1000000>;
3537                                 #address-cells = <1>;
3538                                 #size-cells = <0>;
3539                         };
3540                 };
3541
3542                 cci2: cci@ac4c000 {
3543                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3544                         reg = <0 0x0ac4c000 0 0x1000>;
3545
3546                         interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
3547
3548                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3549                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3550                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3551                                  <&camcc CAMCC_CCI_2_CLK>;
3552                         clock-names = "camnoc_axi",
3553                                       "slow_ahb_src",
3554                                       "cpas_ahb",
3555                                       "cci";
3556                         power-domains = <&camcc TITAN_TOP_GDSC>;
3557
3558                         pinctrl-0 = <&cci2_default>;
3559                         pinctrl-1 = <&cci2_sleep>;
3560                         pinctrl-names = "default", "sleep";
3561
3562                         #address-cells = <1>;
3563                         #size-cells = <0>;
3564
3565                         status = "disabled";
3566
3567                         cci2_i2c0: i2c-bus@0 {
3568                                 reg = <0>;
3569                                 clock-frequency = <1000000>;
3570                                 #address-cells = <1>;
3571                                 #size-cells = <0>;
3572                         };
3573
3574                         cci2_i2c1: i2c-bus@1 {
3575                                 reg = <1>;
3576                                 clock-frequency = <1000000>;
3577                                 #address-cells = <1>;
3578                                 #size-cells = <0>;
3579                         };
3580                 };
3581
3582                 cci3: cci@ac4d000 {
3583                         compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci";
3584                         reg = <0 0x0ac4d000 0 0x1000>;
3585
3586                         interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>;
3587
3588                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3589                                  <&camcc CAMCC_SLOW_AHB_CLK_SRC>,
3590                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3591                                  <&camcc CAMCC_CCI_3_CLK>;
3592                         clock-names = "camnoc_axi",
3593                                       "slow_ahb_src",
3594                                       "cpas_ahb",
3595                                       "cci";
3596
3597                         power-domains = <&camcc TITAN_TOP_GDSC>;
3598
3599                         pinctrl-0 = <&cci3_default>;
3600                         pinctrl-1 = <&cci3_sleep>;
3601                         pinctrl-names = "default", "sleep";
3602
3603                         #address-cells = <1>;
3604                         #size-cells = <0>;
3605
3606                         status = "disabled";
3607
3608                         cci3_i2c0: i2c-bus@0 {
3609                                 reg = <0>;
3610                                 clock-frequency = <1000000>;
3611                                 #address-cells = <1>;
3612                                 #size-cells = <0>;
3613                         };
3614
3615                         cci3_i2c1: i2c-bus@1 {
3616                                 reg = <1>;
3617                                 clock-frequency = <1000000>;
3618                                 #address-cells = <1>;
3619                                 #size-cells = <0>;
3620                         };
3621                 };
3622
3623                 camss: camss@ac5a000 {
3624                         compatible = "qcom,sc8280xp-camss";
3625
3626                         reg = <0 0x0ac5a000 0 0x2000>,
3627                               <0 0x0ac5c000 0 0x2000>,
3628                               <0 0x0ac65000 0 0x2000>,
3629                               <0 0x0ac67000 0 0x2000>,
3630                               <0 0x0acaf000 0 0x4000>,
3631                               <0 0x0acb3000 0 0x1000>,
3632                               <0 0x0acb6000 0 0x4000>,
3633                               <0 0x0acba000 0 0x1000>,
3634                               <0 0x0acbd000 0 0x4000>,
3635                               <0 0x0acc1000 0 0x1000>,
3636                               <0 0x0acc4000 0 0x4000>,
3637                               <0 0x0acc8000 0 0x1000>,
3638                               <0 0x0accb000 0 0x4000>,
3639                               <0 0x0accf000 0 0x1000>,
3640                               <0 0x0acd2000 0 0x4000>,
3641                               <0 0x0acd6000 0 0x1000>,
3642                               <0 0x0acd9000 0 0x4000>,
3643                               <0 0x0acdd000 0 0x1000>,
3644                               <0 0x0ace0000 0 0x4000>,
3645                               <0 0x0ace4000 0 0x1000>;
3646                         reg-names = "csiphy2",
3647                                     "csiphy3",
3648                                     "csiphy0",
3649                                     "csiphy1",
3650                                     "vfe0",
3651                                     "csid0",
3652                                     "vfe1",
3653                                     "csid1",
3654                                     "vfe2",
3655                                     "csid2",
3656                                     "vfe_lite0",
3657                                     "csid0_lite",
3658                                     "vfe_lite1",
3659                                     "csid1_lite",
3660                                     "vfe_lite2",
3661                                     "csid2_lite",
3662                                     "vfe_lite3",
3663                                     "csid3_lite",
3664                                     "vfe3",
3665                                     "csid3";
3666
3667                         interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3668                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
3669                                      <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
3670                                      <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
3671                                      <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
3672                                      <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
3673                                      <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
3674                                      <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
3675                                      <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
3676                                      <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
3677                                      <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
3678                                      <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
3679                                      <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
3680                                      <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
3681                                      <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
3682                                      <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
3683                                      <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
3684                                      <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
3685                                      <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
3686                                      <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
3687                         interrupt-names = "csid1_lite",
3688                                           "vfe_lite1",
3689                                           "csiphy3",
3690                                           "csid0",
3691                                           "vfe0",
3692                                           "csid1",
3693                                           "vfe1",
3694                                           "csid0_lite",
3695                                           "vfe_lite0",
3696                                           "csiphy0",
3697                                           "csiphy1",
3698                                           "csiphy2",
3699                                           "csid2",
3700                                           "vfe2",
3701                                           "csid3_lite",
3702                                           "csid2_lite",
3703                                           "vfe_lite3",
3704                                           "vfe_lite2",
3705                                           "csid3",
3706                                           "vfe3";
3707
3708                         power-domains = <&camcc IFE_0_GDSC>,
3709                                         <&camcc IFE_1_GDSC>,
3710                                         <&camcc IFE_2_GDSC>,
3711                                         <&camcc IFE_3_GDSC>,
3712                                         <&camcc TITAN_TOP_GDSC>;
3713                         power-domain-names = "ife0",
3714                                              "ife1",
3715                                              "ife2",
3716                                              "ife3",
3717                                              "top";
3718
3719                         clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>,
3720                                  <&camcc CAMCC_CPAS_AHB_CLK>,
3721                                  <&camcc CAMCC_CSIPHY0_CLK>,
3722                                  <&camcc CAMCC_CSI0PHYTIMER_CLK>,
3723                                  <&camcc CAMCC_CSIPHY1_CLK>,
3724                                  <&camcc CAMCC_CSI1PHYTIMER_CLK>,
3725                                  <&camcc CAMCC_CSIPHY2_CLK>,
3726                                  <&camcc CAMCC_CSI2PHYTIMER_CLK>,
3727                                  <&camcc CAMCC_CSIPHY3_CLK>,
3728                                  <&camcc CAMCC_CSI3PHYTIMER_CLK>,
3729                                  <&camcc CAMCC_IFE_0_AXI_CLK>,
3730                                  <&camcc CAMCC_IFE_0_CLK>,
3731                                  <&camcc CAMCC_IFE_0_CPHY_RX_CLK>,
3732                                  <&camcc CAMCC_IFE_0_CSID_CLK>,
3733                                  <&camcc CAMCC_IFE_1_AXI_CLK>,
3734                                  <&camcc CAMCC_IFE_1_CLK>,
3735                                  <&camcc CAMCC_IFE_1_CPHY_RX_CLK>,
3736                                  <&camcc CAMCC_IFE_1_CSID_CLK>,
3737                                  <&camcc CAMCC_IFE_2_AXI_CLK>,
3738                                  <&camcc CAMCC_IFE_2_CLK>,
3739                                  <&camcc CAMCC_IFE_2_CPHY_RX_CLK>,
3740                                  <&camcc CAMCC_IFE_2_CSID_CLK>,
3741                                  <&camcc CAMCC_IFE_3_AXI_CLK>,
3742                                  <&camcc CAMCC_IFE_3_CLK>,
3743                                  <&camcc CAMCC_IFE_3_CPHY_RX_CLK>,
3744                                  <&camcc CAMCC_IFE_3_CSID_CLK>,
3745                                  <&camcc CAMCC_IFE_LITE_0_CLK>,
3746                                  <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>,
3747                                  <&camcc CAMCC_IFE_LITE_0_CSID_CLK>,
3748                                  <&camcc CAMCC_IFE_LITE_1_CLK>,
3749                                  <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>,
3750                                  <&camcc CAMCC_IFE_LITE_1_CSID_CLK>,
3751                                  <&camcc CAMCC_IFE_LITE_2_CLK>,
3752                                  <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>,
3753                                  <&camcc CAMCC_IFE_LITE_2_CSID_CLK>,
3754                                  <&camcc CAMCC_IFE_LITE_3_CLK>,
3755                                  <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>,
3756                                  <&camcc CAMCC_IFE_LITE_3_CSID_CLK>,
3757                                  <&gcc GCC_CAMERA_HF_AXI_CLK>,
3758                                  <&gcc GCC_CAMERA_SF_AXI_CLK>;
3759                         clock-names = "camnoc_axi",
3760                                       "cpas_ahb",
3761                                       "csiphy0",
3762                                       "csiphy0_timer",
3763                                       "csiphy1",
3764                                       "csiphy1_timer",
3765                                       "csiphy2",
3766                                       "csiphy2_timer",
3767                                       "csiphy3",
3768                                       "csiphy3_timer",
3769                                       "vfe0_axi",
3770                                       "vfe0",
3771                                       "vfe0_cphy_rx",
3772                                       "vfe0_csid",
3773                                       "vfe1_axi",
3774                                       "vfe1",
3775                                       "vfe1_cphy_rx",
3776                                       "vfe1_csid",
3777                                       "vfe2_axi",
3778                                       "vfe2",
3779                                       "vfe2_cphy_rx",
3780                                       "vfe2_csid",
3781                                       "vfe3_axi",
3782                                       "vfe3",
3783                                       "vfe3_cphy_rx",
3784                                       "vfe3_csid",
3785                                       "vfe_lite0",
3786                                       "vfe_lite0_cphy_rx",
3787                                       "vfe_lite0_csid",
3788                                       "vfe_lite1",
3789                                       "vfe_lite1_cphy_rx",
3790                                       "vfe_lite1_csid",
3791                                       "vfe_lite2",
3792                                       "vfe_lite2_cphy_rx",
3793                                       "vfe_lite2_csid",
3794                                       "vfe_lite3",
3795                                       "vfe_lite3_cphy_rx",
3796                                       "vfe_lite3_csid",
3797                                       "gcc_axi_hf",
3798                                       "gcc_axi_sf";
3799
3800                         iommus = <&apps_smmu 0x2000 0x4e0>,
3801                                  <&apps_smmu 0x2020 0x4e0>,
3802                                  <&apps_smmu 0x2040 0x4e0>,
3803                                  <&apps_smmu 0x2060 0x4e0>,
3804                                  <&apps_smmu 0x2080 0x4e0>,
3805                                  <&apps_smmu 0x20e0 0x4e0>,
3806                                  <&apps_smmu 0x20c0 0x4e0>,
3807                                  <&apps_smmu 0x20a0 0x4e0>,
3808                                  <&apps_smmu 0x2400 0x4e0>,
3809                                  <&apps_smmu 0x2420 0x4e0>,
3810                                  <&apps_smmu 0x2440 0x4e0>,
3811                                  <&apps_smmu 0x2460 0x4e0>,
3812                                  <&apps_smmu 0x2480 0x4e0>,
3813                                  <&apps_smmu 0x24e0 0x4e0>,
3814                                  <&apps_smmu 0x24c0 0x4e0>,
3815                                  <&apps_smmu 0x24a0 0x4e0>;
3816
3817                         interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>,
3818                                         <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>,
3819                                         <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>,
3820                                         <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>;
3821                         interconnect-names = "cam_ahb",
3822                                              "cam_hf_mnoc",
3823                                              "cam_sf_mnoc",
3824                                              "cam_sf_icp_mnoc";
3825
3826                         status = "disabled";
3827
3828                         ports {
3829                                 #address-cells = <1>;
3830                                 #size-cells = <0>;
3831
3832                                 port@0 {
3833                                         reg = <0>;
3834                                         #address-cells = <1>;
3835                                         #size-cells = <0>;
3836                                 };
3837
3838                                 port@1 {
3839                                         reg = <1>;
3840                                         #address-cells = <1>;
3841                                         #size-cells = <0>;
3842                                 };
3843
3844                                 port@2 {
3845                                         reg = <2>;
3846                                         #address-cells = <1>;
3847                                         #size-cells = <0>;
3848                                 };
3849
3850                                 port@3 {
3851                                         reg = <3>;
3852                                         #address-cells = <1>;
3853                                         #size-cells = <0>;
3854                                 };
3855                         };
3856                 };
3857
3858                 camcc: clock-controller@ad00000 {
3859                         compatible = "qcom,sc8280xp-camcc";
3860                         reg = <0 0x0ad00000 0 0x20000>;
3861                         clocks = <&gcc GCC_CAMERA_AHB_CLK>,
3862                                  <&rpmhcc RPMH_CXO_CLK>,
3863                                  <&rpmhcc RPMH_CXO_CLK_A>,
3864                                  <&sleep_clk>;
3865                         power-domains = <&rpmhpd SC8280XP_MMCX>;
3866                         required-opps = <&rpmhpd_opp_low_svs>;
3867                         #clock-cells = <1>;
3868                         #reset-cells = <1>;
3869                         #power-domain-cells = <1>;
3870                 };
3871
3872                 mdss0: display-subsystem@ae00000 {
3873                         compatible = "qcom,sc8280xp-mdss";
3874                         reg = <0 0x0ae00000 0 0x1000>;
3875                         reg-names = "mdss";
3876
3877                         clocks = <&gcc GCC_DISP_AHB_CLK>,
3878                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3879                                  <&dispcc0 DISP_CC_MDSS_MDP_CLK>;
3880                         clock-names = "iface",
3881                                       "ahb",
3882                                       "core";
3883                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
3884                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
3885                                         <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
3886                         interconnect-names = "mdp0-mem", "mdp1-mem";
3887                         iommus = <&apps_smmu 0x1000 0x402>;
3888                         power-domains = <&dispcc0 MDSS_GDSC>;
3889                         resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>;
3890
3891                         interrupt-controller;
3892                         #interrupt-cells = <1>;
3893                         #address-cells = <2>;
3894                         #size-cells = <2>;
3895                         ranges;
3896
3897                         status = "disabled";
3898
3899                         mdss0_mdp: display-controller@ae01000 {
3900                                 compatible = "qcom,sc8280xp-dpu";
3901                                 reg = <0 0x0ae01000 0 0x8f000>,
3902                                       <0 0x0aeb0000 0 0x2008>;
3903                                 reg-names = "mdp", "vbif";
3904
3905                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3906                                          <&gcc GCC_DISP_SF_AXI_CLK>,
3907                                          <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3908                                          <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>,
3909                                          <&dispcc0 DISP_CC_MDSS_MDP_CLK>,
3910                                          <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
3911                                 clock-names = "bus",
3912                                               "nrt_bus",
3913                                               "iface",
3914                                               "lut",
3915                                               "core",
3916                                               "vsync";
3917                                 interrupt-parent = <&mdss0>;
3918                                 interrupts = <0>;
3919                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
3920
3921                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>;
3922                                 assigned-clock-rates = <19200000>;
3923                                 operating-points-v2 = <&mdss0_mdp_opp_table>;
3924
3925                                 ports {
3926                                         #address-cells = <1>;
3927                                         #size-cells = <0>;
3928
3929                                         port@0 {
3930                                                 reg = <0>;
3931                                                 mdss0_intf0_out: endpoint {
3932                                                         remote-endpoint = <&mdss0_dp0_in>;
3933                                                 };
3934                                         };
3935
3936                                         port@4 {
3937                                                 reg = <4>;
3938                                                 mdss0_intf4_out: endpoint {
3939                                                         remote-endpoint = <&mdss0_dp1_in>;
3940                                                 };
3941                                         };
3942
3943                                         port@5 {
3944                                                 reg = <5>;
3945                                                 mdss0_intf5_out: endpoint {
3946                                                         remote-endpoint = <&mdss0_dp3_in>;
3947                                                 };
3948                                         };
3949
3950                                         port@6 {
3951                                                 reg = <6>;
3952                                                 mdss0_intf6_out: endpoint {
3953                                                         remote-endpoint = <&mdss0_dp2_in>;
3954                                                 };
3955                                         };
3956                                 };
3957
3958                                 mdss0_mdp_opp_table: opp-table {
3959                                         compatible = "operating-points-v2";
3960
3961                                         opp-200000000 {
3962                                                 opp-hz = /bits/ 64 <200000000>;
3963                                                 required-opps = <&rpmhpd_opp_low_svs>;
3964                                         };
3965
3966                                         opp-300000000 {
3967                                                 opp-hz = /bits/ 64 <300000000>;
3968                                                 required-opps = <&rpmhpd_opp_svs>;
3969                                         };
3970
3971                                         opp-375000000 {
3972                                                 opp-hz = /bits/ 64 <375000000>;
3973                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3974                                         };
3975
3976                                         opp-500000000 {
3977                                                 opp-hz = /bits/ 64 <500000000>;
3978                                                 required-opps = <&rpmhpd_opp_nom>;
3979                                         };
3980                                         opp-600000000 {
3981                                                 opp-hz = /bits/ 64 <600000000>;
3982                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
3983                                         };
3984                                 };
3985                         };
3986
3987                         mdss0_dp0: displayport-controller@ae90000 {
3988                                 compatible = "qcom,sc8280xp-dp";
3989                                 reg = <0 0xae90000 0 0x200>,
3990                                       <0 0xae90200 0 0x200>,
3991                                       <0 0xae90400 0 0x600>,
3992                                       <0 0xae91000 0 0x400>,
3993                                       <0 0xae91400 0 0x400>;
3994                                 interrupt-parent = <&mdss0>;
3995                                 interrupts = <12>;
3996                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
3997                                          <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>,
3998                                          <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>,
3999                                          <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
4000                                          <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
4001                                 clock-names = "core_iface", "core_aux",
4002                                               "ctrl_link",
4003                                               "ctrl_link_iface",
4004                                               "stream_pixel";
4005
4006                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
4007                                                   <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
4008                                 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4009                                                          <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4010
4011                                 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>;
4012                                 phy-names = "dp";
4013
4014                                 #sound-dai-cells = <0>;
4015
4016                                 operating-points-v2 = <&mdss0_dp0_opp_table>;
4017                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4018
4019                                 status = "disabled";
4020
4021                                 ports {
4022                                         #address-cells = <1>;
4023                                         #size-cells = <0>;
4024
4025                                         port@0 {
4026                                                 reg = <0>;
4027
4028                                                 mdss0_dp0_in: endpoint {
4029                                                         remote-endpoint = <&mdss0_intf0_out>;
4030                                                 };
4031                                         };
4032
4033                                         port@1 {
4034                                                 reg = <1>;
4035
4036                                                 mdss0_dp0_out: endpoint {
4037                                                 };
4038                                         };
4039                                 };
4040
4041                                 mdss0_dp0_opp_table: opp-table {
4042                                         compatible = "operating-points-v2";
4043
4044                                         opp-160000000 {
4045                                                 opp-hz = /bits/ 64 <160000000>;
4046                                                 required-opps = <&rpmhpd_opp_low_svs>;
4047                                         };
4048
4049                                         opp-270000000 {
4050                                                 opp-hz = /bits/ 64 <270000000>;
4051                                                 required-opps = <&rpmhpd_opp_svs>;
4052                                         };
4053
4054                                         opp-540000000 {
4055                                                 opp-hz = /bits/ 64 <540000000>;
4056                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4057                                         };
4058
4059                                         opp-810000000 {
4060                                                 opp-hz = /bits/ 64 <810000000>;
4061                                                 required-opps = <&rpmhpd_opp_nom>;
4062                                         };
4063                                 };
4064                         };
4065
4066                         mdss0_dp1: displayport-controller@ae98000 {
4067                                 compatible = "qcom,sc8280xp-dp";
4068                                 reg = <0 0xae98000 0 0x200>,
4069                                       <0 0xae98200 0 0x200>,
4070                                       <0 0xae98400 0 0x600>,
4071                                       <0 0xae99000 0 0x400>,
4072                                       <0 0xae99400 0 0x400>;
4073                                 interrupt-parent = <&mdss0>;
4074                                 interrupts = <13>;
4075                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4076                                          <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>,
4077                                          <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>,
4078                                          <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
4079                                          <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
4080                                 clock-names = "core_iface", "core_aux",
4081                                               "ctrl_link",
4082                                               "ctrl_link_iface", "stream_pixel";
4083
4084                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
4085                                                   <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
4086                                 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4087                                                          <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
4088
4089                                 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
4090                                 phy-names = "dp";
4091
4092                                 #sound-dai-cells = <0>;
4093
4094                                 operating-points-v2 = <&mdss0_dp1_opp_table>;
4095                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4096
4097                                 status = "disabled";
4098
4099                                 ports {
4100                                         #address-cells = <1>;
4101                                         #size-cells = <0>;
4102
4103                                         port@0 {
4104                                                 reg = <0>;
4105
4106                                                 mdss0_dp1_in: endpoint {
4107                                                         remote-endpoint = <&mdss0_intf4_out>;
4108                                                 };
4109                                         };
4110
4111                                         port@1 {
4112                                                 reg = <1>;
4113
4114                                                 mdss0_dp1_out: endpoint {
4115                                                 };
4116                                         };
4117                                 };
4118
4119                                 mdss0_dp1_opp_table: opp-table {
4120                                         compatible = "operating-points-v2";
4121
4122                                         opp-160000000 {
4123                                                 opp-hz = /bits/ 64 <160000000>;
4124                                                 required-opps = <&rpmhpd_opp_low_svs>;
4125                                         };
4126
4127                                         opp-270000000 {
4128                                                 opp-hz = /bits/ 64 <270000000>;
4129                                                 required-opps = <&rpmhpd_opp_svs>;
4130                                         };
4131
4132                                         opp-540000000 {
4133                                                 opp-hz = /bits/ 64 <540000000>;
4134                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4135                                         };
4136
4137                                         opp-810000000 {
4138                                                 opp-hz = /bits/ 64 <810000000>;
4139                                                 required-opps = <&rpmhpd_opp_nom>;
4140                                         };
4141                                 };
4142                         };
4143
4144                         mdss0_dp2: displayport-controller@ae9a000 {
4145                                 compatible = "qcom,sc8280xp-dp";
4146                                 reg = <0 0xae9a000 0 0x200>,
4147                                       <0 0xae9a200 0 0x200>,
4148                                       <0 0xae9a400 0 0x600>,
4149                                       <0 0xae9b000 0 0x400>,
4150                                       <0 0xae9b400 0 0x400>;
4151
4152                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4153                                          <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4154                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>,
4155                                          <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
4156                                          <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
4157                                 clock-names = "core_iface", "core_aux",
4158                                               "ctrl_link",
4159                                               "ctrl_link_iface", "stream_pixel";
4160                                 interrupt-parent = <&mdss0>;
4161                                 interrupts = <14>;
4162                                 phys = <&mdss0_dp2_phy>;
4163                                 phy-names = "dp";
4164                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4165
4166                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
4167                                                   <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
4168                                 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>;
4169                                 operating-points-v2 = <&mdss0_dp2_opp_table>;
4170
4171                                 #sound-dai-cells = <0>;
4172
4173                                 status = "disabled";
4174
4175                                 ports {
4176                                         #address-cells = <1>;
4177                                         #size-cells = <0>;
4178
4179                                         port@0 {
4180                                                 reg = <0>;
4181                                                 mdss0_dp2_in: endpoint {
4182                                                         remote-endpoint = <&mdss0_intf6_out>;
4183                                                 };
4184                                         };
4185
4186                                         port@1 {
4187                                                 reg = <1>;
4188                                         };
4189                                 };
4190
4191                                 mdss0_dp2_opp_table: opp-table {
4192                                         compatible = "operating-points-v2";
4193
4194                                         opp-160000000 {
4195                                                 opp-hz = /bits/ 64 <160000000>;
4196                                                 required-opps = <&rpmhpd_opp_low_svs>;
4197                                         };
4198
4199                                         opp-270000000 {
4200                                                 opp-hz = /bits/ 64 <270000000>;
4201                                                 required-opps = <&rpmhpd_opp_svs>;
4202                                         };
4203
4204                                         opp-540000000 {
4205                                                 opp-hz = /bits/ 64 <540000000>;
4206                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4207                                         };
4208
4209                                         opp-810000000 {
4210                                                 opp-hz = /bits/ 64 <810000000>;
4211                                                 required-opps = <&rpmhpd_opp_nom>;
4212                                         };
4213                                 };
4214                         };
4215
4216                         mdss0_dp3: displayport-controller@aea0000 {
4217                                 compatible = "qcom,sc8280xp-dp";
4218                                 reg = <0 0xaea0000 0 0x200>,
4219                                       <0 0xaea0200 0 0x200>,
4220                                       <0 0xaea0400 0 0x600>,
4221                                       <0 0xaea1000 0 0x400>,
4222                                       <0 0xaea1400 0 0x400>;
4223
4224                                 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>,
4225                                          <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4226                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>,
4227                                          <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
4228                                          <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
4229                                 clock-names = "core_iface", "core_aux",
4230                                               "ctrl_link",
4231                                               "ctrl_link_iface", "stream_pixel";
4232                                 interrupt-parent = <&mdss0>;
4233                                 interrupts = <15>;
4234                                 phys = <&mdss0_dp3_phy>;
4235                                 phy-names = "dp";
4236                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
4237
4238                                 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
4239                                                   <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
4240                                 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>;
4241                                 operating-points-v2 = <&mdss0_dp3_opp_table>;
4242
4243                                 #sound-dai-cells = <0>;
4244
4245                                 status = "disabled";
4246
4247                                 ports {
4248                                         #address-cells = <1>;
4249                                         #size-cells = <0>;
4250
4251                                         port@0 {
4252                                                 reg = <0>;
4253                                                 mdss0_dp3_in: endpoint {
4254                                                         remote-endpoint = <&mdss0_intf5_out>;
4255                                                 };
4256                                         };
4257
4258                                         port@1 {
4259                                                 reg = <1>;
4260                                         };
4261                                 };
4262
4263                                 mdss0_dp3_opp_table: opp-table {
4264                                         compatible = "operating-points-v2";
4265
4266                                         opp-160000000 {
4267                                                 opp-hz = /bits/ 64 <160000000>;
4268                                                 required-opps = <&rpmhpd_opp_low_svs>;
4269                                         };
4270
4271                                         opp-270000000 {
4272                                                 opp-hz = /bits/ 64 <270000000>;
4273                                                 required-opps = <&rpmhpd_opp_svs>;
4274                                         };
4275
4276                                         opp-540000000 {
4277                                                 opp-hz = /bits/ 64 <540000000>;
4278                                                 required-opps = <&rpmhpd_opp_svs_l1>;
4279                                         };
4280
4281                                         opp-810000000 {
4282                                                 opp-hz = /bits/ 64 <810000000>;
4283                                                 required-opps = <&rpmhpd_opp_nom>;
4284                                         };
4285                                 };
4286                         };
4287                 };
4288
4289                 mdss0_dp2_phy: phy@aec2a00 {
4290                         compatible = "qcom,sc8280xp-dp-phy";
4291                         reg = <0 0x0aec2a00 0 0x19c>,
4292                               <0 0x0aec2200 0 0xec>,
4293                               <0 0x0aec2600 0 0xec>,
4294                               <0 0x0aec2000 0 0x1c8>;
4295
4296                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>,
4297                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4298                         clock-names = "aux", "cfg_ahb";
4299                         power-domains = <&rpmhpd SC8280XP_MX>;
4300
4301                         #clock-cells = <1>;
4302                         #phy-cells = <0>;
4303
4304                         status = "disabled";
4305                 };
4306
4307                 mdss0_dp3_phy: phy@aec5a00 {
4308                         compatible = "qcom,sc8280xp-dp-phy";
4309                         reg = <0 0x0aec5a00 0 0x19c>,
4310                               <0 0x0aec5200 0 0xec>,
4311                               <0 0x0aec5600 0 0xec>,
4312                               <0 0x0aec5000 0 0x1c8>;
4313
4314                         clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>,
4315                                  <&dispcc0 DISP_CC_MDSS_AHB_CLK>;
4316                         clock-names = "aux", "cfg_ahb";
4317                         power-domains = <&rpmhpd SC8280XP_MX>;
4318
4319                         #clock-cells = <1>;
4320                         #phy-cells = <0>;
4321
4322                         status = "disabled";
4323                 };
4324
4325                 dispcc0: clock-controller@af00000 {
4326                         compatible = "qcom,sc8280xp-dispcc0";
4327                         reg = <0 0x0af00000 0 0x20000>;
4328
4329                         clocks = <&gcc GCC_DISP_AHB_CLK>,
4330                                  <&rpmhcc RPMH_CXO_CLK>,
4331                                  <&sleep_clk>,
4332                                  <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4333                                  <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4334                                  <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4335                                  <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
4336                                  <&mdss0_dp2_phy 0>,
4337                                  <&mdss0_dp2_phy 1>,
4338                                  <&mdss0_dp3_phy 0>,
4339                                  <&mdss0_dp3_phy 1>,
4340                                  <0>,
4341                                  <0>,
4342                                  <0>,
4343                                  <0>;
4344                         power-domains = <&rpmhpd SC8280XP_MMCX>;
4345
4346                         #clock-cells = <1>;
4347                         #power-domain-cells = <1>;
4348                         #reset-cells = <1>;
4349
4350                         status = "disabled";
4351                 };
4352
4353                 pdc: interrupt-controller@b220000 {
4354                         compatible = "qcom,sc8280xp-pdc", "qcom,pdc";
4355                         reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
4356                         qcom,pdc-ranges = <0 480 40>,
4357                                           <40 140 14>,
4358                                           <54 263 1>,
4359                                           <55 306 4>,
4360                                           <59 312 3>,
4361                                           <62 374 2>,
4362                                           <64 434 2>,
4363                                           <66 438 3>,
4364                                           <69 86 1>,
4365                                           <70 520 54>,
4366                                           <124 609 28>,
4367                                           <159 638 1>,
4368                                           <160 720 8>,
4369                                           <168 801 1>,
4370                                           <169 728 30>,
4371                                           <199 416 2>,
4372                                           <201 449 1>,
4373                                           <202 89 1>,
4374                                           <203 451 1>,
4375                                           <204 462 1>,
4376                                           <205 264 1>,
4377                                           <206 579 1>,
4378                                           <207 653 1>,
4379                                           <208 656 1>,
4380                                           <209 659 1>,
4381                                           <210 122 1>,
4382                                           <211 699 1>,
4383                                           <212 705 1>,
4384                                           <213 450 1>,
4385                                           <214 643 1>,
4386                                           <216 646 5>,
4387                                           <221 390 5>,
4388                                           <226 700 3>,
4389                                           <229 240 3>,
4390                                           <232 269 1>,
4391                                           <233 377 1>,
4392                                           <234 372 1>,
4393                                           <235 138 1>,
4394                                           <236 857 1>,
4395                                           <237 860 1>,
4396                                           <238 137 1>,
4397                                           <239 668 1>,
4398                                           <240 366 1>,
4399                                           <241 949 1>,
4400                                           <242 815 5>,
4401                                           <247 769 1>,
4402                                           <248 768 1>,
4403                                           <249 663 1>,
4404                                           <250 799 2>,
4405                                           <252 798 1>,
4406                                           <253 765 1>,
4407                                           <254 763 1>,
4408                                           <255 454 1>,
4409                                           <258 139 1>,
4410                                           <259 786 2>,
4411                                           <261 370 2>,
4412                                           <263 158 2>;
4413                         #interrupt-cells = <2>;
4414                         interrupt-parent = <&intc>;
4415                         interrupt-controller;
4416                 };
4417
4418                 tsens2: thermal-sensor@c251000 {
4419                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4420                         reg = <0 0x0c251000 0 0x1ff>,
4421                               <0 0x0c224000 0 0x8>;
4422                         #qcom,sensors = <11>;
4423                         interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>,
4424                                               <&pdc 124 IRQ_TYPE_LEVEL_HIGH>;
4425                         interrupt-names = "uplow", "critical";
4426                         #thermal-sensor-cells = <1>;
4427                 };
4428
4429                 tsens3: thermal-sensor@c252000 {
4430                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4431                         reg = <0 0x0c252000 0 0x1ff>,
4432                               <0 0x0c225000 0 0x8>;
4433                         #qcom,sensors = <5>;
4434                         interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>,
4435                                               <&pdc 125 IRQ_TYPE_LEVEL_HIGH>;
4436                         interrupt-names = "uplow", "critical";
4437                         #thermal-sensor-cells = <1>;
4438                 };
4439
4440                 tsens0: thermal-sensor@c263000 {
4441                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4442                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
4443                               <0 0x0c222000 0 0x8>; /* SROT */
4444                         #qcom,sensors = <14>;
4445                         interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
4446                                               <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
4447                         interrupt-names = "uplow", "critical";
4448                         #thermal-sensor-cells = <1>;
4449                 };
4450
4451                 tsens1: thermal-sensor@c265000 {
4452                         compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2";
4453                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
4454                               <0 0x0c223000 0 0x8>; /* SROT */
4455                         #qcom,sensors = <16>;
4456                         interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
4457                                               <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
4458                         interrupt-names = "uplow", "critical";
4459                         #thermal-sensor-cells = <1>;
4460                 };
4461
4462                 aoss_qmp: power-management@c300000 {
4463                         compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp";
4464                         reg = <0 0x0c300000 0 0x400>;
4465                         interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>;
4466                         mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
4467
4468                         #clock-cells = <0>;
4469                 };
4470
4471                 sram@c3f0000 {
4472                         compatible = "qcom,rpmh-stats";
4473                         reg = <0 0x0c3f0000 0 0x400>;
4474                         qcom,qmp = <&aoss_qmp>;
4475                 };
4476
4477                 spmi_bus: spmi@c440000 {
4478                         compatible = "qcom,spmi-pmic-arb";
4479                         reg = <0 0x0c440000 0 0x1100>,
4480                               <0 0x0c600000 0 0x2000000>,
4481                               <0 0x0e600000 0 0x100000>,
4482                               <0 0x0e700000 0 0xa0000>,
4483                               <0 0x0c40a000 0 0x26000>;
4484                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4485                         interrupt-names = "periph_irq";
4486                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4487                         qcom,ee = <0>;
4488                         qcom,channel = <0>;
4489                         #address-cells = <2>;
4490                         #size-cells = <0>;
4491                         interrupt-controller;
4492                         #interrupt-cells = <4>;
4493                 };
4494
4495                 tlmm: pinctrl@f100000 {
4496                         compatible = "qcom,sc8280xp-tlmm";
4497                         reg = <0 0x0f100000 0 0x300000>;
4498                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
4499                         gpio-controller;
4500                         #gpio-cells = <2>;
4501                         interrupt-controller;
4502                         #interrupt-cells = <2>;
4503                         gpio-ranges = <&tlmm 0 0 230>;
4504                         wakeup-parent = <&pdc>;
4505
4506                         cci0_default: cci0-default-state {
4507                                 cci0_i2c0_default: cci0-i2c0-default-pins {
4508                                         /* cci_i2c_sda0, cci_i2c_scl0 */
4509                                         pins = "gpio113", "gpio114";
4510                                         function = "cci_i2c";
4511                                         drive-strength = <2>;
4512                                         bias-pull-up;
4513                                 };
4514
4515                                 cci0_i2c1_default: cci0-i2c1-default-pins {
4516                                         /* cci_i2c_sda1, cci_i2c_scl1 */
4517                                         pins = "gpio115", "gpio116";
4518                                         function = "cci_i2c";
4519                                         drive-strength = <2>;
4520                                         bias-pull-up;
4521                                 };
4522                         };
4523
4524                         cci0_sleep: cci0-sleep-state {
4525                                 cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
4526                                         /* cci_i2c_sda0, cci_i2c_scl0 */
4527                                         pins = "gpio113", "gpio114";
4528                                         function = "cci_i2c";
4529                                         drive-strength = <2>;
4530                                         bias-pull-down;
4531                                 };
4532
4533                                 cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
4534                                         /* cci_i2c_sda1, cci_i2c_scl1 */
4535                                         pins = "gpio115", "gpio116";
4536                                         function = "cci_i2c";
4537                                         drive-strength = <2>;
4538                                         bias-pull-down;
4539                                 };
4540                         };
4541
4542                         cci1_default: cci1-default-state {
4543                                 cci1_i2c0_default: cci1-i2c0-default-pins {
4544                                         /* cci_i2c_sda2, cci_i2c_scl2 */
4545                                         pins = "gpio10","gpio11";
4546                                         function = "cci_i2c";
4547                                         drive-strength = <2>;
4548                                         bias-pull-up;
4549                                 };
4550
4551                                 cci1_i2c1_default: cci1-i2c1-default-pins {
4552                                         /* cci_i2c_sda3, cci_i2c_scl3 */
4553                                         pins = "gpio123","gpio124";
4554                                         function = "cci_i2c";
4555                                         drive-strength = <2>;
4556                                         bias-pull-up;
4557                                 };
4558                         };
4559
4560                         cci1_sleep: cci1-sleep-state {
4561                                 cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
4562                                         /* cci_i2c_sda2, cci_i2c_scl2 */
4563                                         pins = "gpio10","gpio11";
4564                                         function = "cci_i2c";
4565                                         drive-strength = <2>;
4566                                         bias-pull-down;
4567                                 };
4568
4569                                 cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
4570                                         /* cci_i2c_sda3, cci_i2c_scl3 */
4571                                         pins = "gpio123","gpio124";
4572                                         function = "cci_i2c";
4573                                         drive-strength = <2>;
4574                                         bias-pull-down;
4575                                 };
4576                         };
4577
4578                         cci2_default: cci2-default-state {
4579                                 cci2_i2c0_default: cci2-i2c0-default-pins {
4580                                         /* cci_i2c_sda4, cci_i2c_scl4 */
4581                                         pins = "gpio117","gpio118";
4582                                         function = "cci_i2c";
4583                                         drive-strength = <2>;
4584                                         bias-pull-up;
4585                                 };
4586
4587                                 cci2_i2c1_default: cci2-i2c1-default-pins {
4588                                         /* cci_i2c_sda5, cci_i2c_scl5 */
4589                                         pins = "gpio12","gpio13";
4590                                         function = "cci_i2c";
4591                                         drive-strength = <2>;
4592                                         bias-pull-up;
4593                                 };
4594                         };
4595
4596                         cci2_sleep: cci2-sleep-state {
4597                                 cci2_i2c0_sleep: cci2-i2c0-sleep-pins {
4598                                         /* cci_i2c_sda4, cci_i2c_scl4 */
4599                                         pins = "gpio117","gpio118";
4600                                         function = "cci_i2c";
4601                                         drive-strength = <2>;
4602                                         bias-pull-down;
4603                                 };
4604
4605                                 cci2_i2c1_sleep: cci2-i2c1-sleep-pins {
4606                                         /* cci_i2c_sda5, cci_i2c_scl5 */
4607                                         pins = "gpio12","gpio13";
4608                                         function = "cci_i2c";
4609                                         drive-strength = <2>;
4610                                         bias-pull-down;
4611                                 };
4612                         };
4613
4614                         cci3_default: cci3-default-state {
4615                                 cci3_i2c0_default: cci3-i2c0-default-pins {
4616                                         /* cci_i2c_sda6, cci_i2c_scl6 */
4617                                         pins = "gpio145","gpio146";
4618                                         function = "cci_i2c";
4619                                         drive-strength = <2>;
4620                                         bias-pull-up;
4621                                 };
4622
4623                                 cci3_i2c1_default: cci3-i2c1-default-pins {
4624                                         /* cci_i2c_sda7, cci_i2c_scl7 */
4625                                         pins = "gpio164","gpio165";
4626                                         function = "cci_i2c";
4627                                         drive-strength = <2>;
4628                                         bias-pull-up;
4629                                 };
4630                         };
4631
4632                         cci3_sleep: cci3-sleep-state {
4633                                 cci3_i2c0_sleep: cci3-i2c0-sleep-pins {
4634                                         /* cci_i2c_sda6, cci_i2c_scl6 */
4635                                         pins = "gpio145","gpio146";
4636                                         function = "cci_i2c";
4637                                         drive-strength = <2>;
4638                                         bias-pull-down;
4639                                 };
4640
4641                                 cci3_i2c1_sleep: cci3-i2c1-sleep-pins {
4642                                         /* cci_i2c_sda7, cci_i2c_scl7 */
4643                                         pins = "gpio164","gpio165";
4644                                         function = "cci_i2c";
4645                                         drive-strength = <2>;
4646                                         bias-pull-down;
4647                                 };
4648                         };
4649                 };
4650
4651                 apps_smmu: iommu@15000000 {
4652                         compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500";
4653                         reg = <0 0x15000000 0 0x100000>;
4654                         #iommu-cells = <2>;
4655                         #global-interrupts = <2>;
4656                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
4657                                      <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
4658                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4659                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
4660                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
4661                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4662                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4663                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
4664                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
4665                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4666                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4667                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4668                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
4669                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
4670                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
4671                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4672                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
4673                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
4674                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
4675                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
4676                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
4677                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
4678                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
4679                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
4680                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
4681                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
4682                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
4683                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
4684                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
4685                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
4686                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
4687                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
4688                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
4689                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
4690                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
4691                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
4692                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
4693                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
4694                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
4695                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
4696                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
4697                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
4698                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
4699                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
4700                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
4701                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
4702                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
4703                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
4704                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
4705                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
4706                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
4707                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
4708                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
4709                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
4710                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
4711                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
4712                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
4713                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
4714                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
4715                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
4716                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
4717                                      <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
4718                                      <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
4719                                      <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
4720                                      <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
4721                                      <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
4722                                      <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
4723                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
4724                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
4725                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
4726                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
4727                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
4728                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
4729                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
4730                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
4731                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
4732                                      <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
4733                                      <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
4734                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
4735                                      <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
4736                                      <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
4737                                      <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
4738                                      <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
4739                                      <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
4740                                      <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
4741                                      <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
4742                                      <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
4743                                      <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
4744                                      <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
4745                                      <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
4746                                      <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
4747                                      <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
4748                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
4749                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
4750                                      <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
4751                                      <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
4752                                      <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4753                                      <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
4754                                      <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
4755                                      <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
4756                                      <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
4757                                      <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
4758                                      <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
4759                                      <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
4760                                      <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
4761                                      <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
4762                                      <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
4763                                      <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
4764                                      <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
4765                                      <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
4766                                      <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
4767                                      <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
4768                                      <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
4769                                      <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
4770                                      <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
4771                                      <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
4772                                      <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
4773                                      <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
4774                                      <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
4775                                      <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
4776                                      <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
4777                                      <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
4778                                      <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
4779                                      <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
4780                                      <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
4781                                      <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
4782                                      <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
4783                                      <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
4784                                      <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>,
4785                                      <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>;
4786                 };
4787
4788                 intc: interrupt-controller@17a00000 {
4789                         compatible = "arm,gic-v3";
4790                         interrupt-controller;
4791                         #interrupt-cells = <3>;
4792                         reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
4793                               <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
4794                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
4795                         #redistributor-regions = <1>;
4796                         redistributor-stride = <0 0x20000>;
4797
4798                         #address-cells = <2>;
4799                         #size-cells = <2>;
4800                         ranges;
4801
4802                         msi-controller@17a40000 {
4803                                 compatible = "arm,gic-v3-its";
4804                                 reg = <0 0x17a40000 0 0x20000>;
4805                                 msi-controller;
4806                                 #msi-cells = <1>;
4807                         };
4808                 };
4809
4810                 watchdog@17c10000 {
4811                         compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt";
4812                         reg = <0 0x17c10000 0 0x1000>;
4813                         clocks = <&sleep_clk>;
4814                         interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
4815                 };
4816
4817                 timer@17c20000 {
4818                         compatible = "arm,armv7-timer-mem";
4819                         reg = <0x0 0x17c20000 0x0 0x1000>;
4820                         #address-cells = <1>;
4821                         #size-cells = <1>;
4822                         ranges = <0x0 0x0 0x0 0x20000000>;
4823
4824                         frame@17c21000 {
4825                                 frame-number = <0>;
4826                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
4827                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4828                                 reg = <0x17c21000 0x1000>,
4829                                       <0x17c22000 0x1000>;
4830                         };
4831
4832                         frame@17c23000 {
4833                                 frame-number = <1>;
4834                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
4835                                 reg = <0x17c23000 0x1000>;
4836                                 status = "disabled";
4837                         };
4838
4839                         frame@17c25000 {
4840                                 frame-number = <2>;
4841                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
4842                                 reg = <0x17c25000 0x1000>;
4843                                 status = "disabled";
4844                         };
4845
4846                         frame@17c27000 {
4847                                 frame-number = <3>;
4848                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
4849                                 reg = <0x17c26000 0x1000>;
4850                                 status = "disabled";
4851                         };
4852
4853                         frame@17c29000 {
4854                                 frame-number = <4>;
4855                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
4856                                 reg = <0x17c29000 0x1000>;
4857                                 status = "disabled";
4858                         };
4859
4860                         frame@17c2b000 {
4861                                 frame-number = <5>;
4862                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
4863                                 reg = <0x17c2b000 0x1000>;
4864                                 status = "disabled";
4865                         };
4866
4867                         frame@17c2d000 {
4868                                 frame-number = <6>;
4869                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
4870                                 reg = <0x17c2d000 0x1000>;
4871                                 status = "disabled";
4872                         };
4873                 };
4874
4875                 apps_rsc: rsc@18200000 {
4876                         compatible = "qcom,rpmh-rsc";
4877                         reg = <0x0 0x18200000 0x0 0x10000>,
4878                                 <0x0 0x18210000 0x0 0x10000>,
4879                                 <0x0 0x18220000 0x0 0x10000>;
4880                         reg-names = "drv-0", "drv-1", "drv-2";
4881                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
4882                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
4883                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
4884                         qcom,tcs-offset = <0xd00>;
4885                         qcom,drv-id = <2>;
4886                         qcom,tcs-config = <ACTIVE_TCS  2>, <SLEEP_TCS   3>,
4887                                           <WAKE_TCS    3>, <CONTROL_TCS 1>;
4888                         label = "apps_rsc";
4889                         power-domains = <&CLUSTER_PD>;
4890
4891                         apps_bcm_voter: bcm-voter {
4892                                 compatible = "qcom,bcm-voter";
4893                         };
4894
4895                         rpmhcc: clock-controller {
4896                                 compatible = "qcom,sc8280xp-rpmh-clk";
4897                                 #clock-cells = <1>;
4898                                 clock-names = "xo";
4899                                 clocks = <&xo_board_clk>;
4900                         };
4901
4902                         rpmhpd: power-controller {
4903                                 compatible = "qcom,sc8280xp-rpmhpd";
4904                                 #power-domain-cells = <1>;
4905                                 operating-points-v2 = <&rpmhpd_opp_table>;
4906
4907                                 rpmhpd_opp_table: opp-table {
4908                                         compatible = "operating-points-v2";
4909
4910                                         rpmhpd_opp_ret: opp1 {
4911                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4912                                         };
4913
4914                                         rpmhpd_opp_min_svs: opp2 {
4915                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4916                                         };
4917
4918                                         rpmhpd_opp_low_svs: opp3 {
4919                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4920                                         };
4921
4922                                         rpmhpd_opp_svs: opp4 {
4923                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4924                                         };
4925
4926                                         rpmhpd_opp_svs_l1: opp5 {
4927                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4928                                         };
4929
4930                                         rpmhpd_opp_nom: opp6 {
4931                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4932                                         };
4933
4934                                         rpmhpd_opp_nom_l1: opp7 {
4935                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4936                                         };
4937
4938                                         rpmhpd_opp_nom_l2: opp8 {
4939                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4940                                         };
4941
4942                                         rpmhpd_opp_turbo: opp9 {
4943                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4944                                         };
4945
4946                                         rpmhpd_opp_turbo_l1: opp10 {
4947                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4948                                         };
4949                                 };
4950                         };
4951                 };
4952
4953                 epss_l3: interconnect@18590000 {
4954                         compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3";
4955                         reg = <0 0x18590000 0 0x1000>;
4956
4957                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4958                         clock-names = "xo", "alternate";
4959
4960                         #interconnect-cells = <1>;
4961                 };
4962
4963                 cpufreq_hw: cpufreq@18591000 {
4964                         compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss";
4965                         reg = <0 0x18591000 0 0x1000>,
4966                               <0 0x18592000 0 0x1000>;
4967                         reg-names = "freq-domain0", "freq-domain1";
4968
4969                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
4970                         clock-names = "xo", "alternate";
4971
4972                         #freq-domain-cells = <1>;
4973                         #clock-cells = <1>;
4974                 };
4975
4976                 remoteproc_nsp0: remoteproc@1b300000 {
4977                         compatible = "qcom,sc8280xp-nsp0-pas";
4978                         reg = <0 0x1b300000 0 0x100>;
4979
4980                         interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
4981                                               <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>,
4982                                               <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>,
4983                                               <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>,
4984                                               <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>;
4985                         interrupt-names = "wdog", "fatal", "ready",
4986                                           "handover", "stop-ack";
4987
4988                         clocks = <&rpmhcc RPMH_CXO_CLK>;
4989                         clock-names = "xo";
4990
4991                         power-domains = <&rpmhpd SC8280XP_NSP>;
4992                         power-domain-names = "nsp";
4993
4994                         memory-region = <&pil_nsp0_mem>;
4995
4996                         qcom,smem-states = <&smp2p_nsp0_out 0>;
4997                         qcom,smem-state-names = "stop";
4998
4999                         interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
5000
5001                         status = "disabled";
5002
5003                         glink-edge {
5004                                 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
5005                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
5006                                                              IRQ_TYPE_EDGE_RISING>;
5007                                 mboxes = <&ipcc IPCC_CLIENT_CDSP
5008                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5009
5010                                 label = "nsp0";
5011                                 qcom,remote-pid = <5>;
5012
5013                                 fastrpc {
5014                                         compatible = "qcom,fastrpc";
5015                                         qcom,glink-channels = "fastrpcglink-apps-dsp";
5016                                         label = "cdsp";
5017                                         #address-cells = <1>;
5018                                         #size-cells = <0>;
5019
5020                                         compute-cb@1 {
5021                                                 compatible = "qcom,fastrpc-compute-cb";
5022                                                 reg = <1>;
5023                                                 iommus = <&apps_smmu 0x3181 0x0420>;
5024                                         };
5025
5026                                         compute-cb@2 {
5027                                                 compatible = "qcom,fastrpc-compute-cb";
5028                                                 reg = <2>;
5029                                                 iommus = <&apps_smmu 0x3182 0x0420>;
5030                                         };
5031
5032                                         compute-cb@3 {
5033                                                 compatible = "qcom,fastrpc-compute-cb";
5034                                                 reg = <3>;
5035                                                 iommus = <&apps_smmu 0x3183 0x0420>;
5036                                         };
5037
5038                                         compute-cb@4 {
5039                                                 compatible = "qcom,fastrpc-compute-cb";
5040                                                 reg = <4>;
5041                                                 iommus = <&apps_smmu 0x3184 0x0420>;
5042                                         };
5043
5044                                         compute-cb@5 {
5045                                                 compatible = "qcom,fastrpc-compute-cb";
5046                                                 reg = <5>;
5047                                                 iommus = <&apps_smmu 0x3185 0x0420>;
5048                                         };
5049
5050                                         compute-cb@6 {
5051                                                 compatible = "qcom,fastrpc-compute-cb";
5052                                                 reg = <6>;
5053                                                 iommus = <&apps_smmu 0x3186 0x0420>;
5054                                         };
5055
5056                                         compute-cb@7 {
5057                                                 compatible = "qcom,fastrpc-compute-cb";
5058                                                 reg = <7>;
5059                                                 iommus = <&apps_smmu 0x3187 0x0420>;
5060                                         };
5061
5062                                         compute-cb@8 {
5063                                                 compatible = "qcom,fastrpc-compute-cb";
5064                                                 reg = <8>;
5065                                                 iommus = <&apps_smmu 0x3188 0x0420>;
5066                                         };
5067
5068                                         compute-cb@9 {
5069                                                 compatible = "qcom,fastrpc-compute-cb";
5070                                                 reg = <9>;
5071                                                 iommus = <&apps_smmu 0x318b 0x0420>;
5072                                         };
5073
5074                                         compute-cb@10 {
5075                                                 compatible = "qcom,fastrpc-compute-cb";
5076                                                 reg = <10>;
5077                                                 iommus = <&apps_smmu 0x318b 0x0420>;
5078                                         };
5079
5080                                         compute-cb@11 {
5081                                                 compatible = "qcom,fastrpc-compute-cb";
5082                                                 reg = <11>;
5083                                                 iommus = <&apps_smmu 0x318c 0x0420>;
5084                                         };
5085
5086                                         compute-cb@12 {
5087                                                 compatible = "qcom,fastrpc-compute-cb";
5088                                                 reg = <12>;
5089                                                 iommus = <&apps_smmu 0x318d 0x0420>;
5090                                         };
5091
5092                                         compute-cb@13 {
5093                                                 compatible = "qcom,fastrpc-compute-cb";
5094                                                 reg = <13>;
5095                                                 iommus = <&apps_smmu 0x318e 0x0420>;
5096                                         };
5097
5098                                         compute-cb@14 {
5099                                                 compatible = "qcom,fastrpc-compute-cb";
5100                                                 reg = <14>;
5101                                                 iommus = <&apps_smmu 0x318f 0x0420>;
5102                                         };
5103                                 };
5104                         };
5105                 };
5106
5107                 remoteproc_nsp1: remoteproc@21300000 {
5108                         compatible = "qcom,sc8280xp-nsp1-pas";
5109                         reg = <0 0x21300000 0 0x100>;
5110
5111                         interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>,
5112                                               <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>,
5113                                               <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>,
5114                                               <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>,
5115                                               <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>;
5116                         interrupt-names = "wdog", "fatal", "ready",
5117                                           "handover", "stop-ack";
5118
5119                         clocks = <&rpmhcc RPMH_CXO_CLK>;
5120                         clock-names = "xo";
5121
5122                         power-domains = <&rpmhpd SC8280XP_NSP>;
5123                         power-domain-names = "nsp";
5124
5125                         memory-region = <&pil_nsp1_mem>;
5126
5127                         qcom,smem-states = <&smp2p_nsp1_out 0>;
5128                         qcom,smem-state-names = "stop";
5129
5130                         interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>;
5131
5132                         status = "disabled";
5133
5134                         glink-edge {
5135                                 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1
5136                                                              IPCC_MPROC_SIGNAL_GLINK_QMP
5137                                                              IRQ_TYPE_EDGE_RISING>;
5138                                 mboxes = <&ipcc IPCC_CLIENT_NSP1
5139                                                 IPCC_MPROC_SIGNAL_GLINK_QMP>;
5140
5141                                 label = "nsp1";
5142                                 qcom,remote-pid = <12>;
5143                         };
5144                 };
5145
5146                 mdss1: display-subsystem@22000000 {
5147                         compatible = "qcom,sc8280xp-mdss";
5148                         reg = <0 0x22000000 0 0x1000>;
5149                         reg-names = "mdss";
5150
5151                         clocks = <&gcc GCC_DISP_AHB_CLK>,
5152                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5153                                  <&dispcc1 DISP_CC_MDSS_MDP_CLK>;
5154                         clock-names = "iface",
5155                                       "ahb",
5156                                       "core";
5157                         interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>,
5158                                         <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>;
5159                         interconnect-names = "mdp0-mem", "mdp1-mem";
5160                         interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>;
5161
5162                         iommus = <&apps_smmu 0x1800 0x402>;
5163                         power-domains = <&dispcc1 MDSS_GDSC>;
5164                         resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>;
5165
5166                         interrupt-controller;
5167                         #interrupt-cells = <1>;
5168                         #address-cells = <2>;
5169                         #size-cells = <2>;
5170                         ranges;
5171
5172                         status = "disabled";
5173
5174                         mdss1_mdp: display-controller@22001000 {
5175                                 compatible = "qcom,sc8280xp-dpu";
5176                                 reg = <0 0x22001000 0 0x8f000>,
5177                                       <0 0x220b0000 0 0x2008>;
5178                                 reg-names = "mdp", "vbif";
5179
5180                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5181                                          <&gcc GCC_DISP_SF_AXI_CLK>,
5182                                          <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5183                                          <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>,
5184                                          <&dispcc1 DISP_CC_MDSS_MDP_CLK>,
5185                                          <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5186                                 clock-names = "bus",
5187                                               "nrt_bus",
5188                                               "iface",
5189                                               "lut",
5190                                               "core",
5191                                               "vsync";
5192                                 interrupt-parent = <&mdss1>;
5193                                 interrupts = <0>;
5194                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5195
5196                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>;
5197                                 assigned-clock-rates = <19200000>;
5198                                 operating-points-v2 = <&mdss1_mdp_opp_table>;
5199
5200                                 ports {
5201                                         #address-cells = <1>;
5202                                         #size-cells = <0>;
5203
5204                                         port@0 {
5205                                                 reg = <0>;
5206                                                 mdss1_intf0_out: endpoint {
5207                                                         remote-endpoint = <&mdss1_dp0_in>;
5208                                                 };
5209                                         };
5210
5211                                         port@4 {
5212                                                 reg = <4>;
5213                                                 mdss1_intf4_out: endpoint {
5214                                                         remote-endpoint = <&mdss1_dp1_in>;
5215                                                 };
5216                                         };
5217
5218                                         port@5 {
5219                                                 reg = <5>;
5220                                                 mdss1_intf5_out: endpoint {
5221                                                         remote-endpoint = <&mdss1_dp3_in>;
5222                                                 };
5223                                         };
5224
5225                                         port@6 {
5226                                                 reg = <6>;
5227                                                 mdss1_intf6_out: endpoint {
5228                                                         remote-endpoint = <&mdss1_dp2_in>;
5229                                                 };
5230                                         };
5231                                 };
5232
5233                                 mdss1_mdp_opp_table: opp-table {
5234                                         compatible = "operating-points-v2";
5235
5236                                         opp-200000000 {
5237                                                 opp-hz = /bits/ 64 <200000000>;
5238                                                 required-opps = <&rpmhpd_opp_low_svs>;
5239                                         };
5240
5241                                         opp-300000000 {
5242                                                 opp-hz = /bits/ 64 <300000000>;
5243                                                 required-opps = <&rpmhpd_opp_svs>;
5244                                         };
5245
5246                                         opp-375000000 {
5247                                                 opp-hz = /bits/ 64 <375000000>;
5248                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5249                                         };
5250
5251                                         opp-500000000 {
5252                                                 opp-hz = /bits/ 64 <500000000>;
5253                                                 required-opps = <&rpmhpd_opp_nom>;
5254                                         };
5255                                         opp-600000000 {
5256                                                 opp-hz = /bits/ 64 <600000000>;
5257                                                 required-opps = <&rpmhpd_opp_turbo_l1>;
5258                                         };
5259                                 };
5260                         };
5261
5262                         mdss1_dp0: displayport-controller@22090000 {
5263                                 compatible = "qcom,sc8280xp-dp";
5264                                 reg = <0 0x22090000 0 0x200>,
5265                                       <0 0x22090200 0 0x200>,
5266                                       <0 0x22090400 0 0x600>,
5267                                       <0 0x22091000 0 0x400>,
5268                                       <0 0x22091400 0 0x400>;
5269
5270                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5271                                          <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>,
5272                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>,
5273                                          <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
5274                                          <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
5275                                 clock-names = "core_iface", "core_aux",
5276                                               "ctrl_link",
5277                                               "ctrl_link_iface", "stream_pixel";
5278                                 interrupt-parent = <&mdss1>;
5279                                 interrupts = <12>;
5280                                 phys = <&mdss1_dp0_phy>;
5281                                 phy-names = "dp";
5282                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5283
5284                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5285                                                   <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
5286                                 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>;
5287                                 operating-points-v2 = <&mdss1_dp0_opp_table>;
5288
5289                                 #sound-dai-cells = <0>;
5290
5291                                 status = "disabled";
5292
5293                                 ports {
5294                                         #address-cells = <1>;
5295                                         #size-cells = <0>;
5296
5297                                         port@0 {
5298                                                 reg = <0>;
5299                                                 mdss1_dp0_in: endpoint {
5300                                                         remote-endpoint = <&mdss1_intf0_out>;
5301                                                 };
5302                                         };
5303
5304                                         port@1 {
5305                                                 reg = <1>;
5306                                         };
5307                                 };
5308
5309                                 mdss1_dp0_opp_table: opp-table {
5310                                         compatible = "operating-points-v2";
5311
5312                                         opp-160000000 {
5313                                                 opp-hz = /bits/ 64 <160000000>;
5314                                                 required-opps = <&rpmhpd_opp_low_svs>;
5315                                         };
5316
5317                                         opp-270000000 {
5318                                                 opp-hz = /bits/ 64 <270000000>;
5319                                                 required-opps = <&rpmhpd_opp_svs>;
5320                                         };
5321
5322                                         opp-540000000 {
5323                                                 opp-hz = /bits/ 64 <540000000>;
5324                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5325                                         };
5326
5327                                         opp-810000000 {
5328                                                 opp-hz = /bits/ 64 <810000000>;
5329                                                 required-opps = <&rpmhpd_opp_nom>;
5330                                         };
5331                                 };
5332                         };
5333
5334                         mdss1_dp1: displayport-controller@22098000 {
5335                                 compatible = "qcom,sc8280xp-dp";
5336                                 reg = <0 0x22098000 0 0x200>,
5337                                       <0 0x22098200 0 0x200>,
5338                                       <0 0x22098400 0 0x600>,
5339                                       <0 0x22099000 0 0x400>,
5340                                       <0 0x22099400 0 0x400>;
5341
5342                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5343                                          <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>,
5344                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>,
5345                                          <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
5346                                          <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
5347                                 clock-names = "core_iface", "core_aux",
5348                                               "ctrl_link",
5349                                               "ctrl_link_iface", "stream_pixel";
5350                                 interrupt-parent = <&mdss1>;
5351                                 interrupts = <13>;
5352                                 phys = <&mdss1_dp1_phy>;
5353                                 phy-names = "dp";
5354                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5355
5356                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5357                                                   <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
5358                                 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>;
5359                                 operating-points-v2 = <&mdss1_dp1_opp_table>;
5360
5361                                 #sound-dai-cells = <0>;
5362
5363                                 status = "disabled";
5364
5365                                 ports {
5366                                         #address-cells = <1>;
5367                                         #size-cells = <0>;
5368
5369                                         port@0 {
5370                                                 reg = <0>;
5371                                                 mdss1_dp1_in: endpoint {
5372                                                         remote-endpoint = <&mdss1_intf4_out>;
5373                                                 };
5374                                         };
5375
5376                                         port@1 {
5377                                                 reg = <1>;
5378                                         };
5379                                 };
5380
5381                                 mdss1_dp1_opp_table: opp-table {
5382                                         compatible = "operating-points-v2";
5383
5384                                         opp-160000000 {
5385                                                 opp-hz = /bits/ 64 <160000000>;
5386                                                 required-opps = <&rpmhpd_opp_low_svs>;
5387                                         };
5388
5389                                         opp-270000000 {
5390                                                 opp-hz = /bits/ 64 <270000000>;
5391                                                 required-opps = <&rpmhpd_opp_svs>;
5392                                         };
5393
5394                                         opp-540000000 {
5395                                                 opp-hz = /bits/ 64 <540000000>;
5396                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5397                                         };
5398
5399                                         opp-810000000 {
5400                                                 opp-hz = /bits/ 64 <810000000>;
5401                                                 required-opps = <&rpmhpd_opp_nom>;
5402                                         };
5403                                 };
5404                         };
5405
5406                         mdss1_dp2: displayport-controller@2209a000 {
5407                                 compatible = "qcom,sc8280xp-dp";
5408                                 reg = <0 0x2209a000 0 0x200>,
5409                                       <0 0x2209a200 0 0x200>,
5410                                       <0 0x2209a400 0 0x600>,
5411                                       <0 0x2209b000 0 0x400>,
5412                                       <0 0x2209b400 0 0x400>;
5413
5414                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5415                                          <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5416                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>,
5417                                          <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
5418                                          <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
5419                                 clock-names = "core_iface", "core_aux",
5420                                               "ctrl_link",
5421                                               "ctrl_link_iface", "stream_pixel";
5422                                 interrupt-parent = <&mdss1>;
5423                                 interrupts = <14>;
5424                                 phys = <&mdss1_dp2_phy>;
5425                                 phy-names = "dp";
5426                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5427
5428                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5429                                                   <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
5430                                 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>;
5431                                 operating-points-v2 = <&mdss1_dp2_opp_table>;
5432
5433                                 #sound-dai-cells = <0>;
5434
5435                                 status = "disabled";
5436
5437                                 ports {
5438                                         #address-cells = <1>;
5439                                         #size-cells = <0>;
5440
5441                                         port@0 {
5442                                                 reg = <0>;
5443                                                 mdss1_dp2_in: endpoint {
5444                                                         remote-endpoint = <&mdss1_intf6_out>;
5445                                                 };
5446                                         };
5447
5448                                         port@1 {
5449                                                 reg = <1>;
5450                                         };
5451                                 };
5452
5453                                 mdss1_dp2_opp_table: opp-table {
5454                                         compatible = "operating-points-v2";
5455
5456                                         opp-160000000 {
5457                                                 opp-hz = /bits/ 64 <160000000>;
5458                                                 required-opps = <&rpmhpd_opp_low_svs>;
5459                                         };
5460
5461                                         opp-270000000 {
5462                                                 opp-hz = /bits/ 64 <270000000>;
5463                                                 required-opps = <&rpmhpd_opp_svs>;
5464                                         };
5465
5466                                         opp-540000000 {
5467                                                 opp-hz = /bits/ 64 <540000000>;
5468                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5469                                         };
5470
5471                                         opp-810000000 {
5472                                                 opp-hz = /bits/ 64 <810000000>;
5473                                                 required-opps = <&rpmhpd_opp_nom>;
5474                                         };
5475                                 };
5476                         };
5477
5478                         mdss1_dp3: displayport-controller@220a0000 {
5479                                 compatible = "qcom,sc8280xp-dp";
5480                                 reg = <0 0x220a0000 0 0x200>,
5481                                       <0 0x220a0200 0 0x200>,
5482                                       <0 0x220a0400 0 0x600>,
5483                                       <0 0x220a1000 0 0x400>,
5484                                       <0 0x220a1400 0 0x400>;
5485
5486                                 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>,
5487                                          <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5488                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>,
5489                                          <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
5490                                          <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
5491                                 clock-names = "core_iface", "core_aux",
5492                                               "ctrl_link",
5493                                               "ctrl_link_iface", "stream_pixel";
5494                                 interrupt-parent = <&mdss1>;
5495                                 interrupts = <15>;
5496                                 phys = <&mdss1_dp3_phy>;
5497                                 phy-names = "dp";
5498                                 power-domains = <&rpmhpd SC8280XP_MMCX>;
5499
5500                                 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5501                                                   <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
5502                                 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>;
5503                                 operating-points-v2 = <&mdss1_dp3_opp_table>;
5504
5505                                 #sound-dai-cells = <0>;
5506
5507                                 status = "disabled";
5508
5509                                 ports {
5510                                         #address-cells = <1>;
5511                                         #size-cells = <0>;
5512
5513                                         port@0 {
5514                                                 reg = <0>;
5515                                                 mdss1_dp3_in: endpoint {
5516                                                         remote-endpoint = <&mdss1_intf5_out>;
5517                                                 };
5518                                         };
5519
5520                                         port@1 {
5521                                                 reg = <1>;
5522                                         };
5523                                 };
5524
5525                                 mdss1_dp3_opp_table: opp-table {
5526                                         compatible = "operating-points-v2";
5527
5528                                         opp-160000000 {
5529                                                 opp-hz = /bits/ 64 <160000000>;
5530                                                 required-opps = <&rpmhpd_opp_low_svs>;
5531                                         };
5532
5533                                         opp-270000000 {
5534                                                 opp-hz = /bits/ 64 <270000000>;
5535                                                 required-opps = <&rpmhpd_opp_svs>;
5536                                         };
5537
5538                                         opp-540000000 {
5539                                                 opp-hz = /bits/ 64 <540000000>;
5540                                                 required-opps = <&rpmhpd_opp_svs_l1>;
5541                                         };
5542
5543                                         opp-810000000 {
5544                                                 opp-hz = /bits/ 64 <810000000>;
5545                                                 required-opps = <&rpmhpd_opp_nom>;
5546                                         };
5547                                 };
5548                         };
5549                 };
5550
5551                 mdss1_dp2_phy: phy@220c2a00 {
5552                         compatible = "qcom,sc8280xp-dp-phy";
5553                         reg = <0 0x220c2a00 0 0x19c>,
5554                               <0 0x220c2200 0 0xec>,
5555                               <0 0x220c2600 0 0xec>,
5556                               <0 0x220c2000 0 0x1c8>;
5557
5558                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>,
5559                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5560                         clock-names = "aux", "cfg_ahb";
5561                         power-domains = <&rpmhpd SC8280XP_MX>;
5562
5563                         #clock-cells = <1>;
5564                         #phy-cells = <0>;
5565
5566                         status = "disabled";
5567                 };
5568
5569                 mdss1_dp3_phy: phy@220c5a00 {
5570                         compatible = "qcom,sc8280xp-dp-phy";
5571                         reg = <0 0x220c5a00 0 0x19c>,
5572                               <0 0x220c5200 0 0xec>,
5573                               <0 0x220c5600 0 0xec>,
5574                               <0 0x220c5000 0 0x1c8>;
5575
5576                         clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>,
5577                                  <&dispcc1 DISP_CC_MDSS_AHB_CLK>;
5578                         clock-names = "aux", "cfg_ahb";
5579                         power-domains = <&rpmhpd SC8280XP_MX>;
5580
5581                         #clock-cells = <1>;
5582                         #phy-cells = <0>;
5583
5584                         status = "disabled";
5585                 };
5586
5587                 dispcc1: clock-controller@22100000 {
5588                         compatible = "qcom,sc8280xp-dispcc1";
5589                         reg = <0 0x22100000 0 0x20000>;
5590
5591                         clocks = <&gcc GCC_DISP_AHB_CLK>,
5592                                  <&rpmhcc RPMH_CXO_CLK>,
5593                                  <0>,
5594                                  <&mdss1_dp0_phy 0>,
5595                                  <&mdss1_dp0_phy 1>,
5596                                  <&mdss1_dp1_phy 0>,
5597                                  <&mdss1_dp1_phy 1>,
5598                                  <&mdss1_dp2_phy 0>,
5599                                  <&mdss1_dp2_phy 1>,
5600                                  <&mdss1_dp3_phy 0>,
5601                                  <&mdss1_dp3_phy 1>,
5602                                  <0>,
5603                                  <0>,
5604                                  <0>,
5605                                  <0>;
5606                         power-domains = <&rpmhpd SC8280XP_MMCX>;
5607
5608                         #clock-cells = <1>;
5609                         #power-domain-cells = <1>;
5610                         #reset-cells = <1>;
5611
5612                         status = "disabled";
5613                 };
5614
5615                 ethernet1: ethernet@23000000 {
5616                         compatible = "qcom,sc8280xp-ethqos";
5617                         reg = <0x0 0x23000000 0x0 0x10000>,
5618                               <0x0 0x23016000 0x0 0x100>;
5619                         reg-names = "stmmaceth", "rgmii";
5620
5621                         clocks = <&gcc GCC_EMAC1_AXI_CLK>,
5622                                  <&gcc GCC_EMAC1_SLV_AHB_CLK>,
5623                                  <&gcc GCC_EMAC1_PTP_CLK>,
5624                                  <&gcc GCC_EMAC1_RGMII_CLK>;
5625                         clock-names = "stmmaceth",
5626                                       "pclk",
5627                                       "ptp_ref",
5628                                       "rgmii";
5629
5630                         interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
5631                                      <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>;
5632                         interrupt-names = "macirq", "eth_lpi";
5633
5634                         iommus = <&apps_smmu 0x40 0xf>;
5635                         power-domains = <&gcc EMAC_1_GDSC>;
5636
5637                         snps,tso;
5638                         snps,pbl = <32>;
5639                         rx-fifo-depth = <4096>;
5640                         tx-fifo-depth = <4096>;
5641
5642                         status = "disabled";
5643                 };
5644         };
5645
5646         sound: sound {
5647         };
5648
5649         thermal-zones {
5650                 cpu0-thermal {
5651                         polling-delay-passive = <250>;
5652                         polling-delay = <1000>;
5653
5654                         thermal-sensors = <&tsens0 1>;
5655
5656                         trips {
5657                                 cpu-crit {
5658                                         temperature = <110000>;
5659                                         hysteresis = <1000>;
5660                                         type = "critical";
5661                                 };
5662                         };
5663                 };
5664
5665                 cpu1-thermal {
5666                         polling-delay-passive = <250>;
5667                         polling-delay = <1000>;
5668
5669                         thermal-sensors = <&tsens0 2>;
5670
5671                         trips {
5672                                 cpu-crit {
5673                                         temperature = <110000>;
5674                                         hysteresis = <1000>;
5675                                         type = "critical";
5676                                 };
5677                         };
5678                 };
5679
5680                 cpu2-thermal {
5681                         polling-delay-passive = <250>;
5682                         polling-delay = <1000>;
5683
5684                         thermal-sensors = <&tsens0 3>;
5685
5686                         trips {
5687                                 cpu-crit {
5688                                         temperature = <110000>;
5689                                         hysteresis = <1000>;
5690                                         type = "critical";
5691                                 };
5692                         };
5693                 };
5694
5695                 cpu3-thermal {
5696                         polling-delay-passive = <250>;
5697                         polling-delay = <1000>;
5698
5699                         thermal-sensors = <&tsens0 4>;
5700
5701                         trips {
5702                                 cpu-crit {
5703                                         temperature = <110000>;
5704                                         hysteresis = <1000>;
5705                                         type = "critical";
5706                                 };
5707                         };
5708                 };
5709
5710                 cpu4-thermal {
5711                         polling-delay-passive = <250>;
5712                         polling-delay = <1000>;
5713
5714                         thermal-sensors = <&tsens0 5>;
5715
5716                         trips {
5717                                 cpu-crit {
5718                                         temperature = <110000>;
5719                                         hysteresis = <1000>;
5720                                         type = "critical";
5721                                 };
5722                         };
5723                 };
5724
5725                 cpu5-thermal {
5726                         polling-delay-passive = <250>;
5727                         polling-delay = <1000>;
5728
5729                         thermal-sensors = <&tsens0 6>;
5730
5731                         trips {
5732                                 cpu-crit {
5733                                         temperature = <110000>;
5734                                         hysteresis = <1000>;
5735                                         type = "critical";
5736                                 };
5737                         };
5738                 };
5739
5740                 cpu6-thermal {
5741                         polling-delay-passive = <250>;
5742                         polling-delay = <1000>;
5743
5744                         thermal-sensors = <&tsens0 7>;
5745
5746                         trips {
5747                                 cpu-crit {
5748                                         temperature = <110000>;
5749                                         hysteresis = <1000>;
5750                                         type = "critical";
5751                                 };
5752                         };
5753                 };
5754
5755                 cpu7-thermal {
5756                         polling-delay-passive = <250>;
5757                         polling-delay = <1000>;
5758
5759                         thermal-sensors = <&tsens0 8>;
5760
5761                         trips {
5762                                 cpu-crit {
5763                                         temperature = <110000>;
5764                                         hysteresis = <1000>;
5765                                         type = "critical";
5766                                 };
5767                         };
5768                 };
5769
5770                 cluster0-thermal {
5771                         polling-delay-passive = <250>;
5772                         polling-delay = <1000>;
5773
5774                         thermal-sensors = <&tsens0 9>;
5775
5776                         trips {
5777                                 cpu-crit {
5778                                         temperature = <110000>;
5779                                         hysteresis = <1000>;
5780                                         type = "critical";
5781                                 };
5782                         };
5783                 };
5784
5785                 gpu-thermal {
5786                         polling-delay-passive = <0>;
5787                         polling-delay = <0>;
5788
5789                         thermal-sensors = <&tsens2 2>;
5790
5791                         trips {
5792                                 gpu-crit {
5793                                         temperature = <110000>;
5794                                         hysteresis = <1000>;
5795                                         type = "critical";
5796                                 };
5797                         };
5798                 };
5799
5800                 mem-thermal {
5801                         polling-delay-passive = <250>;
5802                         polling-delay = <1000>;
5803
5804                         thermal-sensors = <&tsens1 15>;
5805
5806                         trips {
5807                                 trip-point0 {
5808                                         temperature = <90000>;
5809                                         hysteresis = <2000>;
5810                                         type = "hot";
5811                                 };
5812                         };
5813                 };
5814         };
5815
5816         timer {
5817                 compatible = "arm,armv8-timer";
5818                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5819                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5820                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
5821                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
5822         };
5823 };