1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
6 #include <dt-bindings/clock/qcom,qdu1000-gcc.h>
7 #include <dt-bindings/clock/qcom,rpmh.h>
8 #include <dt-bindings/dma/qcom-gpi.h>
9 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 interrupt-parent = <&intc>;
28 compatible = "arm,cortex-a55";
30 clocks = <&cpufreq_hw 0>;
31 enable-method = "psci";
32 power-domains = <&CPU_PD0>;
33 power-domain-names = "psci";
34 qcom,freq-domains = <&cpufreq_hw 0>;
35 next-level-cache = <&L2_0>;
40 next-level-cache = <&L3_0>;
51 compatible = "arm,cortex-a55";
53 clocks = <&cpufreq_hw 0>;
54 enable-method = "psci";
55 power-domains = <&CPU_PD1>;
56 power-domain-names = "psci";
57 qcom,freq-domains = <&cpufreq_hw 0>;
58 next-level-cache = <&L2_100>;
63 next-level-cache = <&L3_0>;
69 compatible = "arm,cortex-a55";
71 clocks = <&cpufreq_hw 0>;
72 enable-method = "psci";
73 power-domains = <&CPU_PD2>;
74 power-domain-names = "psci";
75 qcom,freq-domains = <&cpufreq_hw 0>;
76 next-level-cache = <&L2_200>;
81 next-level-cache = <&L3_0>;
87 compatible = "arm,cortex-a55";
89 clocks = <&cpufreq_hw 0>;
90 enable-method = "psci";
91 power-domains = <&CPU_PD3>;
92 power-domain-names = "psci";
93 qcom,freq-domains = <&cpufreq_hw 0>;
94 next-level-cache = <&L2_300>;
99 next-level-cache = <&L3_0>;
125 entry-method = "psci";
127 CPU_OFF: cpu-sleep-0 {
128 compatible = "arm,idle-state";
129 entry-latency-us = <274>;
130 exit-latency-us = <480>;
131 min-residency-us = <3934>;
132 arm,psci-suspend-param = <0x40000004>;
138 CLUSTER_SLEEP_0: cluster-sleep-0 {
139 compatible = "domain-idle-state";
140 entry-latency-us = <584>;
141 exit-latency-us = <2332>;
142 min-residency-us = <6118>;
143 arm,psci-suspend-param = <0x41000044>;
146 CLUSTER_SLEEP_1: cluster-sleep-1 {
147 compatible = "domain-idle-state";
148 entry-latency-us = <2893>;
149 exit-latency-us = <4023>;
150 min-residency-us = <9987>;
151 arm,psci-suspend-param = <0x41003344>;
157 compatible = "qcom,scm-qdu1000", "qcom,scm";
161 mc_virt: interconnect-0 {
162 compatible = "qcom,qdu1000-mc-virt";
163 qcom,bcm-voters = <&apps_bcm_voter>;
164 #interconnect-cells = <2>;
167 clk_virt: interconnect-1 {
168 compatible = "qcom,qdu1000-clk-virt";
169 qcom,bcm-voters = <&apps_bcm_voter>;
170 #interconnect-cells = <2>;
174 device_type = "memory";
175 /* We expect the bootloader to fill in the size */
176 reg = <0x0 0x80000000 0x0 0x0>;
180 compatible = "arm,armv8-pmuv3";
181 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
185 compatible = "arm,psci-1.0";
188 CPU_PD0: power-domain-cpu0 {
189 #power-domain-cells = <0>;
190 power-domains = <&CLUSTER_PD>;
191 domain-idle-states = <&CPU_OFF>;
194 CPU_PD1: power-domain-cpu1 {
195 #power-domain-cells = <0>;
196 power-domains = <&CLUSTER_PD>;
197 domain-idle-states = <&CPU_OFF>;
200 CPU_PD2: power-domain-cpu2 {
201 #power-domain-cells = <0>;
202 power-domains = <&CLUSTER_PD>;
203 domain-idle-states = <&CPU_OFF>;
206 CPU_PD3: power-domain-cpu3 {
207 #power-domain-cells = <0>;
208 power-domains = <&CLUSTER_PD>;
209 domain-idle-states = <&CPU_OFF>;
212 CLUSTER_PD: power-domain-cluster {
213 #power-domain-cells = <0>;
214 domain-idle-states = <&CLUSTER_SLEEP_0 &CLUSTER_SLEEP_1>;
218 reserved_memory: reserved-memory {
219 #address-cells = <2>;
223 hyp_mem: hyp@80000000 {
224 reg = <0x0 0x80000000 0x0 0x600000>;
228 xbl_dt_log_mem: xbl-dt-log@80600000 {
229 reg = <0x0 0x80600000 0x0 0x40000>;
233 xbl_ramdump_mem: xbl-ramdump@80640000 {
234 reg = <0x0 0x80640000 0x0 0x1c0000>;
238 aop_image_mem: aop-image@80800000 {
239 reg = <0x0 0x80800000 0x0 0x60000>;
243 aop_cmd_db_mem: aop-cmd-db@80860000 {
244 compatible = "qcom,cmd-db";
245 reg = <0x0 0x80860000 0x0 0x20000>;
249 aop_config_mem: aop-config@80880000 {
250 reg = <0x0 0x80880000 0x0 0x20000>;
254 tme_crash_dump_mem: tme-crash-dump@808a0000 {
255 reg = <0x0 0x808a0000 0x0 0x40000>;
259 tme_log_mem: tme-log@808e0000 {
260 reg = <0x0 0x808e0000 0x0 0x4000>;
264 uefi_log_mem: uefi-log@808e4000 {
265 reg = <0x0 0x808e4000 0x0 0x10000>;
269 smem_mem: smem@80900000 {
270 compatible = "qcom,smem";
271 reg = <0x0 0x80900000 0x0 0x200000>;
273 hwlocks = <&tcsr_mutex 3>;
276 cpucp_fw_mem: cpucp-fw@80b00000 {
277 reg = <0x0 0x80b00000 0x0 0x100000>;
281 xbl_sc_mem: memory@80c00000 {
282 reg = <0x0 0x80c00000 0x0 0x40000>;
286 tz_stat_mem: tz-stat@81d00000 {
287 reg = <0x0 0x81d00000 0x0 0x100000>;
291 tags_mem: tags@81e00000 {
292 reg = <0x0 0x81e00000 0x0 0x500000>;
296 qtee_mem: qtee@82300000 {
297 reg = <0x0 0x82300000 0x0 0x500000>;
301 ta_mem: ta@82800000 {
302 reg = <0x0 0x82800000 0x0 0xa00000>;
306 fs1_mem: fs1@83200000 {
307 reg = <0x0 0x83200000 0x0 0x400000>;
311 fs2_mem: fs2@83600000 {
312 reg = <0x0 0x83600000 0x0 0x400000>;
316 fs3_mem: fs3@83a00000 {
317 reg = <0x0 0x83a00000 0x0 0x400000>;
321 /* Linux kernel image is loaded at 0x83e00000 */
323 ipa_fw_mem: ipa-fw@8be00000 {
324 reg = <0x0 0x8be00000 0x0 0x10000>;
328 ipa_gsi_mem: ipa-gsi@8be10000 {
329 reg = <0x0 0x8be10000 0x0 0x14000>;
333 mpss_mem: mpss@8c000000 {
334 reg = <0x0 0x8c000000 0x0 0x12c00000>;
338 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 {
339 reg = <0x0 0x9ec00000 0x0 0x80000>;
343 tenx_mem: tenx@a0000000 {
344 reg = <0x0 0xa0000000 0x0 0x19600000>;
348 oem_tenx_mem: oem-tenx@b9600000 {
349 reg = <0x0 0xb9600000 0x0 0x6a00000>;
353 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 {
354 reg = <0x0 0xc0000000 0x0 0x3200000>;
358 ipa_buffer_mem: ipa-buffer@c3200000 {
359 reg = <0x0 0xc3200000 0x0 0x12c00000>;
365 compatible = "simple-bus";
366 #address-cells = <2>;
368 ranges = <0 0 0 0 0x10 0>;
369 dma-ranges = <0 0 0 0 0x10 0>;
371 gcc: clock-controller@80000 {
372 compatible = "qcom,qdu1000-gcc";
373 reg = <0x0 0x80000 0x0 0x1f4200>;
374 clocks = <&rpmhcc RPMH_CXO_CLK>,
381 #power-domain-cells = <1>;
384 gpi_dma0: dma-controller@900000 {
385 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
386 reg = <0x0 0x900000 0x0 0x60000>;
387 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
396 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
397 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
400 dma-channel-mask = <0x3f>;
401 iommus = <&apps_smmu 0xf6 0x0>;
405 qupv3_id_0: geniqup@9c0000 {
406 compatible = "qcom,geni-se-qup";
407 reg = <0x0 0x9c0000 0x0 0x2000>;
408 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
409 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
410 clock-names = "m-ahb", "s-ahb";
411 iommus = <&apps_smmu 0xe3 0x0>;
412 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
413 &clk_virt SLAVE_QUP_CORE_0 0>;
414 interconnect-names = "qup-core";
416 #address-cells = <2>;
421 uart0: serial@980000 {
422 compatible = "qcom,geni-uart";
423 reg = <0x0 0x980000 0x0 0x4000>;
424 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
426 pinctrl-0 = <&qup_uart0_default>;
427 pinctrl-names = "default";
428 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
433 compatible = "qcom,geni-i2c";
434 reg = <0x0 0x984000 0x0 0x4000>;
435 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
437 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
438 pinctrl-0 = <&qup_i2c1_data_clk>;
439 pinctrl-names = "default";
440 #address-cells = <1>;
446 compatible = "qcom,geni-spi";
447 reg = <0x0 0x984000 0x0 0x4000>;
448 #address-cells = <1>;
450 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
453 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
454 pinctrl-names = "default";
459 compatible = "qcom,geni-i2c";
460 reg = <0x0 0x988000 0x0 0x4000>;
461 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
463 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
464 pinctrl-0 = <&qup_i2c2_data_clk>;
465 pinctrl-names = "default";
466 #address-cells = <1>;
472 compatible = "qcom,geni-spi";
473 reg = <0x0 0x988000 0x0 0x4000>;
474 #address-cells = <1>;
476 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
479 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
480 pinctrl-names = "default";
485 compatible = "qcom,geni-i2c";
486 reg = <0x0 0x98c000 0x0 0x4000>;
487 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
489 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
490 pinctrl-0 = <&qup_i2c3_data_clk>;
491 pinctrl-names = "default";
492 #address-cells = <1>;
498 compatible = "qcom,geni-spi";
499 reg = <0x0 0x98c000 0x0 0x4000>;
500 #address-cells = <1>;
502 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
505 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
506 pinctrl-names = "default";
511 compatible = "qcom,geni-i2c";
512 reg = <0x0 0x990000 0x0 0x4000>;
513 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
515 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
516 pinctrl-0 = <&qup_i2c4_data_clk>;
517 pinctrl-names = "default";
518 #address-cells = <1>;
524 compatible = "qcom,geni-spi";
525 reg = <0x0 0x990000 0x0 0x4000>;
526 #address-cells = <1>;
528 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
531 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
532 pinctrl-names = "default";
537 compatible = "qcom,geni-i2c";
538 reg = <0x0 0x994000 0x0 0x4000>;
539 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
541 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
542 pinctrl-0 = <&qup_i2c5_data_clk>;
543 pinctrl-names = "default";
544 #address-cells = <1>;
550 compatible = "qcom,geni-spi";
551 reg = <0x0 0x994000 0x0 0x4000>;
552 #address-cells = <1>;
554 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
557 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
558 pinctrl-names = "default";
563 compatible = "qcom,geni-i2c";
564 reg = <0x0 0x998000 0x0 0x4000>;
565 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
567 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
568 pinctrl-0 = <&qup_i2c6_data_clk>;
569 pinctrl-names = "default";
570 #address-cells = <1>;
576 compatible = "qcom,geni-spi";
577 reg = <0x0 0x998000 0x0 0x4000>;
578 #address-cells = <1>;
580 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
583 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
584 pinctrl-names = "default";
588 uart7: serial@99c000 {
589 compatible = "qcom,geni-debug-uart";
590 reg = <0x0 0x99c000 0x0 0x4000>;
591 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
593 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
594 pinctrl-names = "default";
595 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
600 gpi_dma1: dma-controller@a00000 {
601 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma";
602 reg = <0x0 0xa00000 0x0 0x60000>;
603 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
604 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
605 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
607 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
608 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
616 dma-channel-mask = <0x3f>;
617 iommus = <&apps_smmu 0x116 0x0>;
621 qupv3_id_1: geniqup@ac0000 {
622 compatible = "qcom,geni-se-qup";
623 reg = <0x0 0xac0000 0x0 0x2000>;
624 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
625 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
626 clock-names = "m-ahb", "s-ahb";
627 iommus = <&apps_smmu 0x103 0x0>;
628 #address-cells = <2>;
633 uart8: serial@a80000 {
634 compatible = "qcom,geni-uart";
635 reg = <0x0 0xa80000 0x0 0x4000>;
636 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
638 pinctrl-0 = <&qup_uart8_default>;
639 pinctrl-names = "default";
640 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
641 #address-cells = <1>;
647 compatible = "qcom,geni-i2c";
648 reg = <0x0 0xa84000 0x0 0x4000>;
649 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
651 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
652 pinctrl-0 = <&qup_i2c9_data_clk>;
653 pinctrl-names = "default";
654 #address-cells = <1>;
660 compatible = "qcom,geni-spi";
661 reg = <0x0 0xa84000 0x0 0x4000>;
662 #address-cells = <1>;
664 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
667 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
668 pinctrl-names = "default";
673 compatible = "qcom,geni-i2c";
674 reg = <0x0 0xa88000 0x0 0x4000>;
675 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
677 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
678 pinctrl-0 = <&qup_i2c10_data_clk>;
679 pinctrl-names = "default";
680 #address-cells = <1>;
686 compatible = "qcom,geni-spi";
687 reg = <0x0 0xa88000 0x0 0x4000>;
688 #address-cells = <1>;
690 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
693 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
694 pinctrl-names = "default";
699 compatible = "qcom,geni-i2c";
700 reg = <0x0 0xa8c000 0x0 0x4000>;
701 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
703 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
704 pinctrl-0 = <&qup_i2c11_data_clk>;
705 pinctrl-names = "default";
706 #address-cells = <1>;
712 compatible = "qcom,geni-spi";
713 reg = <0x0 0xa8c000 0x0 0x4000>;
714 #address-cells = <1>;
716 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
719 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
720 pinctrl-names = "default";
725 compatible = "qcom,geni-i2c";
726 reg = <0x0 0xa90000 0x0 0x4000>;
727 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
729 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
730 pinctrl-0 = <&qup_i2c12_data_clk>;
731 pinctrl-names = "default";
732 #address-cells = <1>;
738 compatible = "qcom,geni-spi";
739 reg = <0x0 0xa90000 0x0 0x4000>;
740 #address-cells = <1>;
742 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
745 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
746 pinctrl-names = "default";
751 compatible = "qcom,geni-i2c";
752 reg = <0x0 0xa94000 0x0 0x4000>;
753 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
755 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
756 pinctrl-0 = <&qup_i2c13_data_clk>;
757 pinctrl-names = "default";
758 #address-cells = <1>;
763 uart13: serial@a94000 {
764 compatible = "qcom,geni-uart";
765 reg = <0x0 0xa94000 0x0 0x4000>;
766 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
768 pinctrl-0 = <&qup_uart13_default>;
769 pinctrl-names = "default";
770 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
771 #address-cells = <1>;
777 compatible = "qcom,geni-spi";
778 reg = <0x0 0xa94000 0x0 0x4000>;
779 #address-cells = <1>;
781 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
784 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
785 pinctrl-names = "default";
790 compatible = "qcom,geni-i2c";
791 reg = <0x0 0xa98000 0x0 0x4000>;
792 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
794 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
795 pinctrl-0 = <&qup_i2c14_data_clk>;
796 pinctrl-names = "default";
797 #address-cells = <1>;
803 compatible = "qcom,geni-spi";
804 reg = <0x0 0xa98000 0x0 0x4000>;
805 #address-cells = <1>;
807 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
810 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
811 pinctrl-names = "default";
816 compatible = "qcom,geni-i2c";
817 reg = <0x0 0xa9c000 0x0 0x4000>;
818 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
820 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
821 pinctrl-0 = <&qup_i2c15_data_clk>;
822 pinctrl-names = "default";
823 #address-cells = <1>;
829 compatible = "qcom,geni-spi";
830 reg = <0x0 0xa9c000 0x0 0x4000>;
831 #address-cells = <1>;
833 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
836 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
837 pinctrl-names = "default";
842 system_noc: interconnect@1640000 {
843 compatible = "qcom,qdu1000-system-noc";
844 reg = <0x0 0x1640000 0x0 0x45080>;
845 qcom,bcm-voters = <&apps_bcm_voter>;
846 #interconnect-cells = <2>;
849 tcsr_mutex: hwlock@1f40000 {
850 compatible = "qcom,tcsr-mutex";
851 reg = <0x0 0x1f40000 0x0 0x20000>;
855 pdc: interrupt-controller@b220000 {
856 compatible = "qcom,qdu1000-pdc", "qcom,pdc";
857 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
858 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
859 <94 609 31>, <125 63 1>;
860 #interrupt-cells = <2>;
861 interrupt-parent = <&intc>;
862 interrupt-controller;
865 spmi_bus: spmi@c400000 {
866 compatible = "qcom,spmi-pmic-arb";
867 reg = <0x0 0xc400000 0x0 0x3000>,
868 <0x0 0xc500000 0x0 0x400000>,
869 <0x0 0xc440000 0x0 0x80000>,
870 <0x0 0xc4c0000 0x0 0x10000>,
871 <0x0 0xc42d000 0x0 0x4000>;
872 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
873 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
874 interrupt-names = "periph_irq";
877 #address-cells = <2>;
879 interrupt-controller;
880 #interrupt-cells = <4>;
883 tlmm: pinctrl@f000000 {
884 compatible = "qcom,qdu1000-tlmm";
885 reg = <0x0 0xf000000 0x0 0x1000000>;
886 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
889 interrupt-controller;
890 #interrupt-cells = <2>;
891 gpio-ranges = <&tlmm 0 0 151>;
892 wakeup-parent = <&pdc>;
894 qup_uart0_default: qup-uart0-default-state {
895 pins = "gpio6", "gpio7", "gpio8", "gpio9";
899 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
900 pins = "gpio10", "gpio11";
904 qup_spi1_data_clk: qup-spi1-data-clk-state {
905 pins = "gpio10", "gpio11", "gpio12";
909 qup_spi1_cs: qup-spi1-cs-state {
914 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
915 pins = "gpio12", "gpio13";
919 qup_spi2_data_clk: qup-spi2-data-clk-state {
920 pins = "gpio12", "gpio13", "gpio10";
924 qup_spi2_cs: qup-spi2-cs-state {
929 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
930 pins = "gpio14", "gpio15";
934 qup_spi3_data_clk: qup-spi3-data-clk-state {
935 pins = "gpio14", "gpio15", "gpio16";
939 qup_spi3_cs: qup-spi3-cs-state {
944 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
945 pins = "gpio16", "gpio17";
949 qup_spi4_data_clk: qup-spi4-data-clk-state {
950 pins = "gpio16", "gpio17", "gpio14";
954 qup_spi4_cs: qup-spi4-cs-state {
959 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
960 pins = "gpio130", "gpio131";
964 qup_spi5_data_clk: qup-spi5-data-clk-state {
965 pins = "gpio130", "gpio131", "gpio132";
969 qup_spi5_cs: qup-spi5-cs-state {
974 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
975 pins = "gpio132", "gpio133";
979 qup_spi6_data_clk: qup-spi6-data-clk-state {
980 pins = "gpio132", "gpio133", "gpio130";
984 qup_spi6_cs: qup-spi6-cs-state {
989 qup_uart7_rx: qup-uart7-rx-state {
994 qup_uart7_tx: qup-uart7-tx-state {
999 qup_uart8_default: qup-uart8-default-state {
1000 pins = "gpio18", "gpio19", "gpio20", "gpio21";
1004 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
1005 pins = "gpio22", "gpio23";
1009 qup_spi9_data_clk: qup-spi9-data-clk-state {
1010 pins = "gpio22", "gpio23", "gpio24";
1014 qup_spi9_cs: qup-spi9-cs-state {
1019 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
1020 pins = "gpio24", "gpio25";
1024 qup_spi10_data_clk: qup-spi10-data-clk-state {
1025 pins = "gpio24", "gpio25", "gpio22";
1029 qup_spi10_cs: qup-spi10-cs-state {
1034 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
1035 pins = "gpio26", "gpio27";
1039 qup_spi11_data_clk: qup-spi11-data-clk-state {
1040 pins = "gpio26", "gpio27", "gpio28";
1044 qup_spi11_cs: qup-spi11-cs-state {
1049 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
1050 pins = "gpio28", "gpio29";
1054 qup_spi12_data_clk: qup-spi12-data-clk-state {
1055 pins = "gpio28", "gpio29", "gpio26";
1059 qup_spi12_cs: qup-spi12-cs-state {
1064 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
1065 pins = "gpio30", "gpio31";
1069 qup_spi13_data_clk: qup-spi13-data-clk-state {
1070 pins = "gpio30", "gpio31", "gpio32";
1074 qup_spi13_cs: qup-spi13-cs-state {
1079 qup_uart13_default: qup-uart13-default-state {
1080 pins = "gpio30", "gpio31", "gpio32", "gpio33";
1084 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
1085 pins = "gpio34", "gpio35";
1089 qup_spi14_data_clk: qup-spi14-data-clk-state {
1090 pins = "gpio34", "gpio35", "gpio36";
1094 qup_spi14_cs: qup-spi14-cs-state {
1095 pins = "gpio37", "gpio38";
1099 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
1100 pins = "gpio40", "gpio41";
1104 qup_spi15_data_clk: qup-spi15-data-clk-state {
1105 pins = "gpio40", "gpio41", "gpio30";
1109 qup_spi15_cs: qup-spi15-cs-state {
1115 apps_smmu: iommu@15000000 {
1116 compatible = "qcom,qdu1000-smmu-500", "arm,mmu-500";
1117 reg = <0x0 0x15000000 0x0 0x100000>;
1119 #global-interrupts = <2>;
1120 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1121 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1123 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1124 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1125 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1126 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
1127 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
1128 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1134 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1138 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1139 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1140 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1141 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1142 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1143 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1146 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
1171 intc: interrupt-controller@17200000 {
1172 compatible = "arm,gic-v3";
1173 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1174 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1175 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1176 #interrupt-cells = <3>;
1177 interrupt-controller;
1178 #redistributor-regions = <1>;
1179 redistributor-stride = <0x0 0x20000>;
1183 compatible = "arm,armv7-timer-mem";
1184 reg = <0x0 0x17420000 0x0 0x1000>;
1185 #address-cells = <1>;
1187 ranges = <0x0 0x0 0x0 0x20000000>;
1190 reg = <0x17421000 0x1000>,
1191 <0x17422000 0x1000>;
1192 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1198 reg = <0x17423000 0x1000>;
1199 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1201 status = "disabled";
1205 reg = <0x17425000 0x1000>,
1206 <0x17426000 0x1000>;
1207 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1209 status = "disabled";
1213 reg = <0x17427000 0x1000>;
1214 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1216 status = "disabled";
1220 reg = <0x17429000 0x1000>;
1221 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1223 status = "disabled";
1227 reg = <0x1742b000 0x1000>;
1228 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1230 status = "disabled";
1234 reg = <0x1742d000 0x1000>;
1235 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1237 status = "disabled";
1241 apps_rsc: rsc@17a00000 {
1242 compatible = "qcom,rpmh-rsc";
1243 reg = <0x0 0x17a00000 0x0 0x10000>,
1244 <0x0 0x17a10000 0x0 0x10000>,
1245 <0x0 0x17a20000 0x0 0x10000>;
1246 reg-names = "drv-0", "drv-1", "drv-2";
1247 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1250 qcom,tcs-offset = <0xd00>;
1252 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
1253 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1256 apps_bcm_voter: bcm-voter {
1257 compatible = "qcom,bcm-voter";
1260 rpmhcc: clock-controller {
1261 compatible = "qcom,qdu1000-rpmh-clk";
1262 clocks = <&xo_board>;
1267 rpmhpd: power-controller {
1268 compatible = "qcom,qdu1000-rpmhpd";
1269 #power-domain-cells = <1>;
1270 operating-points-v2 = <&rpmhpd_opp_table>;
1272 rpmhpd_opp_table: opp-table {
1273 compatible = "operating-points-v2";
1275 rpmhpd_opp_ret: opp1 {
1276 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1279 rpmhpd_opp_min_svs: opp2 {
1280 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1283 rpmhpd_opp_low_svs: opp3 {
1284 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1287 rpmhpd_opp_svs: opp4 {
1288 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1291 rpmhpd_opp_svs_l1: opp5 {
1292 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1295 rpmhpd_opp_nom: opp6 {
1296 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1299 rpmhpd_opp_nom_l1: opp7 {
1300 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1303 rpmhpd_opp_nom_l2: opp8 {
1304 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1307 rpmhpd_opp_turbo: opp9 {
1308 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1311 rpmhpd_opp_turbo_l1: opp10 {
1312 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1318 cpufreq_hw: cpufreq@17d90000 {
1319 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss";
1320 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1321 reg-names = "freq-domain0", "freq-domain1";
1322 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
1323 clock-names = "xo", "alternate";
1324 #freq-domain-cells = <1>;
1328 gem_noc: interconnect@19100000 {
1329 compatible = "qcom,qdu1000-gem-noc";
1330 reg = <0x0 0x19100000 0x0 0xB8080>;
1331 qcom,bcm-voters = <&apps_bcm_voter>;
1332 #interconnect-cells = <2>;
1335 system-cache-controller@19200000 {
1336 compatible = "qcom,qdu1000-llcc";
1337 reg = <0 0x19200000 0 0xd80000>,
1338 <0 0x1a200000 0 0x80000>,
1339 <0 0x221c8128 0 0x4>;
1340 reg-names = "llcc_base",
1341 "llcc_broadcast_base",
1342 "multi_channel_register";
1343 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1344 multi-ch-bit-off = <24 2>;
1349 compatible = "arm,armv8-timer";
1350 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1351 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1352 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1353 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1354 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;