1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
4 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/thermal/thermal.h>
11 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
22 clock-frequency = <32768>;
26 compatible = "fixed-clock";
28 clock-frequency = <19200000>;
29 clock-output-names = "xo";
39 compatible = "arm,cortex-a53";
41 enable-method = "psci";
42 capacity-dmips-mhz = <1024>;
43 next-level-cache = <&L2_0>;
56 compatible = "arm,cortex-a53";
58 enable-method = "psci";
59 capacity-dmips-mhz = <1024>;
60 next-level-cache = <&L2_0>;
73 compatible = "arm,cortex-a53";
75 enable-method = "psci";
76 capacity-dmips-mhz = <1024>;
77 next-level-cache = <&L2_0>;
90 compatible = "arm,cortex-a53";
92 enable-method = "psci";
93 capacity-dmips-mhz = <1024>;
94 next-level-cache = <&L2_0>;
101 compatible = "cache";
107 compatible = "arm,cortex-a53";
109 enable-method = "psci";
110 capacity-dmips-mhz = <1024>;
111 next-level-cache = <&L2_1>;
112 #cooling-cells = <2>;
115 compatible = "cache";
118 compatible = "cache";
124 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 capacity-dmips-mhz = <1024>;
128 next-level-cache = <&L2_1>;
129 #cooling-cells = <2>;
132 compatible = "cache";
135 compatible = "cache";
141 compatible = "arm,cortex-a53";
143 enable-method = "psci";
144 capacity-dmips-mhz = <1024>;
145 next-level-cache = <&L2_1>;
146 #cooling-cells = <2>;
149 compatible = "cache";
152 compatible = "cache";
158 compatible = "arm,cortex-a53";
160 enable-method = "psci";
161 capacity-dmips-mhz = <1024>;
162 next-level-cache = <&L2_1>;
163 #cooling-cells = <2>;
166 compatible = "cache";
169 compatible = "cache";
206 compatible = "cache";
211 compatible = "cache";
218 compatible = "qcom,scm-msm8953", "qcom,scm";
219 clocks = <&gcc GCC_CRYPTO_CLK>,
220 <&gcc GCC_CRYPTO_AXI_CLK>,
221 <&gcc GCC_CRYPTO_AHB_CLK>;
222 clock-names = "core", "bus", "iface";
228 device_type = "memory";
229 /* We expect the bootloader to fill in the reg */
234 compatible = "arm,cortex-a53-pmu";
235 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
239 compatible = "arm,psci-1.0";
244 #address-cells = <2>;
248 zap_shader_region: memory@81800000 {
249 compatible = "shared-dma-pool";
250 reg = <0x0 0x81800000 0x0 0x2000>;
255 reg = <0x0 0x85b00000 0x0 0x800000>;
259 smem_mem: memory@86300000 {
260 compatible = "qcom,smem";
261 reg = <0x0 0x86300000 0x0 0x100000>;
262 qcom,rpm-msg-ram = <&rpm_msg_ram>;
263 hwlocks = <&tcsr_mutex 3>;
268 reg = <0x0 0x86400000 0x0 0x400000>;
272 mpss_mem: memory@86c00000 {
273 reg = <0x0 0x86c00000 0x0 0x6a00000>;
277 adsp_fw_mem: memory@8d600000 {
278 reg = <0x0 0x8d600000 0x0 0x1100000>;
282 wcnss_fw_mem: memory@8e700000 {
283 reg = <0x0 0x8e700000 0x0 0x700000>;
288 reg = <0 0x90000000 0 0x1000>;
293 reg = <0x0 0x90001000 0x0 0x13ff000>;
297 venus_mem: memory@91400000 {
298 reg = <0x0 0x91400000 0x0 0x700000>;
302 mba_mem: memory@92000000 {
303 reg = <0x0 0x92000000 0x0 0x100000>;
308 compatible = "qcom,rmtfs-mem";
309 reg = <0x0 0xf2d00000 0x0 0x180000>;
312 qcom,client-id = <1>;
317 compatible = "qcom,smd";
320 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
321 qcom,ipc = <&apcs 8 0>;
322 qcom,smd-edge = <15>;
324 rpm_requests: rpm-requests {
325 compatible = "qcom,rpm-msm8953";
326 qcom,smd-channels = "rpm_requests";
329 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
330 clocks = <&xo_board>;
335 rpmpd: power-controller {
336 compatible = "qcom,msm8953-rpmpd";
337 #power-domain-cells = <1>;
338 operating-points-v2 = <&rpmpd_opp_table>;
340 clocks = <&xo_board>;
343 rpmpd_opp_table: opp-table {
344 compatible = "operating-points-v2";
346 rpmpd_opp_ret: opp1 {
347 opp-level = <RPM_SMD_LEVEL_RETENTION>;
350 rpmpd_opp_ret_plus: opp2 {
351 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
354 rpmpd_opp_min_svs: opp3 {
355 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
358 rpmpd_opp_low_svs: opp4 {
359 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
362 rpmpd_opp_svs: opp5 {
363 opp-level = <RPM_SMD_LEVEL_SVS>;
366 rpmpd_opp_svs_plus: opp6 {
367 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
370 rpmpd_opp_nom: opp7 {
371 opp-level = <RPM_SMD_LEVEL_NOM>;
374 rpmpd_opp_nom_plus: opp8 {
375 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
378 rpmpd_opp_turbo: opp9 {
379 opp-level = <RPM_SMD_LEVEL_TURBO>;
388 compatible = "qcom,smsm";
390 #address-cells = <1>;
393 qcom,ipc-1 = <&apcs 8 13>;
394 qcom,ipc-3 = <&apcs 8 19>;
399 #qcom,smem-state-cells = <1>;
404 #address-cells = <1>;
406 ranges = <0 0 0 0xffffffff>;
407 compatible = "simple-bus";
409 rpm_msg_ram: sram@60000 {
410 compatible = "qcom,rpm-msg-ram";
411 reg = <0x60000 0x8000>;
414 hsusb_phy: phy@79000 {
415 compatible = "qcom,msm8953-qusb2-phy";
416 reg = <0x79000 0x180>;
419 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
420 <&gcc GCC_QUSB_REF_CLK>;
421 clock-names = "cfg_ahb", "ref";
423 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>;
425 resets = <&gcc GCC_QUSB2_PHY_BCR>;
431 compatible = "qcom,prng";
432 reg = <0x000e3000 0x1000>;
433 clocks = <&gcc GCC_PRNG_AHB_CLK>;
434 clock-names = "core";
437 tsens0: thermal-sensor@4a9000 {
438 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
439 reg = <0x4a9000 0x1000>, /* TM */
440 <0x4a8000 0x1000>; /* SROT */
441 #qcom,sensors = <16>;
442 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
444 interrupt-names = "uplow", "critical";
445 #thermal-sensor-cells = <1>;
449 compatible = "qcom,pshold";
450 reg = <0x4ab000 0x4>;
453 tlmm: pinctrl@1000000 {
454 compatible = "qcom,msm8953-pinctrl";
455 reg = <0x1000000 0x300000>;
456 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
458 gpio-ranges = <&tlmm 0 0 155>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
463 uart_console_active: uart-console-active-pins {
464 pins = "gpio4", "gpio5";
465 function = "blsp_uart2";
466 drive-strength = <2>;
470 uart_console_sleep: uart-console-sleep-pins {
471 pins = "gpio4", "gpio5";
472 function = "blsp_uart2";
473 drive-strength = <2>;
477 sdc1_clk_on: sdc1-clk-on-pins {
480 drive-strength = <16>;
483 sdc1_clk_off: sdc1-clk-off-pins {
486 drive-strength = <2>;
489 sdc1_cmd_on: sdc1-cmd-on-pins {
492 drive-strength = <10>;
495 sdc1_cmd_off: sdc1-cmd-off-pins {
498 drive-strength = <2>;
501 sdc1_data_on: sdc1-data-on-pins {
504 drive-strength = <10>;
507 sdc1_data_off: sdc1-data-off-pins {
510 drive-strength = <2>;
513 sdc1_rclk_on: sdc1-rclk-on-pins {
518 sdc1_rclk_off: sdc1-rclk-off-pins {
523 sdc2_clk_on: sdc2-clk-on-pins {
525 drive-strength = <16>;
529 sdc2_clk_off: sdc2-clk-off-pins {
532 drive-strength = <2>;
535 sdc2_cmd_on: sdc2-cmd-on-pins {
538 drive-strength = <10>;
541 sdc2_cmd_off: sdc2-cmd-off-pins {
544 drive-strength = <2>;
547 sdc2_data_on: sdc2-data-on-pins {
550 drive-strength = <10>;
553 sdc2_data_off: sdc2-data-off-pins {
556 drive-strength = <2>;
559 sdc2_cd_on: cd-on-pins {
562 drive-strength = <2>;
566 sdc2_cd_off: cd-off-pins {
569 drive-strength = <2>;
573 gpio_key_default: gpio-key-default-pins {
576 drive-strength = <2>;
580 i2c_1_default: i2c-1-default-pins {
581 pins = "gpio2", "gpio3";
582 function = "blsp_i2c1";
583 drive-strength = <2>;
587 i2c_1_sleep: i2c-1-sleep-pins {
588 pins = "gpio2", "gpio3";
590 drive-strength = <2>;
594 i2c_2_default: i2c-2-default-pins {
595 pins = "gpio6", "gpio7";
596 function = "blsp_i2c2";
597 drive-strength = <2>;
601 i2c_2_sleep: i2c-2-sleep-pins {
602 pins = "gpio6", "gpio7";
604 drive-strength = <2>;
608 i2c_3_default: i2c-3-default-pins {
609 pins = "gpio10", "gpio11";
610 function = "blsp_i2c3";
611 drive-strength = <2>;
615 i2c_3_sleep: i2c-3-sleep-pins {
616 pins = "gpio10", "gpio11";
618 drive-strength = <2>;
622 i2c_4_default: i2c-4-default-pins {
623 pins = "gpio14", "gpio15";
624 function = "blsp_i2c4";
625 drive-strength = <2>;
629 i2c_4_sleep: i2c-4-sleep-pins {
630 pins = "gpio14", "gpio15";
632 drive-strength = <2>;
636 i2c_5_default: i2c-5-default-pins {
637 pins = "gpio18", "gpio19";
638 function = "blsp_i2c5";
639 drive-strength = <2>;
643 i2c_5_sleep: i2c-5-sleep-pins {
644 pins = "gpio18", "gpio19";
646 drive-strength = <2>;
650 i2c_6_default: i2c-6-default-pins {
651 pins = "gpio22", "gpio23";
652 function = "blsp_i2c6";
653 drive-strength = <2>;
657 i2c_6_sleep: i2c-6-sleep-pins {
658 pins = "gpio22", "gpio23";
660 drive-strength = <2>;
664 i2c_7_default: i2c-7-default-pins {
665 pins = "gpio135", "gpio136";
666 function = "blsp_i2c7";
667 drive-strength = <2>;
671 i2c_7_sleep: i2c-7-sleep-pins {
672 pins = "gpio135", "gpio136";
674 drive-strength = <2>;
678 i2c_8_default: i2c-8-default-pins {
679 pins = "gpio98", "gpio99";
680 function = "blsp_i2c8";
681 drive-strength = <2>;
685 i2c_8_sleep: i2c-8-sleep-pins {
686 pins = "gpio98", "gpio99";
688 drive-strength = <2>;
693 gcc: clock-controller@1800000 {
694 compatible = "qcom,gcc-msm8953";
695 reg = <0x1800000 0x80000>;
698 #power-domain-cells = <1>;
699 clocks = <&xo_board>,
713 tcsr_mutex: hwlock@1905000 {
714 compatible = "qcom,tcsr-mutex";
715 reg = <0x1905000 0x20000>;
719 tcsr: syscon@1937000 {
720 compatible = "qcom,tcsr-msm8953", "syscon";
721 reg = <0x1937000 0x30000>;
724 tcsr_phy_clk_scheme_sel: syscon@193f044 {
725 compatible = "syscon";
726 reg = <0x193f044 0x4>;
729 spmi_bus: spmi@200f000 {
730 compatible = "qcom,spmi-pmic-arb";
731 reg = <0x200f000 0x1000>,
732 <0x2400000 0x800000>,
733 <0x2c00000 0x800000>,
734 <0x3800000 0x200000>,
736 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
737 interrupt-names = "periph_irq";
738 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
741 interrupt-controller;
743 #interrupt-cells = <4>;
744 #address-cells = <2>;
749 compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
750 reg = <0x70f8800 0x400>;
751 #address-cells = <1>;
755 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
757 interrupt-names = "hs_phy_irq", "ss_phy_irq";
759 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
760 <&gcc GCC_USB30_MASTER_CLK>,
761 <&gcc GCC_PCNOC_USB3_AXI_CLK>,
762 <&gcc GCC_USB30_SLEEP_CLK>,
763 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
764 clock-names = "cfg_noc",
770 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
771 <&gcc GCC_USB30_MASTER_CLK>;
772 assigned-clock-rates = <19200000>, <133330000>;
774 power-domains = <&gcc USB30_GDSC>;
776 qcom,select-utmi-as-pipe-clk;
780 usb3_dwc3: usb@7000000 {
781 compatible = "snps,dwc3";
782 reg = <0x07000000 0xcc00>;
783 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
785 phy-names = "usb2-phy";
787 snps,usb2-gadget-lpm-disable;
788 snps,dis-u1-entry-quirk;
789 snps,dis-u2-entry-quirk;
790 snps,is-utmi-l1-suspend;
791 snps,hird-threshold = /bits/ 8 <0x00>;
793 maximum-speed = "high-speed";
798 sdhc_1: mmc@7824900 {
799 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
801 reg = <0x7824900 0x500>, <0x7824000 0x800>;
802 reg-names = "hc_mem", "core_mem";
804 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
806 interrupt-names = "hc_irq", "pwr_irq";
808 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
809 <&gcc GCC_SDCC1_APPS_CLK>,
811 clock-names = "iface", "core", "xo";
813 power-domains = <&rpmpd MSM8953_VDDCX>;
814 operating-points-v2 = <&sdhc1_opp_table>;
816 pinctrl-names = "default", "sleep";
817 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
818 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
828 sdhc1_opp_table: opp-table-sdhc1 {
829 compatible = "operating-points-v2";
832 opp-hz = /bits/ 64 <25000000>;
833 required-opps = <&rpmpd_opp_low_svs>;
837 opp-hz = /bits/ 64 <50000000>;
838 required-opps = <&rpmpd_opp_svs>;
842 opp-hz = /bits/ 64 <100000000>;
843 required-opps = <&rpmpd_opp_svs>;
847 opp-hz = /bits/ 64 <192000000>;
848 required-opps = <&rpmpd_opp_nom>;
852 opp-hz = /bits/ 64 <384000000>;
853 required-opps = <&rpmpd_opp_nom>;
858 sdhc_2: mmc@7864900 {
859 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
861 reg = <0x7864900 0x500>, <0x7864000 0x800>;
862 reg-names = "hc_mem", "core_mem";
864 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
865 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
866 interrupt-names = "hc_irq", "pwr_irq";
868 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
869 <&gcc GCC_SDCC2_APPS_CLK>,
871 clock-names = "iface", "core", "xo";
873 power-domains = <&rpmpd MSM8953_VDDCX>;
874 operating-points-v2 = <&sdhc2_opp_table>;
876 pinctrl-names = "default", "sleep";
877 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
878 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
884 sdhc2_opp_table: opp-table-sdhc2 {
885 compatible = "operating-points-v2";
888 opp-hz = /bits/ 64 <25000000>;
889 required-opps = <&rpmpd_opp_low_svs>;
893 opp-hz = /bits/ 64 <50000000>;
894 required-opps = <&rpmpd_opp_svs>;
898 opp-hz = /bits/ 64 <100000000>;
899 required-opps = <&rpmpd_opp_svs>;
903 opp-hz = /bits/ 64 <177770000>;
904 required-opps = <&rpmpd_opp_nom>;
908 opp-hz = /bits/ 64 <200000000>;
909 required-opps = <&rpmpd_opp_nom>;
914 uart_0: serial@78af000 {
915 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
916 reg = <0x78af000 0x200>;
917 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
919 <&gcc GCC_BLSP1_AHB_CLK>;
920 clock-names = "core", "iface";
926 compatible = "qcom,i2c-qup-v2.2.1";
927 reg = <0x78b5000 0x600>;
928 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
929 clock-names = "core", "iface";
930 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
931 <&gcc GCC_BLSP1_AHB_CLK>;
933 pinctrl-names = "default", "sleep";
934 pinctrl-0 = <&i2c_1_default>;
935 pinctrl-1 = <&i2c_1_sleep>;
937 #address-cells = <1>;
944 compatible = "qcom,i2c-qup-v2.2.1";
945 reg = <0x78b6000 0x600>;
946 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
947 clock-names = "core", "iface";
948 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
949 <&gcc GCC_BLSP1_AHB_CLK>;
951 pinctrl-names = "default", "sleep";
952 pinctrl-0 = <&i2c_2_default>;
953 pinctrl-1 = <&i2c_2_sleep>;
955 #address-cells = <1>;
962 compatible = "qcom,i2c-qup-v2.2.1";
963 reg = <0x78b7000 0x600>;
964 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
965 clock-names = "core", "iface";
966 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
967 <&gcc GCC_BLSP1_AHB_CLK>;
968 pinctrl-names = "default", "sleep";
969 pinctrl-0 = <&i2c_3_default>;
970 pinctrl-1 = <&i2c_3_sleep>;
972 #address-cells = <1>;
979 compatible = "qcom,i2c-qup-v2.2.1";
980 reg = <0x78b8000 0x600>;
981 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
982 clock-names = "core", "iface";
983 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
984 <&gcc GCC_BLSP1_AHB_CLK>;
985 pinctrl-names = "default", "sleep";
986 pinctrl-0 = <&i2c_4_default>;
987 pinctrl-1 = <&i2c_4_sleep>;
989 #address-cells = <1>;
996 compatible = "qcom,i2c-qup-v2.2.1";
997 reg = <0x7af5000 0x600>;
998 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
999 clock-names = "core", "iface";
1000 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
1001 <&gcc GCC_BLSP2_AHB_CLK>;
1002 pinctrl-names = "default", "sleep";
1003 pinctrl-0 = <&i2c_5_default>;
1004 pinctrl-1 = <&i2c_5_sleep>;
1006 #address-cells = <1>;
1009 status = "disabled";
1012 i2c_6: i2c@7af6000 {
1013 compatible = "qcom,i2c-qup-v2.2.1";
1014 reg = <0x7af6000 0x600>;
1015 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1016 clock-names = "core", "iface";
1017 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
1018 <&gcc GCC_BLSP2_AHB_CLK>;
1019 pinctrl-names = "default", "sleep";
1020 pinctrl-0 = <&i2c_6_default>;
1021 pinctrl-1 = <&i2c_6_sleep>;
1023 #address-cells = <1>;
1026 status = "disabled";
1029 i2c_7: i2c@7af7000 {
1030 compatible = "qcom,i2c-qup-v2.2.1";
1031 reg = <0x7af7000 0x600>;
1032 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
1033 clock-names = "core", "iface";
1034 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
1035 <&gcc GCC_BLSP2_AHB_CLK>;
1036 pinctrl-names = "default", "sleep";
1037 pinctrl-0 = <&i2c_7_default>;
1038 pinctrl-1 = <&i2c_7_sleep>;
1040 #address-cells = <1>;
1043 status = "disabled";
1046 i2c_8: i2c@7af8000 {
1047 compatible = "qcom,i2c-qup-v2.2.1";
1048 reg = <0x7af8000 0x600>;
1049 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
1050 clock-names = "core", "iface";
1051 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
1052 <&gcc GCC_BLSP2_AHB_CLK>;
1053 pinctrl-names = "default", "sleep";
1054 pinctrl-0 = <&i2c_8_default>;
1055 pinctrl-1 = <&i2c_8_sleep>;
1057 #address-cells = <1>;
1060 status = "disabled";
1063 intc: interrupt-controller@b000000 {
1064 compatible = "qcom,msm-qgic2";
1065 interrupt-controller;
1066 #interrupt-cells = <3>;
1067 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
1070 apcs: mailbox@b011000 {
1071 compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
1072 reg = <0xb011000 0x1000>;
1077 compatible = "arm,armv7-timer-mem";
1078 reg = <0xb120000 0x1000>;
1079 #address-cells = <0x01>;
1080 #size-cells = <0x01>;
1085 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1086 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1087 reg = <0xb121000 0x1000>,
1093 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1094 reg = <0xb123000 0x1000>;
1095 status = "disabled";
1100 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1101 reg = <0xb124000 0x1000>;
1102 status = "disabled";
1107 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1108 reg = <0xb125000 0x1000>;
1109 status = "disabled";
1114 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1115 reg = <0xb126000 0x1000>;
1116 status = "disabled";
1121 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1122 reg = <0xb127000 0x1000>;
1123 status = "disabled";
1128 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1129 reg = <0xb128000 0x1000>;
1130 status = "disabled";
1137 polling-delay-passive = <250>;
1138 polling-delay = <1000>;
1139 thermal-sensors = <&tsens0 9>;
1141 cpu0_alert: trip-point0 {
1142 temperature = <80000>;
1143 hysteresis = <2000>;
1147 temperature = <100000>;
1148 hysteresis = <2000>;
1154 trip = <&cpu0_alert>;
1155 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1160 polling-delay-passive = <250>;
1161 polling-delay = <1000>;
1162 thermal-sensors = <&tsens0 10>;
1164 cpu1_alert: trip-point0 {
1165 temperature = <80000>;
1166 hysteresis = <2000>;
1170 temperature = <100000>;
1171 hysteresis = <2000>;
1177 trip = <&cpu1_alert>;
1178 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1183 polling-delay-passive = <250>;
1184 polling-delay = <1000>;
1185 thermal-sensors = <&tsens0 11>;
1187 cpu2_alert: trip-point0 {
1188 temperature = <80000>;
1189 hysteresis = <2000>;
1193 temperature = <100000>;
1194 hysteresis = <2000>;
1200 trip = <&cpu2_alert>;
1201 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1206 polling-delay-passive = <250>;
1207 polling-delay = <1000>;
1208 thermal-sensors = <&tsens0 12>;
1210 cpu3_alert: trip-point0 {
1211 temperature = <80000>;
1212 hysteresis = <2000>;
1216 temperature = <100000>;
1217 hysteresis = <2000>;
1223 trip = <&cpu3_alert>;
1224 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1229 polling-delay-passive = <250>;
1230 polling-delay = <1000>;
1231 thermal-sensors = <&tsens0 4>;
1233 cpu4_alert: trip-point0 {
1234 temperature = <80000>;
1235 hysteresis = <2000>;
1239 temperature = <100000>;
1240 hysteresis = <2000>;
1246 trip = <&cpu4_alert>;
1247 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1252 polling-delay-passive = <250>;
1253 polling-delay = <1000>;
1254 thermal-sensors = <&tsens0 5>;
1256 cpu5_alert: trip-point0 {
1257 temperature = <80000>;
1258 hysteresis = <2000>;
1262 temperature = <100000>;
1263 hysteresis = <2000>;
1269 trip = <&cpu5_alert>;
1270 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1275 polling-delay-passive = <250>;
1276 polling-delay = <1000>;
1277 thermal-sensors = <&tsens0 6>;
1279 cpu6_alert: trip-point0 {
1280 temperature = <80000>;
1281 hysteresis = <2000>;
1285 temperature = <100000>;
1286 hysteresis = <2000>;
1292 trip = <&cpu6_alert>;
1293 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1298 polling-delay-passive = <250>;
1299 polling-delay = <1000>;
1300 thermal-sensors = <&tsens0 7>;
1302 cpu7_alert: trip-point0 {
1303 temperature = <80000>;
1304 hysteresis = <2000>;
1308 temperature = <100000>;
1309 hysteresis = <2000>;
1315 trip = <&cpu7_alert>;
1316 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1323 compatible = "arm,armv8-timer";
1324 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1325 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1326 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1327 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;