arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17 #include <dt-bindings/clock/qcom,rpmcc.h>
  18
  19 / {
  20         model = "Qualcomm Technologies, Inc. MSM8916";
  21         compatible = "qcom,msm8916";
  22
  23         interrupt-parent = <&intc>;
  24
  25         #address-cells = <2>;
  26         #size-cells = <2>;
  27
  28         aliases {
  29                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  30                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  31         };
  32
  33         chosen { };
  34
  35         memory {
  36                 device_type = "memory";
  37                 /* We expect the bootloader to fill in the reg */
  38                 reg = <0 0 0 0>;
  39         };
  40
  41         reserved-memory {
  42                 #address-cells = <2>;
  43                 #size-cells = <2>;
  44                 ranges;
  45
  46                 tz-apps@86000000 {
  47                         reg = <0x0 0x86000000 0x0 0x300000>;
  48                         no-map;
  49                 };
  50
  51                 smem_mem: smem_region@86300000 {
  52                         reg = <0x0 0x86300000 0x0 0x100000>;
  53                         no-map;
  54                 };
  55
  56                 hypervisor@86400000 {
  57                         reg = <0x0 0x86400000 0x0 0x100000>;
  58                         no-map;
  59                 };
  60
  61                 tz@86500000 {
  62                         reg = <0x0 0x86500000 0x0 0x180000>;
  63                         no-map;
  64                 };
  65
  66                 reserved@8668000 {
  67                         reg = <0x0 0x86680000 0x0 0x80000>;
  68                         no-map;
  69                 };
  70
  71                 rmtfs@86700000 {
  72                         reg = <0x0 0x86700000 0x0 0xe0000>;
  73                         no-map;
  74                 };
  75
  76                 rfsa@867e00000 {
  77                         reg = <0x0 0x867e0000 0x0 0x20000>;
  78                         no-map;
  79                 };
  80
  81                 mpss_mem: mpss@86800000 {
  82                         reg = <0x0 0x86800000 0x0 0x2b00000>;
  83                         no-map;
  84                 };
  85
  86                 wcnss_mem: wcnss@89300000 {
  87                         reg = <0x0 0x89300000 0x0 0x600000>;
  88                         no-map;
  89                 };
  90
  91                 venus_mem: venus@89900000 {
  92                         reg = <0x0 0x89900000 0x0 0x600000>;
  93                         no-map;
  94                 };
  95
  96                 mba_mem: mba@8ea00000 {
  97                         no-map;
  98                         reg = <0 0x8ea00000 0 0x100000>;
  99                 };
 100         };
 101
 102         cpus {
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105
 106                 CPU0: cpu@0 {
 107                         device_type = "cpu";
 108                         compatible = "arm,cortex-a53", "arm,armv8";
 109                         reg = <0x0>;
 110                         next-level-cache = <&L2_0>;
 111                         enable-method = "psci";
 112                         cpu-idle-states = <&CPU_SPC>;
 113                 };
 114
 115                 CPU1: cpu@1 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x1>;
 119                         next-level-cache = <&L2_0>;
 120                         enable-method = "psci";
 121                         cpu-idle-states = <&CPU_SPC>;
 122                 };
 123
 124                 CPU2: cpu@2 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x2>;
 128                         next-level-cache = <&L2_0>;
 129                         enable-method = "psci";
 130                         cpu-idle-states = <&CPU_SPC>;
 131                 };
 132
 133                 CPU3: cpu@3 {
 134                         device_type = "cpu";
 135                         compatible = "arm,cortex-a53", "arm,armv8";
 136                         reg = <0x3>;
 137                         next-level-cache = <&L2_0>;
 138                         enable-method = "psci";
 139                         cpu-idle-states = <&CPU_SPC>;
 140                 };
 141
 142                 L2_0: l2-cache {
 143                       compatible = "cache";
 144                       cache-level = <2>;
 145                 };
 146
 147                 idle-states {
 148                         CPU_SPC: spc {
 149                                 compatible = "arm,idle-state";
 150                                 arm,psci-suspend-param = <0x40000002>;
 151                                 entry-latency-us = <130>;
 152                                 exit-latency-us = <150>;
 153                                 min-residency-us = <2000>;
 154                                 local-timer-stop;
 155                         };
 156                 };
 157         };
 158
 159         psci {
 160                 compatible = "arm,psci-1.0";
 161                 method = "smc";
 162         };
 163
 164         pmu {
 165                 compatible = "arm,cortex-a53-pmu";
 166                 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
 167         };
 168
 169         thermal-zones {
 170                 cpu-thermal0 {
 171                         polling-delay-passive = <250>;
 172                         polling-delay = <1000>;
 173
 174                         thermal-sensors = <&tsens 4>;
 175
 176                         trips {
 177                                 cpu_alert0: trip0 {
 178                                         temperature = <75000>;
 179                                         hysteresis = <2000>;
 180                                         type = "passive";
 181                                 };
 182                                 cpu_crit0: trip1 {
 183                                         temperature = <110000>;
 184                                         hysteresis = <2000>;
 185                                         type = "critical";
 186                                 };
 187                         };
 188                 };
 189
 190                 cpu-thermal1 {
 191                         polling-delay-passive = <250>;
 192                         polling-delay = <1000>;
 193
 194                         thermal-sensors = <&tsens 3>;
 195
 196                         trips {
 197                                 cpu_alert1: trip0 {
 198                                         temperature = <75000>;
 199                                         hysteresis = <2000>;
 200                                         type = "passive";
 201                                 };
 202                                 cpu_crit1: trip1 {
 203                                         temperature = <110000>;
 204                                         hysteresis = <2000>;
 205                                         type = "critical";
 206                                 };
 207                         };
 208                 };
 209
 210         };
 211
 212         gpu_opp_table: opp_table {
 213                 compatible = "operating-points-v2";
 214
 215                 opp-400000000 {
 216                         opp-hz = /bits/ 64 <400000000>;
 217                 };
 218                 opp-19200000 {
 219                         opp-hz = /bits/ 64 <19200000>;
 220                 };
 221         };
 222
 223         timer {
 224                 compatible = "arm,armv8-timer";
 225                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 226                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 227                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 228                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 229         };
 230
 231         clocks {
 232                 xo_board: xo_board {
 233                         compatible = "fixed-clock";
 234                         #clock-cells = <0>;
 235                         clock-frequency = <19200000>;
 236                 };
 237
 238                 sleep_clk: sleep_clk {
 239                         compatible = "fixed-clock";
 240                         #clock-cells = <0>;
 241                         clock-frequency = <32768>;
 242                 };
 243         };
 244
 245         smem {
 246                 compatible = "qcom,smem";
 247
 248                 memory-region = <&smem_mem>;
 249                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 250
 251                 hwlocks = <&tcsr_mutex 3>;
 252         };
 253
 254         firmware {
 255                 scm: scm {
 256                         compatible = "qcom,scm";
 257                         clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
 258                         clock-names = "core", "bus", "iface";
 259                         #reset-cells = <1>;
 260                 };
 261         };
 262
 263         soc: soc {
 264                 #address-cells = <1>;
 265                 #size-cells = <1>;
 266                 ranges = <0 0 0 0xffffffff>;
 267                 compatible = "simple-bus";
 268
 269                 restart@4ab000 {
 270                         compatible = "qcom,pshold";
 271                         reg = <0x4ab000 0x4>;
 272                 };
 273
 274                 msmgpio: pinctrl@1000000 {
 275                         compatible = "qcom,msm8916-pinctrl";
 276                         reg = <0x1000000 0x300000>;
 277                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 278                         gpio-controller;
 279                         #gpio-cells = <2>;
 280                         interrupt-controller;
 281                         #interrupt-cells = <2>;
 282                 };
 283
 284                 gcc: clock-controller@1800000 {
 285                         compatible = "qcom,gcc-msm8916";
 286                         #clock-cells = <1>;
 287                         #reset-cells = <1>;
 288                         #power-domain-cells = <1>;
 289                         reg = <0x1800000 0x80000>;
 290                 };
 291
 292                 tcsr_mutex_regs: syscon@1905000 {
 293                         compatible = "syscon";
 294                         reg = <0x1905000 0x20000>;
 295                 };
 296
 297                 tcsr: syscon@1937000 {
 298                         compatible = "qcom,tcsr-msm8916", "syscon";
 299                         reg = <0x1937000 0x30000>;
 300                 };
 301
 302                 tcsr_mutex: hwlock {
 303                         compatible = "qcom,tcsr-mutex";
 304                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 305                         #hwlock-cells = <1>;
 306                 };
 307
 308                 rpm_msg_ram: memory@60000 {
 309                         compatible = "qcom,rpm-msg-ram";
 310                         reg = <0x60000 0x8000>;
 311                 };
 312
 313                 blsp1_uart1: serial@78af000 {
 314                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 315                         reg = <0x78af000 0x200>;
 316                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 317                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 318                         clock-names = "core", "iface";
 319                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 320                         dma-names = "rx", "tx";
 321                         status = "disabled";
 322                 };
 323
 324                 apcs: syscon@b011000 {
 325                         compatible = "syscon";
 326                         reg = <0x0b011000 0x1000>;
 327                 };
 328
 329                 blsp1_uart2: serial@78b0000 {
 330                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 331                         reg = <0x78b0000 0x200>;
 332                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 333                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 334                         clock-names = "core", "iface";
 335                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 336                         dma-names = "rx", "tx";
 337                         status = "disabled";
 338                 };
 339
 340                 blsp_dma: dma@7884000 {
 341                         compatible = "qcom,bam-v1.7.0";
 342                         reg = <0x07884000 0x23000>;
 343                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 345                         clock-names = "bam_clk";
 346                         #dma-cells = <1>;
 347                         qcom,ee = <0>;
 348                         status = "disabled";
 349                 };
 350
 351                 blsp_spi1: spi@78b5000 {
 352                         compatible = "qcom,spi-qup-v2.2.1";
 353                         reg = <0x078b5000 0x600>;
 354                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 356                                  <&gcc GCC_BLSP1_AHB_CLK>;
 357                         clock-names = "core", "iface";
 358                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 359                         dma-names = "rx", "tx";
 360                         pinctrl-names = "default", "sleep";
 361                         pinctrl-0 = <&spi1_default>;
 362                         pinctrl-1 = <&spi1_sleep>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         status = "disabled";
 366                 };
 367
 368                 blsp_spi2: spi@78b6000 {
 369                         compatible = "qcom,spi-qup-v2.2.1";
 370                         reg = <0x078b6000 0x600>;
 371                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 372                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 373                                  <&gcc GCC_BLSP1_AHB_CLK>;
 374                         clock-names = "core", "iface";
 375                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 376                         dma-names = "rx", "tx";
 377                         pinctrl-names = "default", "sleep";
 378                         pinctrl-0 = <&spi2_default>;
 379                         pinctrl-1 = <&spi2_sleep>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         status = "disabled";
 383                 };
 384
 385                 blsp_spi3: spi@78b7000 {
 386                         compatible = "qcom,spi-qup-v2.2.1";
 387                         reg = <0x078b7000 0x600>;
 388                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 389                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 390                                  <&gcc GCC_BLSP1_AHB_CLK>;
 391                         clock-names = "core", "iface";
 392                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 393                         dma-names = "rx", "tx";
 394                         pinctrl-names = "default", "sleep";
 395                         pinctrl-0 = <&spi3_default>;
 396                         pinctrl-1 = <&spi3_sleep>;
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         status = "disabled";
 400                 };
 401
 402                 blsp_spi4: spi@78b8000 {
 403                         compatible = "qcom,spi-qup-v2.2.1";
 404                         reg = <0x078b8000 0x600>;
 405                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 406                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 407                                  <&gcc GCC_BLSP1_AHB_CLK>;
 408                         clock-names = "core", "iface";
 409                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 410                         dma-names = "rx", "tx";
 411                         pinctrl-names = "default", "sleep";
 412                         pinctrl-0 = <&spi4_default>;
 413                         pinctrl-1 = <&spi4_sleep>;
 414                         #address-cells = <1>;
 415                         #size-cells = <0>;
 416                         status = "disabled";
 417                 };
 418
 419                 blsp_spi5: spi@78b9000 {
 420                         compatible = "qcom,spi-qup-v2.2.1";
 421                         reg = <0x078b9000 0x600>;
 422                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 424                                  <&gcc GCC_BLSP1_AHB_CLK>;
 425                         clock-names = "core", "iface";
 426                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 427                         dma-names = "rx", "tx";
 428                         pinctrl-names = "default", "sleep";
 429                         pinctrl-0 = <&spi5_default>;
 430                         pinctrl-1 = <&spi5_sleep>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         status = "disabled";
 434                 };
 435
 436                 blsp_spi6: spi@78ba000 {
 437                         compatible = "qcom,spi-qup-v2.2.1";
 438                         reg = <0x078ba000 0x600>;
 439                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 441                                  <&gcc GCC_BLSP1_AHB_CLK>;
 442                         clock-names = "core", "iface";
 443                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 444                         dma-names = "rx", "tx";
 445                         pinctrl-names = "default", "sleep";
 446                         pinctrl-0 = <&spi6_default>;
 447                         pinctrl-1 = <&spi6_sleep>;
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         status = "disabled";
 451                 };
 452
 453                 blsp_i2c2: i2c@78b6000 {
 454                         compatible = "qcom,i2c-qup-v2.2.1";
 455                         reg = <0x78b6000 0x1000>;
 456                         interrupts = <GIC_SPI 96 0>;
 457                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 458                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 459                         clock-names = "iface", "core";
 460                         pinctrl-names = "default", "sleep";
 461                         pinctrl-0 = <&i2c2_default>;
 462                         pinctrl-1 = <&i2c2_sleep>;
 463                         #address-cells = <1>;
 464                         #size-cells = <0>;
 465                         status = "disabled";
 466                 };
 467
 468                 blsp_i2c4: i2c@78b8000 {
 469                         compatible = "qcom,i2c-qup-v2.2.1";
 470                         reg = <0x78b8000 0x1000>;
 471                         interrupts = <GIC_SPI 98 0>;
 472                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 473                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 474                         clock-names = "iface", "core";
 475                         pinctrl-names = "default", "sleep";
 476                         pinctrl-0 = <&i2c4_default>;
 477                         pinctrl-1 = <&i2c4_sleep>;
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         status = "disabled";
 481                 };
 482
 483                 blsp_i2c6: i2c@78ba000 {
 484                         compatible = "qcom,i2c-qup-v2.2.1";
 485                         reg = <0x78ba000 0x1000>;
 486                         interrupts = <GIC_SPI 100 0>;
 487                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 488                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 489                         clock-names = "iface", "core";
 490                         pinctrl-names = "default", "sleep";
 491                         pinctrl-0 = <&i2c6_default>;
 492                         pinctrl-1 = <&i2c6_sleep>;
 493                         #address-cells = <1>;
 494                         #size-cells = <0>;
 495                         status = "disabled";
 496                 };
 497
 498                 lpass: lpass@07708000 {
 499                         status = "disabled";
 500                         compatible = "qcom,lpass-cpu-apq8016";
 501                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 502                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 503                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 504                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 505                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 506                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 507                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 508
 509                         clock-names = "ahbix-clk",
 510                                         "pcnoc-mport-clk",
 511                                         "pcnoc-sway-clk",
 512                                         "mi2s-bit-clk0",
 513                                         "mi2s-bit-clk1",
 514                                         "mi2s-bit-clk2",
 515                                         "mi2s-bit-clk3";
 516                         #sound-dai-cells = <1>;
 517
 518                         interrupts = <0 160 0>;
 519                         interrupt-names = "lpass-irq-lpaif";
 520                         reg = <0x07708000 0x10000>;
 521                         reg-names = "lpass-lpaif";
 522                 };
 523
 524                 lpass_codec: codec{
 525                         compatible = "qcom,msm8916-wcd-digital-codec";
 526                         reg = <0x0771c000 0x400>;
 527                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 528                                  <&gcc GCC_CODEC_DIGCODEC_CLK>;
 529                         clock-names = "ahbix-clk", "mclk";
 530                         #sound-dai-cells = <1>;
 531                 };
 532
 533                 sdhc_1: sdhci@07824000 {
 534                         compatible = "qcom,sdhci-msm-v4";
 535                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 536                         reg-names = "hc_mem", "core_mem";
 537
 538                         interrupts = <0 123 0>, <0 138 0>;
 539                         interrupt-names = "hc_irq", "pwr_irq";
 540                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 541                                  <&gcc GCC_SDCC1_AHB_CLK>,
 542                                  <&xo_board>;
 543                         clock-names = "core", "iface", "xo";
 544                         mmc-ddr-1_8v;
 545                         bus-width = <8>;
 546                         non-removable;
 547                         status = "disabled";
 548                 };
 549
 550                 sdhc_2: sdhci@07864000 {
 551                         compatible = "qcom,sdhci-msm-v4";
 552                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 553                         reg-names = "hc_mem", "core_mem";
 554
 555                         interrupts = <0 125 0>, <0 221 0>;
 556                         interrupt-names = "hc_irq", "pwr_irq";
 557                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 558                                  <&gcc GCC_SDCC2_AHB_CLK>,
 559                                  <&xo_board>;
 560                         clock-names = "core", "iface", "xo";
 561                         bus-width = <4>;
 562                         status = "disabled";
 563                 };
 564
 565                 otg: usb@78d9000 {
 566                         compatible = "qcom,ci-hdrc";
 567                         reg = <0x78d9000 0x200>,
 568                               <0x78d9200 0x200>;
 569                         interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 570                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 572                                  <&gcc GCC_USB_HS_SYSTEM_CLK>;
 573                         clock-names = "iface", "core";
 574                         assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
 575                         assigned-clock-rates = <80000000>;
 576                         resets = <&gcc GCC_USB_HS_BCR>;
 577                         reset-names = "core";
 578                         phy_type = "ulpi";
 579                         dr_mode = "otg";
 580                         ahb-burst-config = <0>;
 581                         phy-names = "usb-phy";
 582                         phys = <&usb_hs_phy>;
 583                         status = "disabled";
 584                         #reset-cells = <1>;
 585
 586                         ulpi {
 587                                 usb_hs_phy: phy {
 588                                         compatible = "qcom,usb-hs-phy-msm8916",
 589                                                      "qcom,usb-hs-phy";
 590                                         #phy-cells = <0>;
 591                                         clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 592                                         clock-names = "ref", "sleep";
 593                                         resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
 594                                         reset-names = "phy", "por";
 595                                         qcom,init-seq = /bits/ 8 <0x0 0x44
 596                                                 0x1 0x6b 0x2 0x24 0x3 0x13>;
 597                                 };
 598                         };
 599                 };
 600
 601                 intc: interrupt-controller@b000000 {
 602                         compatible = "qcom,msm-qgic2";
 603                         interrupt-controller;
 604                         #interrupt-cells = <3>;
 605                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 606                 };
 607
 608                 timer@b020000 {
 609                         #address-cells = <1>;
 610                         #size-cells = <1>;
 611                         ranges;
 612                         compatible = "arm,armv7-timer-mem";
 613                         reg = <0xb020000 0x1000>;
 614                         clock-frequency = <19200000>;
 615
 616                         frame@b021000 {
 617                                 frame-number = <0>;
 618                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 619                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 620                                 reg = <0xb021000 0x1000>,
 621                                       <0xb022000 0x1000>;
 622                         };
 623
 624                         frame@b023000 {
 625                                 frame-number = <1>;
 626                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 627                                 reg = <0xb023000 0x1000>;
 628                                 status = "disabled";
 629                         };
 630
 631                         frame@b024000 {
 632                                 frame-number = <2>;
 633                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 634                                 reg = <0xb024000 0x1000>;
 635                                 status = "disabled";
 636                         };
 637
 638                         frame@b025000 {
 639                                 frame-number = <3>;
 640                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 641                                 reg = <0xb025000 0x1000>;
 642                                 status = "disabled";
 643                         };
 644
 645                         frame@b026000 {
 646                                 frame-number = <4>;
 647                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 648                                 reg = <0xb026000 0x1000>;
 649                                 status = "disabled";
 650                         };
 651
 652                         frame@b027000 {
 653                                 frame-number = <5>;
 654                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 655                                 reg = <0xb027000 0x1000>;
 656                                 status = "disabled";
 657                         };
 658
 659                         frame@b028000 {
 660                                 frame-number = <6>;
 661                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 662                                 reg = <0xb028000 0x1000>;
 663                                 status = "disabled";
 664                         };
 665                 };
 666
 667                 spmi_bus: spmi@200f000 {
 668                         compatible = "qcom,spmi-pmic-arb";
 669                         reg = <0x200f000 0x001000>,
 670                               <0x2400000 0x400000>,
 671                               <0x2c00000 0x400000>,
 672                               <0x3800000 0x200000>,
 673                               <0x200a000 0x002100>;
 674                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 675                         interrupt-names = "periph_irq";
 676                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 677                         qcom,ee = <0>;
 678                         qcom,channel = <0>;
 679                         #address-cells = <2>;
 680                         #size-cells = <0>;
 681                         interrupt-controller;
 682                         #interrupt-cells = <4>;
 683                 };
 684
 685                 rng@22000 {
 686                         compatible = "qcom,prng";
 687                         reg = <0x00022000 0x200>;
 688                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 689                         clock-names = "core";
 690                 };
 691
 692                 qfprom: qfprom@5c000 {
 693                         compatible = "qcom,qfprom";
 694                         reg = <0x5c000 0x1000>;
 695                         #address-cells = <1>;
 696                         #size-cells = <1>;
 697                         tsens_caldata: caldata@d0 {
 698                                 reg = <0xd0 0x8>;
 699                         };
 700                         tsens_calsel: calsel@ec {
 701                                 reg = <0xec 0x4>;
 702                         };
 703                 };
 704
 705                 tsens: thermal-sensor@4a8000 {
 706                         compatible = "qcom,msm8916-tsens";
 707                         reg = <0x4a8000 0x2000>;
 708                         nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
 709                         nvmem-cell-names = "calib", "calib_sel";
 710                         #thermal-sensor-cells = <1>;
 711                 };
 712
 713                 apps_iommu: iommu@1ef0000 {
 714                         #address-cells = <1>;
 715                         #size-cells = <1>;
 716                         #iommu-cells = <1>;
 717                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 718                         ranges = <0 0x1e20000 0x40000>;
 719                         reg = <0x1ef0000 0x3000>;
 720                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 721                                  <&gcc GCC_APSS_TCU_CLK>;
 722                         clock-names = "iface", "bus";
 723                         qcom,iommu-secure-id = <17>;
 724
 725                         // mdp_0:
 726                         iommu-ctx@4000 {
 727                                 compatible = "qcom,msm-iommu-v1-ns";
 728                                 reg = <0x4000 0x1000>;
 729                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 730                         };
 731
 732                         // venus_ns:
 733                         iommu-ctx@5000 {
 734                                 compatible = "qcom,msm-iommu-v1-sec";
 735                                 reg = <0x5000 0x1000>;
 736                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 737                         };
 738                 };
 739
 740                 gpu_iommu: iommu@1f08000 {
 741                         #address-cells = <1>;
 742                         #size-cells = <1>;
 743                         #iommu-cells = <1>;
 744                         compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
 745                         ranges = <0 0x1f08000 0x10000>;
 746                         clocks = <&gcc GCC_SMMU_CFG_CLK>,
 747                                  <&gcc GCC_GFX_TCU_CLK>;
 748                         clock-names = "iface", "bus";
 749                         qcom,iommu-secure-id = <18>;
 750
 751                         // gfx3d_user:
 752                         iommu-ctx@1000 {
 753                                 compatible = "qcom,msm-iommu-v1-ns";
 754                                 reg = <0x1000 0x1000>;
 755                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 756                         };
 757
 758                         // gfx3d_priv:
 759                         iommu-ctx@2000 {
 760                                 compatible = "qcom,msm-iommu-v1-ns";
 761                                 reg = <0x2000 0x1000>;
 762                                 interrupts = <GIC_SPI 242 0>;
 763                         };
 764                 };
 765
 766                 gpu@1c00000 {
 767                         compatible = "qcom,adreno-306.0", "qcom,adreno";
 768                         reg = <0x01c00000 0x20000>;
 769                         reg-names = "kgsl_3d0_reg_memory";
 770                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 771                         interrupt-names = "kgsl_3d0_irq";
 772                         clock-names =
 773                             "core",
 774                             "iface",
 775                             "mem",
 776                             "mem_iface",
 777                             "alt_mem_iface",
 778                             "gfx3d";
 779                         clocks =
 780                             <&gcc GCC_OXILI_GFX3D_CLK>,
 781                             <&gcc GCC_OXILI_AHB_CLK>,
 782                             <&gcc GCC_OXILI_GMEM_CLK>,
 783                             <&gcc GCC_BIMC_GFX_CLK>,
 784                             <&gcc GCC_BIMC_GPU_CLK>,
 785                             <&gcc GFX3D_CLK_SRC>;
 786                         power-domains = <&gcc OXILI_GDSC>;
 787                         operating-points-v2 = <&gpu_opp_table>;
 788                         iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
 789                 };
 790
 791                 mdss: mdss@1a00000 {
 792                         compatible = "qcom,mdss";
 793                         reg = <0x1a00000 0x1000>,
 794                               <0x1ac8000 0x3000>;
 795                         reg-names = "mdss_phys", "vbif_phys";
 796
 797                         power-domains = <&gcc MDSS_GDSC>;
 798
 799                         clocks = <&gcc GCC_MDSS_AHB_CLK>,
 800                                  <&gcc GCC_MDSS_AXI_CLK>,
 801                                  <&gcc GCC_MDSS_VSYNC_CLK>;
 802                         clock-names = "iface_clk",
 803                                       "bus_clk",
 804                                       "vsync_clk";
 805
 806                         interrupts = <0 72 0>;
 807
 808                         interrupt-controller;
 809                         #interrupt-cells = <1>;
 810
 811                         #address-cells = <1>;
 812                         #size-cells = <1>;
 813                         ranges;
 814
 815                         mdp: mdp@1a01000 {
 816                                 compatible = "qcom,mdp5";
 817                                 reg = <0x1a01000 0x90000>;
 818                                 reg-names = "mdp_phys";
 819
 820                                 interrupt-parent = <&mdss>;
 821                                 interrupts = <0 0>;
 822
 823                                 clocks = <&gcc GCC_MDSS_AHB_CLK>,
 824                                          <&gcc GCC_MDSS_AXI_CLK>,
 825                                          <&gcc GCC_MDSS_MDP_CLK>,
 826                                          <&gcc GCC_MDSS_VSYNC_CLK>;
 827                                 clock-names = "iface_clk",
 828                                               "bus_clk",
 829                                               "core_clk",
 830                                               "vsync_clk";
 831
 832                                 iommus = <&apps_iommu 4>;
 833
 834                                 ports {
 835                                         #address-cells = <1>;
 836                                         #size-cells = <0>;
 837
 838                                         port@0 {
 839                                                 reg = <0>;
 840                                                 mdp5_intf1_out: endpoint {
 841                                                         remote-endpoint = <&dsi0_in>;
 842                                                 };
 843                                         };
 844                                 };
 845                         };
 846
 847                         dsi0: dsi@1a98000 {
 848                                 compatible = "qcom,mdss-dsi-ctrl";
 849                                 reg = <0x1a98000 0x25c>;
 850                                 reg-names = "dsi_ctrl";
 851
 852                                 interrupt-parent = <&mdss>;
 853                                 interrupts = <4 0>;
 854
 855                                 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
 856                                                   <&gcc PCLK0_CLK_SRC>;
 857                                 assigned-clock-parents = <&dsi_phy0 0>,
 858                                                          <&dsi_phy0 1>;
 859
 860                                 clocks = <&gcc GCC_MDSS_MDP_CLK>,
 861                                          <&gcc GCC_MDSS_AHB_CLK>,
 862                                          <&gcc GCC_MDSS_AXI_CLK>,
 863                                          <&gcc GCC_MDSS_BYTE0_CLK>,
 864                                          <&gcc GCC_MDSS_PCLK0_CLK>,
 865                                          <&gcc GCC_MDSS_ESC0_CLK>;
 866                                 clock-names = "mdp_core_clk",
 867                                               "iface_clk",
 868                                               "bus_clk",
 869                                               "byte_clk",
 870                                               "pixel_clk",
 871                                               "core_clk";
 872                                 phys = <&dsi_phy0>;
 873                                 phy-names = "dsi-phy";
 874
 875                                 ports {
 876                                         #address-cells = <1>;
 877                                         #size-cells = <0>;
 878
 879                                         port@0 {
 880                                                 reg = <0>;
 881                                                 dsi0_in: endpoint {
 882                                                         remote-endpoint = <&mdp5_intf1_out>;
 883                                                 };
 884                                         };
 885
 886                                         port@1 {
 887                                                 reg = <1>;
 888                                                 dsi0_out: endpoint {
 889                                                 };
 890                                         };
 891                                 };
 892                         };
 893
 894                         dsi_phy0: dsi-phy@1a98300 {
 895                                 compatible = "qcom,dsi-phy-28nm-lp";
 896                                 reg = <0x1a98300 0xd4>,
 897                                       <0x1a98500 0x280>,
 898                                       <0x1a98780 0x30>;
 899                                 reg-names = "dsi_pll",
 900                                             "dsi_phy",
 901                                             "dsi_phy_regulator";
 902
 903                                 #clock-cells = <1>;
 904
 905                                 clocks = <&gcc GCC_MDSS_AHB_CLK>;
 906                                 clock-names = "iface_clk";
 907                         };
 908                 };
 909
 910
 911                 hexagon@4080000 {
 912                         compatible = "qcom,q6v5-pil";
 913                         reg = <0x04080000 0x100>,
 914                               <0x04020000 0x040>;
 915
 916                         reg-names = "qdsp6", "rmb";
 917
 918                         interrupts-extended = <&intc 0 24 1>,
 919                                               <&hexagon_smp2p_in 0 0>,
 920                                               <&hexagon_smp2p_in 1 0>,
 921                                               <&hexagon_smp2p_in 2 0>,
 922                                               <&hexagon_smp2p_in 3 0>;
 923                         interrupt-names = "wdog", "fatal", "ready",
 924                                           "handover", "stop-ack";
 925
 926                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
 927                                  <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
 928                                  <&gcc GCC_BOOT_ROM_AHB_CLK>,
 929                                  <&xo_board>;
 930                         clock-names = "iface", "bus", "mem", "xo";
 931
 932                         qcom,smem-states = <&hexagon_smp2p_out 0>;
 933                         qcom,smem-state-names = "stop";
 934
 935                         resets = <&scm 0>;
 936                         reset-names = "mss_restart";
 937
 938                         cx-supply = <&pm8916_s1>;
 939                         mx-supply = <&pm8916_l3>;
 940                         pll-supply = <&pm8916_l7>;
 941
 942                         qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
 943
 944                         status = "disabled";
 945
 946                         mba {
 947                                 memory-region = <&mba_mem>;
 948                         };
 949
 950                         mpss {
 951                                 memory-region = <&mpss_mem>;
 952                         };
 953
 954                         smd-edge {
 955                                 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
 956
 957                                 qcom,smd-edge = <0>;
 958                                 qcom,ipc = <&apcs 8 12>;
 959                                 qcom,remote-pid = <1>;
 960
 961                                 label = "hexagon";
 962                         };
 963                 };
 964
 965                 pronto: wcnss@a21b000 {
 966                         compatible = "qcom,pronto-v2-pil", "qcom,pronto";
 967                         reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
 968                         reg-names = "ccu", "dxe", "pmu";
 969
 970                         memory-region = <&wcnss_mem>;
 971
 972                         interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
 973                                               <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
 974                                               <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
 975                                               <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
 976                                               <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
 977                         interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
 978
 979                         vddmx-supply = <&pm8916_l3>;
 980                         vddpx-supply = <&pm8916_l7>;
 981
 982                         qcom,state = <&wcnss_smp2p_out 0>;
 983                         qcom,state-names = "stop";
 984
 985                         pinctrl-names = "default";
 986                         pinctrl-0 = <&wcnss_pin_a>;
 987
 988                         status = "disabled";
 989
 990                         iris {
 991                                 compatible = "qcom,wcn3620";
 992
 993                                 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
 994                                 clock-names = "xo";
 995
 996                                 vddxo-supply = <&pm8916_l7>;
 997                                 vddrfa-supply = <&pm8916_s3>;
 998                                 vddpa-supply = <&pm8916_l9>;
 999                                 vdddig-supply = <&pm8916_l5>;
1000                         };
1001
1002                         smd-edge {
1003                                 interrupts = <0 142 1>;
1004
1005                                 qcom,ipc = <&apcs 8 17>;
1006                                 qcom,smd-edge = <6>;
1007                                 qcom,remote-pid = <4>;
1008
1009                                 label = "pronto";
1010
1011                                 wcnss {
1012                                         compatible = "qcom,wcnss";
1013                                         qcom,smd-channels = "WCNSS_CTRL";
1014
1015                                         qcom,mmio = <&pronto>;
1016
1017                                         bt {
1018                                                 compatible = "qcom,wcnss-bt";
1019                                         };
1020
1021                                         wifi {
1022                                                 compatible = "qcom,wcnss-wlan";
1023
1024                                                 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1025                                                              <0 146 IRQ_TYPE_LEVEL_HIGH>;
1026                                                 interrupt-names = "tx", "rx";
1027
1028                                                 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1029                                                 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1030                                         };
1031                                 };
1032                         };
1033                 };
1034
1035                 tpiu@820000 {
1036                         compatible = "arm,coresight-tpiu", "arm,primecell";
1037                         reg = <0x820000 0x1000>;
1038
1039                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1040                         clock-names = "apb_pclk", "atclk";
1041
1042                         port {
1043                                 tpiu_in: endpoint {
1044                                         slave-mode;
1045                                         remote-endpoint = <&replicator_out1>;
1046                                 };
1047                         };
1048                 };
1049
1050                 funnel@821000 {
1051                         compatible = "arm,coresight-funnel", "arm,primecell";
1052                         reg = <0x821000 0x1000>;
1053
1054                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1055                         clock-names = "apb_pclk", "atclk";
1056
1057                         ports {
1058                                 #address-cells = <1>;
1059                                 #size-cells = <0>;
1060
1061                                 /*
1062                                  * Not described input ports:
1063                                  * 0 - connected to Resource and Power Manger CPU ETM
1064                                  * 1 - not-connected
1065                                  * 2 - connected to Modem CPU ETM
1066                                  * 3 - not-connected
1067                                  * 5 - not-connected
1068                                  * 6 - connected trought funnel to Wireless CPU ETM
1069                                  * 7 - connected to STM component
1070                                  */
1071
1072                                 port@4 {
1073                                         reg = <4>;
1074                                         funnel0_in4: endpoint {
1075                                                 slave-mode;
1076                                                 remote-endpoint = <&funnel1_out>;
1077                                         };
1078                                 };
1079                                 port@8 {
1080                                         reg = <0>;
1081                                         funnel0_out: endpoint {
1082                                                 remote-endpoint = <&etf_in>;
1083                                         };
1084                                 };
1085                         };
1086                 };
1087
1088                 replicator@824000 {
1089                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1090                         reg = <0x824000 0x1000>;
1091
1092                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1093                         clock-names = "apb_pclk", "atclk";
1094
1095                         ports {
1096                                 #address-cells = <1>;
1097                                 #size-cells = <0>;
1098
1099                                 port@0 {
1100                                         reg = <0>;
1101                                         replicator_out0: endpoint {
1102                                                 remote-endpoint = <&etr_in>;
1103                                         };
1104                                 };
1105                                 port@1 {
1106                                         reg = <1>;
1107                                         replicator_out1: endpoint {
1108                                                 remote-endpoint = <&tpiu_in>;
1109                                         };
1110                                 };
1111                                 port@2 {
1112                                         reg = <0>;
1113                                         replicator_in: endpoint {
1114                                                 slave-mode;
1115                                                 remote-endpoint = <&etf_out>;
1116                                         };
1117                                 };
1118                         };
1119                 };
1120
1121                 etf@825000 {
1122                         compatible = "arm,coresight-tmc", "arm,primecell";
1123                         reg = <0x825000 0x1000>;
1124
1125                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1126                         clock-names = "apb_pclk", "atclk";
1127
1128                         ports {
1129                                 #address-cells = <1>;
1130                                 #size-cells = <0>;
1131
1132                                 port@0 {
1133                                         reg = <0>;
1134                                         etf_out: endpoint {
1135                                                 slave-mode;
1136                                                 remote-endpoint = <&funnel0_out>;
1137                                         };
1138                                 };
1139                                 port@1 {
1140                                         reg = <0>;
1141                                         etf_in: endpoint {
1142                                                 remote-endpoint = <&replicator_in>;
1143                                         };
1144                                 };
1145                         };
1146                 };
1147
1148                 etr@826000 {
1149                         compatible = "arm,coresight-tmc", "arm,primecell";
1150                         reg = <0x826000 0x1000>;
1151
1152                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1153                         clock-names = "apb_pclk", "atclk";
1154
1155                         port {
1156                                 etr_in: endpoint {
1157                                         slave-mode;
1158                                         remote-endpoint = <&replicator_out0>;
1159                                 };
1160                         };
1161                 };
1162
1163                 funnel@841000 { /* APSS funnel only 4 inputs are used */
1164                         compatible = "arm,coresight-funnel", "arm,primecell";
1165                         reg = <0x841000 0x1000>;
1166
1167                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1168                         clock-names = "apb_pclk", "atclk";
1169
1170                         ports {
1171                                 #address-cells = <1>;
1172                                 #size-cells = <0>;
1173
1174                                 port@0 {
1175                                         reg = <0>;
1176                                         funnel1_in0: endpoint {
1177                                                 slave-mode;
1178                                                 remote-endpoint = <&etm0_out>;
1179                                         };
1180                                 };
1181                                 port@1 {
1182                                         reg = <1>;
1183                                         funnel1_in1: endpoint {
1184                                                 slave-mode;
1185                                                 remote-endpoint = <&etm1_out>;
1186                                         };
1187                                 };
1188                                 port@2 {
1189                                         reg = <2>;
1190                                         funnel1_in2: endpoint {
1191                                                 slave-mode;
1192                                                 remote-endpoint = <&etm2_out>;
1193                                         };
1194                                 };
1195                                 port@3 {
1196                                         reg = <3>;
1197                                         funnel1_in3: endpoint {
1198                                                 slave-mode;
1199                                                 remote-endpoint = <&etm3_out>;
1200                                         };
1201                                 };
1202                                 port@4 {
1203                                         reg = <0>;
1204                                         funnel1_out: endpoint {
1205                                                 remote-endpoint = <&funnel0_in4>;
1206                                         };
1207                                 };
1208                         };
1209                 };
1210
1211                 debug@850000 {
1212                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1213                         reg = <0x850000 0x1000>;
1214                         clocks = <&rpmcc RPM_QDSS_CLK>;
1215                         clock-names = "apb_pclk";
1216                         cpu = <&CPU0>;
1217                 };
1218
1219                 debug@852000 {
1220                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1221                         reg = <0x852000 0x1000>;
1222                         clocks = <&rpmcc RPM_QDSS_CLK>;
1223                         clock-names = "apb_pclk";
1224                         cpu = <&CPU1>;
1225                 };
1226
1227                 debug@854000 {
1228                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1229                         reg = <0x854000 0x1000>;
1230                         clocks = <&rpmcc RPM_QDSS_CLK>;
1231                         clock-names = "apb_pclk";
1232                         cpu = <&CPU2>;
1233                 };
1234
1235                 debug@856000 {
1236                         compatible = "arm,coresight-cpu-debug","arm,primecell";
1237                         reg = <0x856000 0x1000>;
1238                         clocks = <&rpmcc RPM_QDSS_CLK>;
1239                         clock-names = "apb_pclk";
1240                         cpu = <&CPU3>;
1241                 };
1242
1243                 etm@85c000 {
1244                         compatible = "arm,coresight-etm4x", "arm,primecell";
1245                         reg = <0x85c000 0x1000>;
1246
1247                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1248                         clock-names = "apb_pclk", "atclk";
1249
1250                         cpu = <&CPU0>;
1251
1252                         port {
1253                                 etm0_out: endpoint {
1254                                 remote-endpoint = <&funnel1_in0>;
1255                                 };
1256                         };
1257                 };
1258
1259                 etm@85d000 {
1260                         compatible = "arm,coresight-etm4x", "arm,primecell";
1261                         reg = <0x85d000 0x1000>;
1262
1263                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1264                         clock-names = "apb_pclk", "atclk";
1265
1266                         cpu = <&CPU1>;
1267
1268                         port {
1269                                 etm1_out: endpoint {
1270                                         remote-endpoint = <&funnel1_in1>;
1271                                 };
1272                         };
1273                 };
1274
1275                 etm@85e000 {
1276                         compatible = "arm,coresight-etm4x", "arm,primecell";
1277                         reg = <0x85e000 0x1000>;
1278
1279                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1280                         clock-names = "apb_pclk", "atclk";
1281
1282                         cpu = <&CPU2>;
1283
1284                         port {
1285                                 etm2_out: endpoint {
1286                                         remote-endpoint = <&funnel1_in2>;
1287                                 };
1288                         };
1289                 };
1290
1291                 etm@85f000 {
1292                         compatible = "arm,coresight-etm4x", "arm,primecell";
1293                         reg = <0x85f000 0x1000>;
1294
1295                         clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1296                         clock-names = "apb_pclk", "atclk";
1297
1298                         cpu = <&CPU3>;
1299
1300                         port {
1301                                 etm3_out: endpoint {
1302                                         remote-endpoint = <&funnel1_in3>;
1303                                 };
1304                         };
1305                 };
1306
1307                 venus: video-codec@1d00000 {
1308                         compatible = "qcom,msm8916-venus";
1309                         reg = <0x01d00000 0xff000>;
1310                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1311                         power-domains = <&gcc VENUS_GDSC>;
1312                         clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1313                                  <&gcc GCC_VENUS0_AHB_CLK>,
1314                                  <&gcc GCC_VENUS0_AXI_CLK>;
1315                         clock-names = "core", "iface", "bus";
1316                         iommus = <&apps_iommu 5>;
1317                         memory-region = <&venus_mem>;
1318                         status = "okay";
1319
1320                         video-decoder {
1321                                 compatible = "venus-decoder";
1322                         };
1323
1324                         video-encoder {
1325                                 compatible = "venus-encoder";
1326                         };
1327                 };
1328         };
1329
1330         smd {
1331                 compatible = "qcom,smd";
1332
1333                 rpm {
1334                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1335                         qcom,ipc = <&apcs 8 0>;
1336                         qcom,smd-edge = <15>;
1337
1338                         rpm_requests {
1339                                 compatible = "qcom,rpm-msm8916";
1340                                 qcom,smd-channels = "rpm_requests";
1341
1342                                 rpmcc: qcom,rpmcc {
1343                                         compatible = "qcom,rpmcc-msm8916";
1344                                         #clock-cells = <1>;
1345                                 };
1346
1347                                 smd_rpm_regulators: pm8916-regulators {
1348                                         compatible = "qcom,rpm-pm8916-regulators";
1349
1350                                         pm8916_s1: s1 {};
1351                                         pm8916_s3: s3 {};
1352                                         pm8916_s4: s4 {};
1353
1354                                         pm8916_l1: l1 {};
1355                                         pm8916_l2: l2 {};
1356                                         pm8916_l3: l3 {};
1357                                         pm8916_l4: l4 {};
1358                                         pm8916_l5: l5 {};
1359                                         pm8916_l6: l6 {};
1360                                         pm8916_l7: l7 {};
1361                                         pm8916_l8: l8 {};
1362                                         pm8916_l9: l9 {};
1363                                         pm8916_l10: l10 {};
1364                                         pm8916_l11: l11 {};
1365                                         pm8916_l12: l12 {};
1366                                         pm8916_l13: l13 {};
1367                                         pm8916_l14: l14 {};
1368                                         pm8916_l15: l15 {};
1369                                         pm8916_l16: l16 {};
1370                                         pm8916_l17: l17 {};
1371                                         pm8916_l18: l18 {};
1372                                 };
1373                         };
1374                 };
1375         };
1376
1377         hexagon-smp2p {
1378                 compatible = "qcom,smp2p";
1379                 qcom,smem = <435>, <428>;
1380
1381                 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1382
1383                 qcom,ipc = <&apcs 8 14>;
1384
1385                 qcom,local-pid = <0>;
1386                 qcom,remote-pid = <1>;
1387
1388                 hexagon_smp2p_out: master-kernel {
1389                         qcom,entry-name = "master-kernel";
1390
1391                         #qcom,smem-state-cells = <1>;
1392                 };
1393
1394                 hexagon_smp2p_in: slave-kernel {
1395                         qcom,entry-name = "slave-kernel";
1396
1397                         interrupt-controller;
1398                         #interrupt-cells = <2>;
1399                 };
1400         };
1401
1402         wcnss-smp2p {
1403                 compatible = "qcom,smp2p";
1404                 qcom,smem = <451>, <431>;
1405
1406                 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1407
1408                 qcom,ipc = <&apcs 8 18>;
1409
1410                 qcom,local-pid = <0>;
1411                 qcom,remote-pid = <4>;
1412
1413                 wcnss_smp2p_out: master-kernel {
1414                         qcom,entry-name = "master-kernel";
1415
1416                         #qcom,smem-state-cells = <1>;
1417                 };
1418
1419                 wcnss_smp2p_in: slave-kernel {
1420                         qcom,entry-name = "slave-kernel";
1421
1422                         interrupt-controller;
1423                         #interrupt-cells = <2>;
1424                 };
1425         };
1426
1427         smsm {
1428                 compatible = "qcom,smsm";
1429
1430                 #address-cells = <1>;
1431                 #size-cells = <0>;
1432
1433                 qcom,ipc-1 = <&apcs 0 13>;
1434                 qcom,ipc-6 = <&apcs 0 19>;
1435
1436                 apps_smsm: apps@0 {
1437                         reg = <0>;
1438
1439                         #qcom,smem-state-cells = <1>;
1440                 };
1441
1442                 hexagon_smsm: hexagon@1 {
1443                         reg = <1>;
1444                         interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1445
1446                         interrupt-controller;
1447                         #interrupt-cells = <2>;
1448                 };
1449
1450                 wcnss_smsm: wcnss@6 {
1451                         reg = <6>;
1452                         interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1453
1454                         interrupt-controller;
1455                         #interrupt-cells = <2>;
1456                 };
1457         };
1458 };
1459
1460 #include "msm8916-pins.dtsi"