arch/arm64/boot/dts/qcom/msm8916.dtsi

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
  16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8916";
  20         compatible = "qcom,msm8916";
  21
  22         interrupt-parent = <&intc>;
  23
  24         #address-cells = <2>;
  25         #size-cells = <2>;
  26
  27         aliases {
  28                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  29                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  30         };
  31
  32         chosen { };
  33
  34         memory {
  35                 device_type = "memory";
  36                 /* We expect the bootloader to fill in the reg */
  37                 reg = <0 0 0 0>;
  38         };
  39
  40         reserved-memory {
  41                 #address-cells = <2>;
  42                 #size-cells = <2>;
  43                 ranges;
  44
  45                 reserve_aligned@86000000 {
  46                         reg = <0x0 0x86000000 0x0 0x0300000>;
  47                         no-map;
  48                 };
  49
  50                 smem_mem: smem_region@86300000 {
  51                         reg = <0x0 0x86300000 0x0 0x0100000>;
  52                         no-map;
  53                 };
  54         };
  55
  56         cpus {
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59
  60                 CPU0: cpu@0 {
  61                         device_type = "cpu";
  62                         compatible = "arm,cortex-a53", "arm,armv8";
  63                         reg = <0x0>;
  64                         next-level-cache = <&L2_0>;
  65                         enable-method = "psci";
  66                         cpu-idle-states = <&CPU_SPC>;
  67                 };
  68
  69                 CPU1: cpu@1 {
  70                         device_type = "cpu";
  71                         compatible = "arm,cortex-a53", "arm,armv8";
  72                         reg = <0x1>;
  73                         next-level-cache = <&L2_0>;
  74                         enable-method = "psci";
  75                         cpu-idle-states = <&CPU_SPC>;
  76                 };
  77
  78                 CPU2: cpu@2 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53", "arm,armv8";
  81                         reg = <0x2>;
  82                         next-level-cache = <&L2_0>;
  83                         enable-method = "psci";
  84                         cpu-idle-states = <&CPU_SPC>;
  85                 };
  86
  87                 CPU3: cpu@3 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53", "arm,armv8";
  90                         reg = <0x3>;
  91                         next-level-cache = <&L2_0>;
  92                         enable-method = "psci";
  93                         cpu-idle-states = <&CPU_SPC>;
  94                 };
  95
  96                 L2_0: l2-cache {
  97                       compatible = "cache";
  98                       cache-level = <2>;
  99                 };
 100
 101                 idle-states {
 102                         CPU_SPC: spc {
 103                                 compatible = "arm,idle-state";
 104                                 arm,psci-suspend-param = <0x40000002>;
 105                                 entry-latency-us = <130>;
 106                                 exit-latency-us = <150>;
 107                                 min-residency-us = <2000>;
 108                                 local-timer-stop;
 109                         };
 110                 };
 111         };
 112
 113         psci {
 114                 compatible = "arm,psci-1.0";
 115                 method = "smc";
 116         };
 117
 118         timer {
 119                 compatible = "arm,armv8-timer";
 120                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 121                              <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 122                              <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 123                              <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 124         };
 125
 126         clocks {
 127                 xo_board: xo_board {
 128                         compatible = "fixed-clock";
 129                         #clock-cells = <0>;
 130                         clock-frequency = <19200000>;
 131                 };
 132
 133                 sleep_clk: sleep_clk {
 134                         compatible = "fixed-clock";
 135                         #clock-cells = <0>;
 136                         clock-frequency = <32768>;
 137                 };
 138         };
 139
 140         smem {
 141                 compatible = "qcom,smem";
 142
 143                 memory-region = <&smem_mem>;
 144                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 145
 146                 hwlocks = <&tcsr_mutex 3>;
 147         };
 148
 149         soc: soc {
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 ranges = <0 0 0 0xffffffff>;
 153                 compatible = "simple-bus";
 154
 155                 restart@4ab000 {
 156                         compatible = "qcom,pshold";
 157                         reg = <0x4ab000 0x4>;
 158                 };
 159
 160                 msmgpio: pinctrl@1000000 {
 161                         compatible = "qcom,msm8916-pinctrl";
 162                         reg = <0x1000000 0x300000>;
 163                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 164                         gpio-controller;
 165                         #gpio-cells = <2>;
 166                         interrupt-controller;
 167                         #interrupt-cells = <2>;
 168                 };
 169
 170                 gcc: clock-controller@1800000 {
 171                         compatible = "qcom,gcc-msm8916";
 172                         #clock-cells = <1>;
 173                         #reset-cells = <1>;
 174                         #power-domain-cells = <1>;
 175                         reg = <0x1800000 0x80000>;
 176                 };
 177
 178                 tcsr_mutex_regs: syscon@1905000 {
 179                         compatible = "syscon";
 180                         reg = <0x1905000 0x20000>;
 181                 };
 182
 183                 tcsr_mutex: hwlock {
 184                         compatible = "qcom,tcsr-mutex";
 185                         syscon = <&tcsr_mutex_regs 0 0x1000>;
 186                         #hwlock-cells = <1>;
 187                 };
 188
 189                 rpm_msg_ram: memory@60000 {
 190                         compatible = "qcom,rpm-msg-ram";
 191                         reg = <0x60000 0x8000>;
 192                 };
 193
 194                 blsp1_uart1: serial@78af000 {
 195                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 196                         reg = <0x78af000 0x200>;
 197                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 198                         clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 199                         clock-names = "core", "iface";
 200                         dmas = <&blsp_dma 1>, <&blsp_dma 0>;
 201                         dma-names = "rx", "tx";
 202                         status = "disabled";
 203                 };
 204
 205                 apcs: syscon@b011000 {
 206                         compatible = "syscon";
 207                         reg = <0x0b011000 0x1000>;
 208                 };
 209
 210                 blsp1_uart2: serial@78b0000 {
 211                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 212                         reg = <0x78b0000 0x200>;
 213                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 215                         clock-names = "core", "iface";
 216                         dmas = <&blsp_dma 3>, <&blsp_dma 2>;
 217                         dma-names = "rx", "tx";
 218                         status = "disabled";
 219                 };
 220
 221                 blsp_dma: dma@7884000 {
 222                         compatible = "qcom,bam-v1.7.0";
 223                         reg = <0x07884000 0x23000>;
 224                         interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
 225                         clocks = <&gcc GCC_BLSP1_AHB_CLK>;
 226                         clock-names = "bam_clk";
 227                         #dma-cells = <1>;
 228                         qcom,ee = <0>;
 229                         status = "disabled";
 230                 };
 231
 232                 blsp_spi1: spi@78b5000 {
 233                         compatible = "qcom,spi-qup-v2.2.1";
 234                         reg = <0x078b5000 0x600>;
 235                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 236                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 237                                  <&gcc GCC_BLSP1_AHB_CLK>;
 238                         clock-names = "core", "iface";
 239                         dmas = <&blsp_dma 5>, <&blsp_dma 4>;
 240                         dma-names = "rx", "tx";
 241                         pinctrl-names = "default", "sleep";
 242                         pinctrl-0 = <&spi1_default>;
 243                         pinctrl-1 = <&spi1_sleep>;
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         status = "disabled";
 247                 };
 248
 249                 blsp_spi2: spi@78b6000 {
 250                         compatible = "qcom,spi-qup-v2.2.1";
 251                         reg = <0x078b6000 0x600>;
 252                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 253                         clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
 254                                  <&gcc GCC_BLSP1_AHB_CLK>;
 255                         clock-names = "core", "iface";
 256                         dmas = <&blsp_dma 7>, <&blsp_dma 6>;
 257                         dma-names = "rx", "tx";
 258                         pinctrl-names = "default", "sleep";
 259                         pinctrl-0 = <&spi2_default>;
 260                         pinctrl-1 = <&spi2_sleep>;
 261                         #address-cells = <1>;
 262                         #size-cells = <0>;
 263                         status = "disabled";
 264                 };
 265
 266                 blsp_spi3: spi@78b7000 {
 267                         compatible = "qcom,spi-qup-v2.2.1";
 268                         reg = <0x078b7000 0x600>;
 269                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 270                         clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 271                                  <&gcc GCC_BLSP1_AHB_CLK>;
 272                         clock-names = "core", "iface";
 273                         dmas = <&blsp_dma 9>, <&blsp_dma 8>;
 274                         dma-names = "rx", "tx";
 275                         pinctrl-names = "default", "sleep";
 276                         pinctrl-0 = <&spi3_default>;
 277                         pinctrl-1 = <&spi3_sleep>;
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                         status = "disabled";
 281                 };
 282
 283                 blsp_spi4: spi@78b8000 {
 284                         compatible = "qcom,spi-qup-v2.2.1";
 285                         reg = <0x078b8000 0x600>;
 286                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 287                         clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
 288                                  <&gcc GCC_BLSP1_AHB_CLK>;
 289                         clock-names = "core", "iface";
 290                         dmas = <&blsp_dma 11>, <&blsp_dma 10>;
 291                         dma-names = "rx", "tx";
 292                         pinctrl-names = "default", "sleep";
 293                         pinctrl-0 = <&spi4_default>;
 294                         pinctrl-1 = <&spi4_sleep>;
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         status = "disabled";
 298                 };
 299
 300                 blsp_spi5: spi@78b9000 {
 301                         compatible = "qcom,spi-qup-v2.2.1";
 302                         reg = <0x078b9000 0x600>;
 303                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 304                         clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
 305                                  <&gcc GCC_BLSP1_AHB_CLK>;
 306                         clock-names = "core", "iface";
 307                         dmas = <&blsp_dma 13>, <&blsp_dma 12>;
 308                         dma-names = "rx", "tx";
 309                         pinctrl-names = "default", "sleep";
 310                         pinctrl-0 = <&spi5_default>;
 311                         pinctrl-1 = <&spi5_sleep>;
 312                         #address-cells = <1>;
 313                         #size-cells = <0>;
 314                         status = "disabled";
 315                 };
 316
 317                 blsp_spi6: spi@78ba000 {
 318                         compatible = "qcom,spi-qup-v2.2.1";
 319                         reg = <0x078ba000 0x600>;
 320                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 321                         clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
 322                                  <&gcc GCC_BLSP1_AHB_CLK>;
 323                         clock-names = "core", "iface";
 324                         dmas = <&blsp_dma 15>, <&blsp_dma 14>;
 325                         dma-names = "rx", "tx";
 326                         pinctrl-names = "default", "sleep";
 327                         pinctrl-0 = <&spi6_default>;
 328                         pinctrl-1 = <&spi6_sleep>;
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                         status = "disabled";
 332                 };
 333
 334                 blsp_i2c2: i2c@78b6000 {
 335                         compatible = "qcom,i2c-qup-v2.2.1";
 336                         reg = <0x78b6000 0x1000>;
 337                         interrupts = <GIC_SPI 96 0>;
 338                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 339                                 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
 340                         clock-names = "iface", "core";
 341                         pinctrl-names = "default", "sleep";
 342                         pinctrl-0 = <&i2c2_default>;
 343                         pinctrl-1 = <&i2c2_sleep>;
 344                         #address-cells = <1>;
 345                         #size-cells = <0>;
 346                         status = "disabled";
 347                 };
 348
 349                 blsp_i2c4: i2c@78b8000 {
 350                         compatible = "qcom,i2c-qup-v2.2.1";
 351                         reg = <0x78b8000 0x1000>;
 352                         interrupts = <GIC_SPI 98 0>;
 353                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 354                                 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
 355                         clock-names = "iface", "core";
 356                         pinctrl-names = "default", "sleep";
 357                         pinctrl-0 = <&i2c4_default>;
 358                         pinctrl-1 = <&i2c4_sleep>;
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         status = "disabled";
 362                 };
 363
 364                 blsp_i2c6: i2c@78ba000 {
 365                         compatible = "qcom,i2c-qup-v2.2.1";
 366                         reg = <0x78ba000 0x1000>;
 367                         interrupts = <GIC_SPI 100 0>;
 368                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 369                                 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
 370                         clock-names = "iface", "core";
 371                         pinctrl-names = "default", "sleep";
 372                         pinctrl-0 = <&i2c6_default>;
 373                         pinctrl-1 = <&i2c6_sleep>;
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         status = "disabled";
 377                 };
 378
 379                 lpass: lpass@07708000 {
 380                         status = "disabled";
 381                         compatible = "qcom,lpass-cpu-apq8016";
 382                         clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
 383                                  <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
 384                                  <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
 385                                  <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
 386                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 387                                  <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
 388                                  <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
 389
 390                         clock-names = "ahbix-clk",
 391                                         "pcnoc-mport-clk",
 392                                         "pcnoc-sway-clk",
 393                                         "mi2s-bit-clk0",
 394                                         "mi2s-bit-clk1",
 395                                         "mi2s-bit-clk2",
 396                                         "mi2s-bit-clk3";
 397                         #sound-dai-cells = <1>;
 398
 399                         interrupts = <0 160 0>;
 400                         interrupt-names = "lpass-irq-lpaif";
 401                         reg = <0x07708000 0x10000>;
 402                         reg-names = "lpass-lpaif";
 403                 };
 404
 405                 sdhc_1: sdhci@07824000 {
 406                         compatible = "qcom,sdhci-msm-v4";
 407                         reg = <0x07824900 0x11c>, <0x07824000 0x800>;
 408                         reg-names = "hc_mem", "core_mem";
 409
 410                         interrupts = <0 123 0>, <0 138 0>;
 411                         interrupt-names = "hc_irq", "pwr_irq";
 412                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 413                                  <&gcc GCC_SDCC1_AHB_CLK>;
 414                         clock-names = "core", "iface";
 415                         bus-width = <8>;
 416                         non-removable;
 417                         status = "disabled";
 418                 };
 419
 420                 sdhc_2: sdhci@07864000 {
 421                         compatible = "qcom,sdhci-msm-v4";
 422                         reg = <0x07864900 0x11c>, <0x07864000 0x800>;
 423                         reg-names = "hc_mem", "core_mem";
 424
 425                         interrupts = <0 125 0>, <0 221 0>;
 426                         interrupt-names = "hc_irq", "pwr_irq";
 427                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
 428                                  <&gcc GCC_SDCC2_AHB_CLK>;
 429                         clock-names = "core", "iface";
 430                         bus-width = <4>;
 431                         status = "disabled";
 432                 };
 433
 434                 usb_dev: usb@78d9000 {
 435                         compatible = "qcom,ci-hdrc";
 436                         reg = <0x78d9000 0x400>;
 437                         dr_mode = "peripheral";
 438                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 439                         usb-phy = <&usb_otg>;
 440                         status = "disabled";
 441                 };
 442
 443                 usb_host: ehci@78d9000 {
 444                         compatible = "qcom,ehci-host";
 445                         reg = <0x78d9000 0x400>;
 446                         interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
 447                         usb-phy = <&usb_otg>;
 448                         status = "disabled";
 449                 };
 450
 451                 usb_otg: phy@78d9000 {
 452                         compatible = "qcom,usb-otg-snps";
 453                         reg = <0x78d9000 0x400>;
 454                         interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
 455                                      <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
 456
 457                         qcom,vdd-levels = <500000 1000000 1320000>;
 458                         qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
 459                         dr_mode = "peripheral";
 460                         qcom,otg-control = <2>; // PMIC
 461                         qcom,manual-pullup;
 462
 463                         clocks = <&gcc GCC_USB_HS_AHB_CLK>,
 464                                  <&gcc GCC_USB_HS_SYSTEM_CLK>,
 465                                  <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
 466                         clock-names = "iface", "core", "sleep";
 467
 468                         resets = <&gcc GCC_USB2A_PHY_BCR>,
 469                                  <&gcc GCC_USB_HS_BCR>;
 470                         reset-names = "phy", "link";
 471                         status = "disabled";
 472                 };
 473
 474                 intc: interrupt-controller@b000000 {
 475                         compatible = "qcom,msm-qgic2";
 476                         interrupt-controller;
 477                         #interrupt-cells = <3>;
 478                         reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
 479                 };
 480
 481                 timer@b020000 {
 482                         #address-cells = <1>;
 483                         #size-cells = <1>;
 484                         ranges;
 485                         compatible = "arm,armv7-timer-mem";
 486                         reg = <0xb020000 0x1000>;
 487                         clock-frequency = <19200000>;
 488
 489                         frame@b021000 {
 490                                 frame-number = <0>;
 491                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 492                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 493                                 reg = <0xb021000 0x1000>,
 494                                       <0xb022000 0x1000>;
 495                         };
 496
 497                         frame@b023000 {
 498                                 frame-number = <1>;
 499                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 500                                 reg = <0xb023000 0x1000>;
 501                                 status = "disabled";
 502                         };
 503
 504                         frame@b024000 {
 505                                 frame-number = <2>;
 506                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 507                                 reg = <0xb024000 0x1000>;
 508                                 status = "disabled";
 509                         };
 510
 511                         frame@b025000 {
 512                                 frame-number = <3>;
 513                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 514                                 reg = <0xb025000 0x1000>;
 515                                 status = "disabled";
 516                         };
 517
 518                         frame@b026000 {
 519                                 frame-number = <4>;
 520                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 521                                 reg = <0xb026000 0x1000>;
 522                                 status = "disabled";
 523                         };
 524
 525                         frame@b027000 {
 526                                 frame-number = <5>;
 527                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 528                                 reg = <0xb027000 0x1000>;
 529                                 status = "disabled";
 530                         };
 531
 532                         frame@b028000 {
 533                                 frame-number = <6>;
 534                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 535                                 reg = <0xb028000 0x1000>;
 536                                 status = "disabled";
 537                         };
 538                 };
 539
 540                 spmi_bus: spmi@200f000 {
 541                         compatible = "qcom,spmi-pmic-arb";
 542                         reg = <0x200f000 0x001000>,
 543                               <0x2400000 0x400000>,
 544                               <0x2c00000 0x400000>,
 545                               <0x3800000 0x200000>,
 546                               <0x200a000 0x002100>;
 547                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 548                         interrupt-names = "periph_irq";
 549                         interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
 550                         qcom,ee = <0>;
 551                         qcom,channel = <0>;
 552                         #address-cells = <2>;
 553                         #size-cells = <0>;
 554                         interrupt-controller;
 555                         #interrupt-cells = <4>;
 556                 };
 557
 558                 rng@22000 {
 559                         compatible = "qcom,prng";
 560                         reg = <0x00022000 0x200>;
 561                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 562                         clock-names = "core";
 563                 };
 564         };
 565
 566         smd {
 567                 compatible = "qcom,smd";
 568
 569                 rpm {
 570                         interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 571                         qcom,ipc = <&apcs 8 0>;
 572                         qcom,smd-edge = <15>;
 573
 574                         rpm_requests {
 575                                 compatible = "qcom,rpm-msm8916";
 576                                 qcom,smd-channels = "rpm_requests";
 577
 578                                 rpmcc: qcom,rpmcc {
 579                                         compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
 580                                         #clock-cells = <1>;
 581                                 };
 582
 583                                 smd_rpm_regulators: pm8916-regulators {
 584                                         compatible = "qcom,rpm-pm8916-regulators";
 585
 586                                         pm8916_s1: s1 {};
 587                                         pm8916_s3: s3 {};
 588                                         pm8916_s4: s4 {};
 589
 590                                         pm8916_l1: l1 {};
 591                                         pm8916_l2: l2 {};
 592                                         pm8916_l3: l3 {};
 593                                         pm8916_l4: l4 {};
 594                                         pm8916_l5: l5 {};
 595                                         pm8916_l6: l6 {};
 596                                         pm8916_l7: l7 {};
 597                                         pm8916_l8: l8 {};
 598                                         pm8916_l9: l9 {};
 599                                         pm8916_l10: l10 {};
 600                                         pm8916_l11: l11 {};
 601                                         pm8916_l12: l12 {};
 602                                         pm8916_l13: l13 {};
 603                                         pm8916_l14: l14 {};
 604                                         pm8916_l15: l15 {};
 605                                         pm8916_l16: l16 {};
 606                                         pm8916_l17: l17 {};
 607                                         pm8916_l18: l18 {};
 608                                 };
 609                         };
 610                 };
 611         };
 612 };
 613
 614 #include "msm8916-pins.dtsi"