1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
8 #include "mt7986b.dtsi"
11 model = "MediaTek MT7986b RFB";
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
24 device_type = "memory";
25 reg = <0 0x40000000 0 0x40000000>;
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-x";
49 compatible = "mediatek,eth-mac";
65 compatible = "mediatek,mt7531";
67 reset-gpios = <&pio 5 0>;
114 phy-mode = "2500base-x";
128 spi_flash_pins: spi-flash-pins {
131 groups = "spi0", "spi0_wp_hold";
135 spic_pins: spic-pins {
142 wf_2g_5g_pins: wf-2g-5g-pins {
145 groups = "wf_2g", "wf_5g";
148 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
149 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
150 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
151 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
152 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
153 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
154 "WF1_TOP_CLK", "WF1_TOP_DATA";
155 drive-strength = <4>;
159 wf_dbdc_pins: wf-dbdc-pins {
165 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
166 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
167 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
168 "WF0_TOP_CLK", "WF0_TOP_DATA";
169 drive-strength = <4>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&spi_flash_pins>;
181 compatible = "spi-nand";
183 spi-max-frequency = <10000000>;
184 spi-tx-bus-width = <4>;
185 spi-rx-bus-width = <4>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&spic_pins>;
210 pinctrl-names = "default", "dbdc";
211 pinctrl-0 = <&wf_2g_5g_pins>;
212 pinctrl-1 = <&wf_dbdc_pins>;