arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Device Tree For AC5.
   4  *
   5  * Copyright (C) 2021 Marvell
   6  * Copyright (C) 2022 Allied Telesis Labs
   7  */
   8
   9 #include <dt-bindings/gpio/gpio.h>
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11
  12 / {
  13         model = "Marvell AC5 SoC";
  14         compatible = "marvell,ac5";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32                 };
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a55";
  37                         reg = <0x0 0x0>;
  38                         enable-method = "psci";
  39                         next-level-cache = <&l2>;
  40                 };
  41
  42                 cpu1: cpu@1 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a55";
  45                         reg = <0x0 0x100>;
  46                         enable-method = "psci";
  47                         next-level-cache = <&l2>;
  48                 };
  49
  50                 l2: l2-cache {
  51                         compatible = "cache";
  52                         cache-level = <2>;
  53                         cache-unified;
  54                 };
  55         };
  56
  57         psci {
  58                 compatible = "arm,psci-0.2";
  59                 method = "smc";
  60         };
  61
  62         timer {
  63                 compatible = "arm,armv8-timer";
  64                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
  65                              <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
  66                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
  67                              <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
  68         };
  69
  70         pmu {
  71                 compatible = "arm,armv8-pmuv3";
  72                 interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 #address-cells = <2>;
  78                 #size-cells = <2>;
  79                 ranges;
  80                 dma-ranges;
  81
  82                 internal-regs@7f000000 {
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         compatible = "simple-bus";
  86                         /* 16M internal register @ 0x7f00_0000 */
  87                         ranges = <0x0 0x0 0x7f000000 0x1000000>;
  88                         dma-coherent;
  89
  90                         uart0: serial@12000 {
  91                                 compatible = "snps,dw-apb-uart";
  92                                 reg = <0x12000 0x100>;
  93                                 reg-shift = <2>;
  94                                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
  95                                 reg-io-width = <1>;
  96                                 clocks = <&cnm_clock>;
  97                                 status = "okay";
  98                         };
  99
 100                         uart1: serial@12100 {
 101                                 compatible = "snps,dw-apb-uart";
 102                                 reg = <0x12100 0x100>;
 103                                 reg-shift = <2>;
 104                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 105                                 reg-io-width = <1>;
 106                                 clocks = <&cnm_clock>;
 107                                 status = "disabled";
 108                         };
 109
 110                         uart2: serial@12200 {
 111                                 compatible = "snps,dw-apb-uart";
 112                                 reg = <0x12200 0x100>;
 113                                 reg-shift = <2>;
 114                                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 115                                 reg-io-width = <1>;
 116                                 clocks = <&cnm_clock>;
 117                                 status = "disabled";
 118                         };
 119
 120                         uart3: serial@12300 {
 121                                 compatible = "snps,dw-apb-uart";
 122                                 reg = <0x12300 0x100>;
 123                                 reg-shift = <2>;
 124                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 125                                 reg-io-width = <1>;
 126                                 clocks = <&cnm_clock>;
 127                                 status = "disabled";
 128                         };
 129
 130                         mdio: mdio@22004 {
 131                                 #address-cells = <1>;
 132                                 #size-cells = <0>;
 133                                 compatible = "marvell,orion-mdio";
 134                                 reg = <0x22004 0x4>;
 135                                 clocks = <&cnm_clock>;
 136                         };
 137
 138                         i2c0: i2c@11000 {
 139                                 compatible = "marvell,mv78230-i2c";
 140                                 reg = <0x11000 0x20>;
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143
 144                                 clocks = <&cnm_clock>;
 145                                 clock-names = "core";
 146                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 147                                 clock-frequency = <100000>;
 148
 149                                 pinctrl-names = "default", "gpio";
 150                                 pinctrl-0 = <&i2c0_pins>;
 151                                 pinctrl-1 = <&i2c0_gpio>;
 152                                 scl-gpios = <&gpio0 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 153                                 sda-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 154                                 status = "disabled";
 155                         };
 156
 157                         i2c1: i2c@11100 {
 158                                 compatible = "marvell,mv78230-i2c";
 159                                 reg = <0x11100 0x20>;
 160                                 #address-cells = <1>;
 161                                 #size-cells = <0>;
 162
 163                                 clocks = <&cnm_clock>;
 164                                 clock-names = "core";
 165                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 166                                 clock-frequency = <100000>;
 167
 168                                 pinctrl-names = "default", "gpio";
 169                                 pinctrl-0 = <&i2c1_pins>;
 170                                 pinctrl-1 = <&i2c1_gpio>;
 171                                 scl-gpios = <&gpio0 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 172                                 sda-gpios = <&gpio0 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 173                                 status = "disabled";
 174                         };
 175
 176                         gpio0: gpio@18100 {
 177                                 compatible = "marvell,orion-gpio";
 178                                 reg = <0x18100 0x40>;
 179                                 ngpios = <32>;
 180                                 gpio-controller;
 181                                 #gpio-cells = <2>;
 182                                 gpio-ranges = <&pinctrl0 0 0 32>;
 183                                 marvell,pwm-offset = <0x1f0>;
 184                                 interrupt-controller;
 185                                 #interrupt-cells = <2>;
 186                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 187                                              <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 188                                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 189                                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 190                         };
 191
 192                         gpio1: gpio@18140 {
 193                                 reg = <0x18140 0x40>;
 194                                 compatible = "marvell,orion-gpio";
 195                                 ngpios = <14>;
 196                                 gpio-controller;
 197                                 #gpio-cells = <2>;
 198                                 gpio-ranges = <&pinctrl0 0 32 14>;
 199                                 marvell,pwm-offset = <0x1f0>;
 200                                 interrupt-controller;
 201                                 #interrupt-cells = <2>;
 202                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
 203                                              <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 204                         };
 205                 };
 206
 207                 /*
 208                  * Dedicated section for devices behind 32bit controllers so we
 209                  * can configure specific DMA mapping for them
 210                  */
 211                 behind-32bit-controller@7f000000 {
 212                         compatible = "simple-bus";
 213                         #address-cells = <0x2>;
 214                         #size-cells = <0x2>;
 215                         ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
 216                         /* Host phy ram starts at 0x200M */
 217                         dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
 218                         dma-coherent;
 219
 220                         eth0: ethernet@20000 {
 221                                 compatible = "marvell,armada-ac5-neta";
 222                                 reg = <0x0 0x20000 0x0 0x4000>;
 223                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 224                                 clocks = <&cnm_clock>;
 225                                 phy-mode = "sgmii";
 226                                 status = "disabled";
 227                         };
 228
 229                         eth1: ethernet@24000 {
 230                                 compatible = "marvell,armada-ac5-neta";
 231                                 reg = <0x0 0x24000 0x0 0x4000>;
 232                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 233                                 clocks = <&cnm_clock>;
 234                                 phy-mode = "sgmii";
 235                                 status = "disabled";
 236                         };
 237
 238                         usb0: usb@80000 {
 239                                 compatible = "marvell,orion-ehci";
 240                                 reg = <0x0 0x80000 0x0 0x500>;
 241                                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 242                                 status = "disabled";
 243                         };
 244
 245                         usb1: usb@a0000 {
 246                                 compatible = "marvell,orion-ehci";
 247                                 reg = <0x0 0xa0000 0x0 0x500>;
 248                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 249                                 status = "disabled";
 250                         };
 251                 };
 252
 253                 pinctrl0: pinctrl@80020100 {
 254                         compatible = "marvell,ac5-pinctrl";
 255                         reg = <0 0x80020100 0 0x20>;
 256
 257                         i2c0_pins: i2c0-pins {
 258                                 marvell,pins = "mpp26", "mpp27";
 259                                 marvell,function = "i2c0";
 260                         };
 261
 262                         i2c0_gpio: i2c0-gpio-pins {
 263                                 marvell,pins = "mpp26", "mpp27";
 264                                 marvell,function = "gpio";
 265                         };
 266
 267                         i2c1_pins: i2c1-pins {
 268                                 marvell,pins = "mpp20", "mpp21";
 269                                 marvell,function = "i2c1";
 270                         };
 271
 272                         i2c1_gpio: i2c1-gpio-pins {
 273                                 marvell,pins = "mpp20", "mpp21";
 274                                 marvell,function = "i2c1";
 275                         };
 276                 };
 277
 278                 spi0: spi@805a0000 {
 279                         compatible = "marvell,armada-3700-spi";
 280                         reg = <0x0 0x805a0000 0x0 0x50>;
 281                         #address-cells = <0x1>;
 282                         #size-cells = <0x0>;
 283                         clocks = <&spi_clock>;
 284                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 285                         num-cs = <1>;
 286                         status = "disabled";
 287                 };
 288
 289                 spi1: spi@805a8000 {
 290                         compatible = "marvell,armada-3700-spi";
 291                         reg = <0x0 0x805a8000 0x0 0x50>;
 292                         #address-cells = <0x1>;
 293                         #size-cells = <0x0>;
 294                         clocks = <&spi_clock>;
 295                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 296                         num-cs = <1>;
 297                         status = "disabled";
 298                 };
 299
 300                 nand: nand-controller@805b0000 {
 301                         compatible = "marvell,ac5-nand-controller";
 302                         reg =  <0x0 0x805b0000 0x0 0x00000054>;
 303                         #address-cells = <0x1>;
 304                         #size-cells = <0x0>;
 305                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 306                         clocks = <&nand_clock>;
 307                         status = "disabled";
 308                 };
 309
 310                 gic: interrupt-controller@80600000 {
 311                         compatible = "arm,gic-v3";
 312                         #interrupt-cells = <3>;
 313                         interrupt-controller;
 314                         reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
 315                               <0x0 0x80660000 0x0 0x40000>; /* GICR */
 316                         interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 317                 };
 318         };
 319
 320         clocks {
 321                 cnm_clock: cnm-clock {
 322                         compatible = "fixed-clock";
 323                         #clock-cells = <0>;
 324                         clock-frequency = <328000000>;
 325                 };
 326
 327                 spi_clock: spi-clock {
 328                         compatible = "fixed-clock";
 329                         #clock-cells = <0>;
 330                         clock-frequency = <200000000>;
 331                 };
 332
 333                 nand_clock: nand-clock {
 334                         compatible = "fixed-clock";
 335                         #clock-cells = <0>;
 336                         clock-frequency = <400000000>;
 337                 };
 338         };
 339 };