1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
14 interrupt-parent = <&gic>;
60 compatible = "arm,cortex-a53";
62 enable-method = "psci";
63 i-cache-size = <0x8000>;
64 i-cache-line-size = <64>;
66 d-cache-size = <0x8000>;
67 d-cache-line-size = <64>;
69 next-level-cache = <&A53_L2>;
74 compatible = "arm,cortex-a53";
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
83 next-level-cache = <&A53_L2>;
88 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
97 next-level-cache = <&A53_L2>;
102 compatible = "arm,cortex-a53";
104 enable-method = "psci";
105 i-cache-size = <0x8000>;
106 i-cache-line-size = <64>;
107 i-cache-sets = <256>;
108 d-cache-size = <0x8000>;
109 d-cache-line-size = <64>;
110 d-cache-sets = <128>;
111 next-level-cache = <&A53_L2>;
116 compatible = "arm,cortex-a72";
118 enable-method = "psci";
119 i-cache-size = <0xC000>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <256>;
122 d-cache-size = <0x8000>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <256>;
125 next-level-cache = <&A72_L2>;
130 compatible = "arm,cortex-a72";
132 enable-method = "psci";
133 next-level-cache = <&A72_L2>;
137 compatible = "cache";
139 cache-size = <0x100000>;
140 cache-line-size = <64>;
145 compatible = "cache";
147 cache-size = <0x100000>;
148 cache-line-size = <64>;
153 gic: interrupt-controller@51a00000 {
154 compatible = "arm,gic-v3";
155 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
156 <0x0 0x51b00000 0 0xC0000>, /* GICR */
157 <0x0 0x52000000 0 0x2000>, /* GICC */
158 <0x0 0x52010000 0 0x1000>, /* GICH */
159 <0x0 0x52020000 0 0x20000>; /* GICV */
160 #interrupt-cells = <3>;
161 interrupt-controller;
162 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
163 interrupt-parent = <&gic>;
167 compatible = "arm,armv8-pmuv3";
168 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
172 compatible = "arm,psci-1.0";
177 compatible = "arm,armv8-timer";
178 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
179 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
180 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
181 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
185 compatible = "fsl,imx-scu";
189 mboxes = <&lsio_mu1 0 0
194 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
195 #power-domain-cells = <1>;
198 clk: clock-controller {
199 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
204 compatible = "fsl,imx8qm-iomuxc";
208 compatible = "fsl,imx8qxp-sc-rtc";
212 /* sorted in register address */
213 #include "imx8-ss-img.dtsi"
214 #include "imx8-ss-dma.dtsi"
215 #include "imx8-ss-conn.dtsi"
216 #include "imx8-ss-lsio.dtsi"
219 #include "imx8qm-ss-img.dtsi"
220 #include "imx8qm-ss-dma.dtsi"
221 #include "imx8qm-ss-conn.dtsi"
222 #include "imx8qm-ss-lsio.dtsi"