arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 /*
   3  * Copyright (C) 2019 Kontron Electronics GmbH
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mm-kontron-sl.dtsi"
   9
  10 / {
  11         model = "Kontron BL i.MX8MM (N801X S)";
  12         compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
  13
  14         aliases {
  15                 ethernet1 = &usbnet;
  16                 rtc0 = &rx8900;
  17                 rtc1 = &snvs_rtc;
  18         };
  19
  20         /* fixed crystal dedicated to mcp2515 */
  21         osc_can: clock-osc-can {
  22                 compatible = "fixed-clock";
  23                 #clock-cells = <0>;
  24                 clock-frequency = <16000000>;
  25                 clock-output-names = "osc-can";
  26         };
  27
  28         leds {
  29                 compatible = "gpio-leds";
  30                 pinctrl-names = "default";
  31                 pinctrl-0 = <&pinctrl_gpio_led>;
  32
  33                 led1 {
  34                         label = "led1";
  35                         gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
  36                         linux,default-trigger = "heartbeat";
  37                 };
  38
  39                 led2 {
  40                         label = "led2";
  41                         gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
  42                 };
  43
  44                 led3 {
  45                         label = "led3";
  46                         gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
  47                 };
  48
  49                 led4 {
  50                         label = "led4";
  51                         gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
  52                 };
  53
  54                 led5 {
  55                         label = "led5";
  56                         gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
  57                 };
  58
  59                 led6 {
  60                         label = "led6";
  61                         gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
  62                 };
  63         };
  64
  65         pwm-beeper {
  66                 compatible = "pwm-beeper";
  67                 pwms = <&pwm2 0 5000 0>;
  68         };
  69
  70         reg_rst_eth2: regulator-rst-eth2 {
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "rst-usb-eth2";
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_usb_eth2>;
  75                 gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
  76                 enable-active-high;
  77                 regulator-always-on;
  78         };
  79
  80         reg_vdd_5v: regulator-5v {
  81                 compatible = "regulator-fixed";
  82                 regulator-name = "vdd-5v";
  83                 regulator-min-microvolt = <5000000>;
  84                 regulator-max-microvolt = <5000000>;
  85         };
  86 };
  87
  88 &ecspi2 {
  89         pinctrl-names = "default";
  90         pinctrl-0 = <&pinctrl_ecspi2>;
  91         cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
  92         status = "okay";
  93
  94         can0: can@0 {
  95                 compatible = "microchip,mcp2515";
  96                 reg = <0>;
  97                 pinctrl-names = "default";
  98                 pinctrl-0 = <&pinctrl_can>;
  99                 clocks = <&osc_can>;
 100                 interrupt-parent = <&gpio4>;
 101                 interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
 102                 spi-max-frequency = <10000000>;
 103                 vdd-supply = <&reg_vdd_3v3>;
 104                 xceiver-supply = <&reg_vdd_5v>;
 105         };
 106 };
 107
 108 &ecspi3 {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_ecspi3>;
 111         cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
 112         status = "okay";
 113 };
 114
 115 &fec1 {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_enet>;
 118         phy-connection-type = "rgmii-rxid";
 119         phy-handle = <&ethphy>;
 120         status = "okay";
 121
 122         mdio {
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125
 126                 ethphy: ethernet-phy@0 {
 127                         reg = <0>;
 128                         reset-assert-us = <1>;
 129                         reset-deassert-us = <15000>;
 130                         reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
 131                 };
 132         };
 133 };
 134
 135 &i2c4 {
 136         clock-frequency = <100000>;
 137         pinctrl-names = "default";
 138         pinctrl-0 = <&pinctrl_i2c4>;
 139         status = "okay";
 140
 141         rx8900: rtc@32 {
 142                 compatible = "epson,rx8900";
 143                 reg = <0x32>;
 144         };
 145 };
 146
 147 &pwm2 {
 148         pinctrl-names = "default";
 149         pinctrl-0 = <&pinctrl_pwm2>;
 150         status = "okay";
 151 };
 152
 153 &uart1 {
 154         pinctrl-names = "default";
 155         pinctrl-0 = <&pinctrl_uart1>;
 156         uart-has-rtscts;
 157         status = "okay";
 158 };
 159
 160 &uart2 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_uart2>;
 163         linux,rs485-enabled-at-boot-time;
 164         uart-has-rtscts;
 165         status = "okay";
 166 };
 167
 168 &usbotg1 {
 169         dr_mode = "otg";
 170         over-current-active-low;
 171         status = "okay";
 172 };
 173
 174 &usbotg2 {
 175         dr_mode = "host";
 176         disable-over-current;
 177         #address-cells = <1>;
 178         #size-cells = <0>;
 179         status = "okay";
 180
 181         usb1@1 {
 182                 compatible = "usb424,9514";
 183                 reg = <1>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186
 187                 usbnet: ethernet@1 {
 188                         compatible = "usb424,ec00";
 189                         reg = <1>;
 190                         local-mac-address = [ 00 00 00 00 00 00 ];
 191                 };
 192         };
 193 };
 194
 195 &usdhc2 {
 196         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 197         pinctrl-0 = <&pinctrl_usdhc2>;
 198         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 199         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 200         vmmc-supply = <&reg_vdd_3v3>;
 201         vqmmc-supply = <&reg_nvcc_sd>;
 202         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 203         status = "okay";
 204 };
 205
 206 &iomuxc {
 207         pinctrl-names = "default";
 208         pinctrl-0 = <&pinctrl_gpio>;
 209
 210         pinctrl_can: cangrp {
 211                 fsl,pins = <
 212                         MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28               0x19
 213                 >;
 214         };
 215
 216         pinctrl_ecspi2: ecspi2grp {
 217                 fsl,pins = <
 218                         MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO            0x82
 219                         MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI            0x82
 220                         MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK            0x82
 221                         MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13              0x19
 222                 >;
 223         };
 224
 225         pinctrl_ecspi3: ecspi3grp {
 226                 fsl,pins = <
 227                         MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO              0x82
 228                         MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI              0x82
 229                         MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK              0x82
 230                         MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25               0x19
 231                 >;
 232         };
 233
 234         pinctrl_enet: enetgrp {
 235                 fsl,pins = <
 236                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 237                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 238                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 239                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 240                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 241                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 242                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 243                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 244                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 245                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 246                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 247                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 248                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 249                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 250                         MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27               0x19 /* PHY RST */
 251                         MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25                0x19 /* ETH IRQ */
 252                 >;
 253         };
 254
 255         pinctrl_gpio_led: gpioledgrp {
 256                 fsl,pins = <
 257                         MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16            0x19
 258                         MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7                0x19
 259                         MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8                0x19
 260                         MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9                0x19
 261                         MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17               0x19
 262                         MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18               0x19
 263                         MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19               0x19
 264                 >;
 265         };
 266
 267         pinctrl_gpio: gpiogrp {
 268                 fsl,pins = <
 269                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3               0x19
 270                         MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7               0x19
 271                         MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9               0x19
 272                         MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11              0x19
 273                         MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x19
 274                         MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8               0x19
 275                         MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10              0x19
 276                         MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2                0x19
 277                 >;
 278         };
 279
 280         pinctrl_i2c4: i2c4grp {
 281                 fsl,pins = <
 282                         MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                  0x40000083
 283                         MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                  0x40000083
 284                 >;
 285         };
 286
 287         pinctrl_pwm2: pwm2grp {
 288                 fsl,pins = <
 289                         MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT                  0x19
 290                 >;
 291         };
 292
 293         pinctrl_uart1: uart1grp {
 294                 fsl,pins = <
 295                         MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX              0x0
 296                         MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX             0x0
 297                         MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B          0x0
 298                         MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B          0x0
 299                 >;
 300         };
 301
 302         pinctrl_uart2: uart2grp {
 303                 fsl,pins = <
 304                         MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX             0x0
 305                         MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX              0x0
 306                         MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B           0x0
 307                         MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B           0x0
 308                 >;
 309         };
 310
 311         pinctrl_usb_eth2: usbeth2grp {
 312                 fsl,pins = <
 313                         MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2               0x19
 314                 >;
 315         };
 316
 317         pinctrl_usdhc2: usdhc2grp {
 318                 fsl,pins = <
 319                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x90
 320                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d0
 321                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d0
 322                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d0
 323                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d0
 324                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d0
 325                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
 326                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
 327                 >;
 328         };
 329
 330         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 331                 fsl,pins = <
 332                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x94
 333                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d4
 334                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d4
 335                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d4
 336                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d4
 337                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d4
 338                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
 339                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
 340                 >;
 341         };
 342
 343         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 344                 fsl,pins = <
 345                         MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                 0x96
 346                         MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                 0x1d6
 347                         MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0             0x1d6
 348                         MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1             0x1d6
 349                         MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2             0x1d6
 350                         MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3             0x1d6
 351                         MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
 352                         MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT          0xd0
 353                 >;
 354         };
 355 };