arch/arm64/boot/dts/amazon/alpine-v2.dtsi

   1 /*
   2  * Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
   3  *
   4  * Antoine Tenart <antoine.tenart@free-electrons.com>
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 /dts-v1/;
  36
  37 #include <dt-bindings/interrupt-controller/arm-gic.h>
  38
  39 / {
  40         model = "Annapurna Labs Alpine v2";
  41         compatible = "al,alpine-v2";
  42         interrupt-parent = <&gic>;
  43         #address-cells = <2>;
  44         #size-cells = <2>;
  45
  46         cpus {
  47                 #address-cells = <2>;
  48                 #size-cells = <0>;
  49
  50                 cpu@0 {
  51                         compatible = "arm,cortex-a57";
  52                         device_type = "cpu";
  53                         reg = <0x0 0x0>;
  54                         enable-method = "psci";
  55                 };
  56
  57                 cpu@1 {
  58                         compatible = "arm,cortex-a57";
  59                         device_type = "cpu";
  60                         reg = <0x0 0x1>;
  61                         enable-method = "psci";
  62                 };
  63
  64                 cpu@2 {
  65                         compatible = "arm,cortex-a57";
  66                         device_type = "cpu";
  67                         reg = <0x0 0x2>;
  68                         enable-method = "psci";
  69                 };
  70
  71                 cpu@3 {
  72                         compatible = "arm,cortex-a57";
  73                         device_type = "cpu";
  74                         reg = <0x0 0x3>;
  75                         enable-method = "psci";
  76                 };
  77         };
  78
  79         psci {
  80                 compatible = "arm,psci-0.2", "arm,psci";
  81                 method = "smc";
  82                 cpu_suspend = <0x84000001>;
  83                 cpu_off = <0x84000002>;
  84                 cpu_on = <0x84000003>;
  85         };
  86
  87         sbclk: sbclk {
  88                 compatible = "fixed-clock";
  89                 #clock-cells = <0>;
  90                 clock-frequency = <1000000>;
  91         };
  92
  93         timer {
  94                 compatible = "arm,armv8-timer";
  95                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
  96                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
  97                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
  98                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
  99         };
 100
 101         pmu {
 102                 compatible = "arm,cortex-a57-pmu";
 103                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 105                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 106                              <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 107         };
 108
 109         soc {
 110                 compatible = "simple-bus";
 111                 #address-cells = <2>;
 112                 #size-cells = <2>;
 113
 114                 interrupt-parent = <&gic>;
 115                 ranges;
 116
 117                 gic: interrupt-controller@f0200000 {
 118                         compatible = "arm,gic-v3";
 119                         reg = <0x0 0xf0200000 0x0 0x10000>,     /* GIC Dist */
 120                               <0x0 0xf0280000 0x0 0x200000>,    /* GICR */
 121                               <0x0 0xf0100000 0x0 0x2000>,      /* GICC */
 122                               <0x0 0xf0110000 0x0 0x2000>,      /* GICV */
 123                               <0x0 0xf0120000 0x0 0x2000>;      /* GICH */
 124                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 125                         interrupt-controller;
 126                         #interrupt-cells = <3>;
 127                 };
 128
 129                 pci@fbc00000 {
 130                         compatible = "pci-host-ecam-generic";
 131                         device_type = "pci";
 132                         #size-cells = <2>;
 133                         #address-cells = <3>;
 134                         #interrupt-cells = <1>;
 135                         reg = <0x0 0xfbc00000 0x0 0x100000>;
 136                         interrupt-map-mask = <0xf800 0 0 7>;
 137                         /* add legacy interrupts for SATA only */
 138                         interrupt-map = <0x4000 0 0 1 &gic 0 53 4>,
 139                                         <0x4800 0 0 1 &gic 0 54 4>;
 140                         /* 32 bit non prefetchable memory space */
 141                         ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
 142                         bus-range = <0x00 0x00>;
 143                         msi-parent = <&msix>;
 144                 };
 145
 146                 msix: msix@fbe00000 {
 147                         compatible = "al,alpine-msix";
 148                         reg = <0x0 0xfbe00000 0x0 0x100000>;
 149                         msi-controller;
 150                         al,msi-base-spi = <160>;
 151                         al,msi-num-spis = <160>;
 152                 };
 153
 154                 io-fabric@fc000000 {
 155                         compatible = "simple-bus";
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158                         ranges = <0x0 0x0 0xfc000000 0x2000000>;
 159
 160                         uart0: serial@1883000 {
 161                                 compatible = "ns16550a";
 162                                 reg = <0x1883000 0x1000>;
 163                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 164                                 clock-frequency = <500000000>;
 165                                 reg-shift = <2>;
 166                                 reg-io-width = <4>;
 167                                 status = "disabled";
 168                         };
 169
 170                         uart1: serial@1884000 {
 171                                 compatible = "ns16550a";
 172                                 reg = <0x1884000 0x1000>;
 173                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 174                                 clock-frequency = <500000000>;
 175                                 reg-shift = <2>;
 176                                 reg-io-width = <4>;
 177                                 status = "disabled";
 178                         };
 179
 180                         uart2: serial@1885000 {
 181                                 compatible = "ns16550a";
 182                                 reg = <0x1885000 0x1000>;
 183                                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 184                                 clock-frequency = <500000000>;
 185                                 reg-shift = <2>;
 186                                 reg-io-width = <4>;
 187                                 status = "disabled";
 188                         };
 189
 190                         uart3: serial@1886000 {
 191                                 compatible = "ns16550a";
 192                                 reg = <0x1886000 0x1000>;
 193                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 194                                 clock-frequency = <500000000>;
 195                                 reg-shift = <2>;
 196                                 reg-io-width = <4>;
 197                                 status = "disabled";
 198                         };
 199
 200                         timer0: timer@1890000 {
 201                                 compatible = "arm,sp804", "arm,primecell";
 202                                 reg = <0x1890000 0x1000>;
 203                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 204                                 clocks = <&sbclk>;
 205                         };
 206
 207                         timer1: timer@1891000 {
 208                                 compatible = "arm,sp804", "arm,primecell";
 209                                 reg = <0x1891000 0x1000>;
 210                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 211                                 clocks = <&sbclk>;
 212                                 status = "disabled";
 213                         };
 214
 215                         timer2: timer@1892000 {
 216                                 compatible = "arm,sp804", "arm,primecell";
 217                                 reg = <0x1892000 0x1000>;
 218                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 219                                 clocks = <&sbclk>;
 220                                 status = "disabled";
 221                         };
 222
 223                         timer3: timer@1893000 {
 224                                 compatible = "arm,sp804", "arm,primecell";
 225                                 reg = <0x1893000 0x1000>;
 226                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 227                                 clocks = <&sbclk>;
 228                                 status = "disabled";
 229                         };
 230                 };
 231         };
 232 };