2 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
32 compatible = "arm,cortex-a53", "arm,armv8";
34 enable-method = "psci";
39 compatible = "arm,cortex-a53", "arm,armv8";
41 enable-method = "psci";
46 compatible = "arm,cortex-a53", "arm,armv8";
48 enable-method = "psci";
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
61 compatible = "arm,armv8-pmuv3";
62 interrupts = <0 120 8>,
66 interrupt-affinity = <&cpu0>,
70 interrupt-parent = <&intc>;
74 compatible = "arm,psci-0.2";
79 compatible = "arm,gic-400", "arm,cortex-a15-gic";
80 #interrupt-cells = <3>;
82 reg = <0x0 0xfffc1000 0x0 0x1000>,
83 <0x0 0xfffc2000 0x0 0x2000>,
84 <0x0 0xfffc4000 0x0 0x2000>,
85 <0x0 0xfffc6000 0x0 0x2000>;
91 compatible = "simple-bus";
93 interrupt-parent = <&intc>;
94 ranges = <0 0 0 0xffffffff>;
96 clkmgr: clock-controller@ffd10000 {
97 compatible = "intel,stratix10-clkmgr";
98 reg = <0xffd10000 0x1000>;
103 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
105 compatible = "fixed-clock";
108 cb_intosc_ls_clk: cb-intosc-ls-clk {
110 compatible = "fixed-clock";
113 f2s_free_clk: f2s-free-clk {
115 compatible = "fixed-clock";
120 compatible = "fixed-clock";
124 gmac0: ethernet@ff800000 {
125 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
126 reg = <0xff800000 0x2000>;
127 interrupts = <0 90 4>;
128 interrupt-names = "macirq";
129 mac-address = [00 00 00 00 00 00];
130 resets = <&rst EMAC0_RESET>;
131 reset-names = "stmmaceth";
132 clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
133 clock-names = "stmmaceth";
137 gmac1: ethernet@ff802000 {
138 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
139 reg = <0xff802000 0x2000>;
140 interrupts = <0 91 4>;
141 interrupt-names = "macirq";
142 mac-address = [00 00 00 00 00 00];
143 resets = <&rst EMAC1_RESET>;
144 reset-names = "stmmaceth";
145 clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
146 clock-names = "stmmaceth";
150 gmac2: ethernet@ff804000 {
151 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
152 reg = <0xff804000 0x2000>;
153 interrupts = <0 92 4>;
154 interrupt-names = "macirq";
155 mac-address = [00 00 00 00 00 00];
156 resets = <&rst EMAC2_RESET>;
157 reset-names = "stmmaceth";
158 clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
159 clock-names = "stmmaceth";
163 gpio0: gpio@ffc03200 {
164 #address-cells = <1>;
166 compatible = "snps,dw-apb-gpio";
167 reg = <0xffc03200 0x100>;
168 resets = <&rst GPIO0_RESET>;
171 porta: gpio-controller@0 {
172 compatible = "snps,dw-apb-gpio-port";
175 snps,nr-gpios = <24>;
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 interrupts = <0 110 4>;
183 gpio1: gpio@ffc03300 {
184 #address-cells = <1>;
186 compatible = "snps,dw-apb-gpio";
187 reg = <0xffc03300 0x100>;
188 resets = <&rst GPIO1_RESET>;
191 portb: gpio-controller@0 {
192 compatible = "snps,dw-apb-gpio-port";
195 snps,nr-gpios = <24>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 interrupts = <0 111 4>;
204 #address-cells = <1>;
206 compatible = "snps,designware-i2c";
207 reg = <0xffc02800 0x100>;
208 interrupts = <0 103 4>;
209 resets = <&rst I2C0_RESET>;
210 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
215 #address-cells = <1>;
217 compatible = "snps,designware-i2c";
218 reg = <0xffc02900 0x100>;
219 interrupts = <0 104 4>;
220 resets = <&rst I2C1_RESET>;
221 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
226 #address-cells = <1>;
228 compatible = "snps,designware-i2c";
229 reg = <0xffc02a00 0x100>;
230 interrupts = <0 105 4>;
231 resets = <&rst I2C2_RESET>;
232 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
237 #address-cells = <1>;
239 compatible = "snps,designware-i2c";
240 reg = <0xffc02b00 0x100>;
241 interrupts = <0 106 4>;
242 resets = <&rst I2C3_RESET>;
243 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
248 #address-cells = <1>;
250 compatible = "snps,designware-i2c";
251 reg = <0xffc02c00 0x100>;
252 interrupts = <0 107 4>;
253 resets = <&rst I2C4_RESET>;
254 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
258 mmc: dwmmc0@ff808000 {
259 #address-cells = <1>;
261 compatible = "altr,socfpga-dw-mshc";
262 reg = <0xff808000 0x1000>;
263 interrupts = <0 96 4>;
264 fifo-depth = <0x400>;
265 resets = <&rst SDMMC_RESET>;
266 reset-names = "reset";
267 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
268 <&clkmgr STRATIX10_SDMMC_CLK>;
269 clock-names = "biu", "ciu";
273 ocram: sram@ffe00000 {
274 compatible = "mmio-sram";
275 reg = <0xffe00000 0x100000>;
278 pdma: pdma@ffda0000 {
279 compatible = "arm,pl330", "arm,primecell";
280 reg = <0xffda0000 0x1000>;
281 interrupts = <0 81 4>,
292 #dma-requests = <32>;
293 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
294 clock-names = "apb_pclk";
297 rst: rstmgr@ffd11000 {
299 compatible = "altr,rst-mgr";
300 reg = <0xffd11000 0x1000>;
301 altr,modrst-offset = <0x20>;
305 compatible = "snps,dw-apb-ssi";
306 #address-cells = <1>;
308 reg = <0xffda4000 0x1000>;
309 interrupts = <0 99 4>;
310 resets = <&rst SPIM0_RESET>;
317 compatible = "snps,dw-apb-ssi";
318 #address-cells = <1>;
320 reg = <0xffda5000 0x1000>;
321 interrupts = <0 100 4>;
322 resets = <&rst SPIM1_RESET>;
328 sysmgr: sysmgr@ffd12000 {
329 compatible = "altr,sys-mgr", "syscon";
330 reg = <0xffd12000 0x1000>;
335 compatible = "arm,armv8-timer";
336 interrupts = <1 13 0xf08>,
342 timer0: timer0@ffc03000 {
343 compatible = "snps,dw-apb-timer";
344 interrupts = <0 113 4>;
345 reg = <0xffc03000 0x100>;
346 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
347 clock-names = "timer";
350 timer1: timer1@ffc03100 {
351 compatible = "snps,dw-apb-timer";
352 interrupts = <0 114 4>;
353 reg = <0xffc03100 0x100>;
354 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
355 clock-names = "timer";
358 timer2: timer2@ffd00000 {
359 compatible = "snps,dw-apb-timer";
360 interrupts = <0 115 4>;
361 reg = <0xffd00000 0x100>;
362 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
363 clock-names = "timer";
366 timer3: timer3@ffd00100 {
367 compatible = "snps,dw-apb-timer";
368 interrupts = <0 116 4>;
369 reg = <0xffd00100 0x100>;
370 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
371 clock-names = "timer";
374 uart0: serial0@ffc02000 {
375 compatible = "snps,dw-apb-uart";
376 reg = <0xffc02000 0x100>;
377 interrupts = <0 108 4>;
380 resets = <&rst UART0_RESET>;
381 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
385 uart1: serial1@ffc02100 {
386 compatible = "snps,dw-apb-uart";
387 reg = <0xffc02100 0x100>;
388 interrupts = <0 109 4>;
391 resets = <&rst UART1_RESET>;
392 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
398 compatible = "usb-nop-xceiv";
403 compatible = "snps,dwc2";
404 reg = <0xffb00000 0x40000>;
405 interrupts = <0 93 4>;
407 phy-names = "usb2-phy";
408 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
409 reset-names = "dwc2", "dwc2-ecc";
414 compatible = "snps,dwc2";
415 reg = <0xffb40000 0x40000>;
416 interrupts = <0 94 4>;
418 phy-names = "usb2-phy";
419 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
420 reset-names = "dwc2", "dwc2-ecc";
424 watchdog0: watchdog@ffd00200 {
425 compatible = "snps,dw-wdt";
426 reg = <0xffd00200 0x100>;
427 interrupts = <0 117 4>;
428 resets = <&rst WATCHDOG0_RESET>;
432 watchdog1: watchdog@ffd00300 {
433 compatible = "snps,dw-wdt";
434 reg = <0xffd00300 0x100>;
435 interrupts = <0 118 4>;
436 resets = <&rst WATCHDOG1_RESET>;
440 watchdog2: watchdog@ffd00400 {
441 compatible = "snps,dw-wdt";
442 reg = <0xffd00400 0x100>;
443 interrupts = <0 125 4>;
444 resets = <&rst WATCHDOG2_RESET>;
448 watchdog3: watchdog@ffd00500 {
449 compatible = "snps,dw-wdt";
450 reg = <0xffd00500 0x100>;
451 interrupts = <0 126 4>;
452 resets = <&rst WATCHDOG3_RESET>;
457 compatible = "altr,socfpga-s10-ecc-manager";
458 interrupts = <0 15 4>, <0 95 4>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
463 compatible = "altr,sdram-edac-s10";
464 interrupts = <16 4>, <48 4>;