2 * Copyright Altera Corporation (C) 2015. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
19 #include <dt-bindings/gpio/gpio.h>
20 #include <dt-bindings/clock/stratix10-clock.h>
23 compatible = "altr,socfpga-stratix10";
32 service_reserved: svcbuffer@0 {
33 compatible = "shared-dma-pool";
34 reg = <0x0 0x0 0x0 0x1000000>;
45 compatible = "arm,cortex-a53";
47 enable-method = "psci";
52 compatible = "arm,cortex-a53";
54 enable-method = "psci";
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
66 compatible = "arm,cortex-a53";
68 enable-method = "psci";
74 compatible = "arm,armv8-pmuv3";
75 interrupts = <0 120 8>,
79 interrupt-affinity = <&cpu0>,
83 interrupt-parent = <&intc>;
87 compatible = "arm,psci-0.2";
92 compatible = "arm,gic-400", "arm,cortex-a15-gic";
93 #interrupt-cells = <3>;
95 reg = <0x0 0xfffc1000 0x0 0x1000>,
96 <0x0 0xfffc2000 0x0 0x2000>,
97 <0x0 0xfffc4000 0x0 0x2000>,
98 <0x0 0xfffc6000 0x0 0x2000>;
102 #address-cells = <1>;
104 compatible = "simple-bus";
106 interrupt-parent = <&intc>;
107 ranges = <0 0 0 0xffffffff>;
110 #address-cells = <0x1>;
113 compatible = "fpga-region";
114 fpga-mgr = <&fpga_mgr>;
117 clkmgr: clock-controller@ffd10000 {
118 compatible = "intel,stratix10-clkmgr";
119 reg = <0xffd10000 0x1000>;
124 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
126 compatible = "fixed-clock";
129 cb_intosc_ls_clk: cb-intosc-ls-clk {
131 compatible = "fixed-clock";
134 f2s_free_clk: f2s-free-clk {
136 compatible = "fixed-clock";
141 compatible = "fixed-clock";
146 compatible = "fixed-clock";
147 clock-frequency = <200000000>;
151 gmac0: ethernet@ff800000 {
152 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
153 reg = <0xff800000 0x2000>;
154 interrupts = <0 90 4>;
155 interrupt-names = "macirq";
156 mac-address = [00 00 00 00 00 00];
157 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
158 reset-names = "stmmaceth", "stmmaceth-ocp";
159 clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
160 clock-names = "stmmaceth";
161 tx-fifo-depth = <16384>;
162 rx-fifo-depth = <16384>;
163 snps,multicast-filter-bins = <256>;
168 gmac1: ethernet@ff802000 {
169 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
170 reg = <0xff802000 0x2000>;
171 interrupts = <0 91 4>;
172 interrupt-names = "macirq";
173 mac-address = [00 00 00 00 00 00];
174 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
175 reset-names = "stmmaceth", "stmmaceth-ocp";
176 clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
177 clock-names = "stmmaceth";
178 tx-fifo-depth = <16384>;
179 rx-fifo-depth = <16384>;
180 snps,multicast-filter-bins = <256>;
185 gmac2: ethernet@ff804000 {
186 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
187 reg = <0xff804000 0x2000>;
188 interrupts = <0 92 4>;
189 interrupt-names = "macirq";
190 mac-address = [00 00 00 00 00 00];
191 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
192 reset-names = "stmmaceth", "stmmaceth-ocp";
193 clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
194 clock-names = "stmmaceth";
195 tx-fifo-depth = <16384>;
196 rx-fifo-depth = <16384>;
197 snps,multicast-filter-bins = <256>;
202 gpio0: gpio@ffc03200 {
203 #address-cells = <1>;
205 compatible = "snps,dw-apb-gpio";
206 reg = <0xffc03200 0x100>;
207 resets = <&rst GPIO0_RESET>;
210 porta: gpio-controller@0 {
211 compatible = "snps,dw-apb-gpio-port";
214 snps,nr-gpios = <24>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 interrupts = <0 110 4>;
222 gpio1: gpio@ffc03300 {
223 #address-cells = <1>;
225 compatible = "snps,dw-apb-gpio";
226 reg = <0xffc03300 0x100>;
227 resets = <&rst GPIO1_RESET>;
230 portb: gpio-controller@0 {
231 compatible = "snps,dw-apb-gpio-port";
234 snps,nr-gpios = <24>;
236 interrupt-controller;
237 #interrupt-cells = <2>;
238 interrupts = <0 111 4>;
243 #address-cells = <1>;
245 compatible = "snps,designware-i2c";
246 reg = <0xffc02800 0x100>;
247 interrupts = <0 103 4>;
248 resets = <&rst I2C0_RESET>;
249 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
254 #address-cells = <1>;
256 compatible = "snps,designware-i2c";
257 reg = <0xffc02900 0x100>;
258 interrupts = <0 104 4>;
259 resets = <&rst I2C1_RESET>;
260 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
265 #address-cells = <1>;
267 compatible = "snps,designware-i2c";
268 reg = <0xffc02a00 0x100>;
269 interrupts = <0 105 4>;
270 resets = <&rst I2C2_RESET>;
271 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
276 #address-cells = <1>;
278 compatible = "snps,designware-i2c";
279 reg = <0xffc02b00 0x100>;
280 interrupts = <0 106 4>;
281 resets = <&rst I2C3_RESET>;
282 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
287 #address-cells = <1>;
289 compatible = "snps,designware-i2c";
290 reg = <0xffc02c00 0x100>;
291 interrupts = <0 107 4>;
292 resets = <&rst I2C4_RESET>;
293 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
297 mmc: dwmmc0@ff808000 {
298 #address-cells = <1>;
300 compatible = "altr,socfpga-dw-mshc";
301 reg = <0xff808000 0x1000>;
302 interrupts = <0 96 4>;
303 fifo-depth = <0x400>;
304 resets = <&rst SDMMC_RESET>;
305 reset-names = "reset";
306 clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
307 <&clkmgr STRATIX10_SDMMC_CLK>;
308 clock-names = "biu", "ciu";
313 ocram: sram@ffe00000 {
314 compatible = "mmio-sram";
315 reg = <0xffe00000 0x100000>;
318 pdma: pdma@ffda0000 {
319 compatible = "arm,pl330", "arm,primecell";
320 reg = <0xffda0000 0x1000>;
321 interrupts = <0 81 4>,
332 #dma-requests = <32>;
333 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
334 clock-names = "apb_pclk";
337 rst: rstmgr@ffd11000 {
339 compatible = "altr,stratix10-rst-mgr";
340 reg = <0xffd11000 0x1000>;
343 smmu: iommu@fa000000 {
344 compatible = "arm,mmu-500", "arm,smmu-v2";
345 reg = <0xfa000000 0x40000>;
346 #global-interrupts = <2>;
348 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
349 clock-names = "iommu";
350 interrupt-parent = <&intc>;
351 interrupts = <0 128 4>, /* Global Secure Fault */
352 <0 129 4>, /* Global Non-secure Fault */
353 /* Non-secure Context Interrupts (32) */
354 <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
355 <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
356 <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
357 <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
358 <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
359 <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
360 <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
361 <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
362 stream-match-mask = <0x7ff0>;
367 compatible = "snps,dw-apb-ssi";
368 #address-cells = <1>;
370 reg = <0xffda4000 0x1000>;
371 interrupts = <0 99 4>;
372 resets = <&rst SPIM0_RESET>;
375 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
380 compatible = "snps,dw-apb-ssi";
381 #address-cells = <1>;
383 reg = <0xffda5000 0x1000>;
384 interrupts = <0 100 4>;
385 resets = <&rst SPIM1_RESET>;
388 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
392 sysmgr: sysmgr@ffd12000 {
393 compatible = "altr,sys-mgr", "syscon";
394 reg = <0xffd12000 0x228>;
399 compatible = "arm,armv8-timer";
400 interrupts = <1 13 0xf08>,
406 timer0: timer0@ffc03000 {
407 compatible = "snps,dw-apb-timer";
408 interrupts = <0 113 4>;
409 reg = <0xffc03000 0x100>;
410 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
411 clock-names = "timer";
414 timer1: timer1@ffc03100 {
415 compatible = "snps,dw-apb-timer";
416 interrupts = <0 114 4>;
417 reg = <0xffc03100 0x100>;
418 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
419 clock-names = "timer";
422 timer2: timer2@ffd00000 {
423 compatible = "snps,dw-apb-timer";
424 interrupts = <0 115 4>;
425 reg = <0xffd00000 0x100>;
426 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
427 clock-names = "timer";
430 timer3: timer3@ffd00100 {
431 compatible = "snps,dw-apb-timer";
432 interrupts = <0 116 4>;
433 reg = <0xffd00100 0x100>;
434 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
435 clock-names = "timer";
438 uart0: serial0@ffc02000 {
439 compatible = "snps,dw-apb-uart";
440 reg = <0xffc02000 0x100>;
441 interrupts = <0 108 4>;
444 resets = <&rst UART0_RESET>;
445 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
449 uart1: serial1@ffc02100 {
450 compatible = "snps,dw-apb-uart";
451 reg = <0xffc02100 0x100>;
452 interrupts = <0 109 4>;
455 resets = <&rst UART1_RESET>;
456 clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
462 compatible = "usb-nop-xceiv";
467 compatible = "snps,dwc2";
468 reg = <0xffb00000 0x40000>;
469 interrupts = <0 93 4>;
471 phy-names = "usb2-phy";
472 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
473 reset-names = "dwc2", "dwc2-ecc";
474 clocks = <&clkmgr STRATIX10_USB_CLK>;
480 compatible = "snps,dwc2";
481 reg = <0xffb40000 0x40000>;
482 interrupts = <0 94 4>;
484 phy-names = "usb2-phy";
485 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
486 reset-names = "dwc2", "dwc2-ecc";
487 clocks = <&clkmgr STRATIX10_USB_CLK>;
492 watchdog0: watchdog@ffd00200 {
493 compatible = "snps,dw-wdt";
494 reg = <0xffd00200 0x100>;
495 interrupts = <0 117 4>;
496 resets = <&rst WATCHDOG0_RESET>;
497 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
501 watchdog1: watchdog@ffd00300 {
502 compatible = "snps,dw-wdt";
503 reg = <0xffd00300 0x100>;
504 interrupts = <0 118 4>;
505 resets = <&rst WATCHDOG1_RESET>;
506 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
510 watchdog2: watchdog@ffd00400 {
511 compatible = "snps,dw-wdt";
512 reg = <0xffd00400 0x100>;
513 interrupts = <0 125 4>;
514 resets = <&rst WATCHDOG2_RESET>;
515 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
519 watchdog3: watchdog@ffd00500 {
520 compatible = "snps,dw-wdt";
521 reg = <0xffd00500 0x100>;
522 interrupts = <0 126 4>;
523 resets = <&rst WATCHDOG3_RESET>;
524 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
529 compatible = "altr,sdr-ctl", "syscon";
530 reg = <0xf8011100 0xc0>;
534 compatible = "altr,socfpga-a10-ecc-manager";
535 altr,sysmgr-syscon = <&sysmgr>;
536 #address-cells = <1>;
538 interrupts = <0 15 4>, <0 95 4>;
539 interrupt-controller;
540 #interrupt-cells = <2>;
544 compatible = "altr,sdram-edac-s10";
545 altr,sdr-syscon = <&sdr>;
546 interrupts = <16 4>, <48 4>;
550 compatible = "altr,socfpga-usb-ecc";
551 reg = <0xff8c4000 0x100>;
552 altr,ecc-parent = <&usb0>;
557 emac0-rx-ecc@ff8c0000 {
558 compatible = "altr,socfpga-eth-mac-ecc";
559 reg = <0xff8c0000 0x100>;
560 altr,ecc-parent = <&gmac0>;
565 emac0-tx-ecc@ff8c0400 {
566 compatible = "altr,socfpga-eth-mac-ecc";
567 reg = <0xff8c0400 0x100>;
568 altr,ecc-parent = <&gmac0>;
576 compatible = "cdns,qspi-nor";
577 #address-cells = <1>;
579 reg = <0xff8d2000 0x100>,
580 <0xff900000 0x100000>;
581 interrupts = <0 3 4>;
582 cdns,fifo-depth = <128>;
583 cdns,fifo-width = <4>;
584 cdns,trigger-address = <0x00000000>;
585 clocks = <&qspi_clk>;
592 compatible = "intel,stratix10-svc";
594 memory-region = <&service_reserved>;
597 compatible = "intel,stratix10-soc-fpga-mgr";