arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi

   1 /*
   2  * Copyright (C) 2016 ARM Ltd.
   3  * based on the Allwinner H3 dtsi:
   4  *    Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/sun50i-a64-ccu.h>
  46 #include <dt-bindings/clock/sun8i-de2.h>
  47 #include <dt-bindings/clock/sun8i-r-ccu.h>
  48 #include <dt-bindings/interrupt-controller/arm-gic.h>
  49 #include <dt-bindings/reset/sun50i-a64-ccu.h>
  50 #include <dt-bindings/reset/sun8i-de2.h>
  51 #include <dt-bindings/reset/sun8i-r-ccu.h>
  52
  53 / {
  54         interrupt-parent = <&gic>;
  55         #address-cells = <1>;
  56         #size-cells = <1>;
  57
  58         chosen {
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 simplefb_lcd: framebuffer-lcd {
  64                         compatible = "allwinner,simple-framebuffer",
  65                                      "simple-framebuffer";
  66                         allwinner,pipeline = "mixer0-lcd0";
  67                         clocks = <&ccu CLK_TCON0>,
  68                                  <&display_clocks CLK_MIXER0>;
  69                         status = "disabled";
  70                 };
  71
  72                 simplefb_hdmi: framebuffer-hdmi {
  73                         compatible = "allwinner,simple-framebuffer",
  74                                      "simple-framebuffer";
  75                         allwinner,pipeline = "mixer1-lcd1-hdmi";
  76                         clocks = <&display_clocks CLK_MIXER1>,
  77                                  <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
  78                         status = "disabled";
  79                 };
  80         };
  81
  82         cpus {
  83                 #address-cells = <1>;
  84                 #size-cells = <0>;
  85
  86                 cpu0: cpu@0 {
  87                         compatible = "arm,cortex-a53", "arm,armv8";
  88                         device_type = "cpu";
  89                         reg = <0>;
  90                         enable-method = "psci";
  91                         next-level-cache = <&L2>;
  92                 };
  93
  94                 cpu1: cpu@1 {
  95                         compatible = "arm,cortex-a53", "arm,armv8";
  96                         device_type = "cpu";
  97                         reg = <1>;
  98                         enable-method = "psci";
  99                         next-level-cache = <&L2>;
 100                 };
 101
 102                 cpu2: cpu@2 {
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         device_type = "cpu";
 105                         reg = <2>;
 106                         enable-method = "psci";
 107                         next-level-cache = <&L2>;
 108                 };
 109
 110                 cpu3: cpu@3 {
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         device_type = "cpu";
 113                         reg = <3>;
 114                         enable-method = "psci";
 115                         next-level-cache = <&L2>;
 116                 };
 117
 118                 L2: l2-cache {
 119                         compatible = "cache";
 120                         cache-level = <2>;
 121                 };
 122         };
 123
 124         osc24M: osc24M_clk {
 125                 #clock-cells = <0>;
 126                 compatible = "fixed-clock";
 127                 clock-frequency = <24000000>;
 128                 clock-output-names = "osc24M";
 129         };
 130
 131         osc32k: osc32k_clk {
 132                 #clock-cells = <0>;
 133                 compatible = "fixed-clock";
 134                 clock-frequency = <32768>;
 135                 clock-output-names = "osc32k";
 136         };
 137
 138         iosc: internal-osc-clk {
 139                 #clock-cells = <0>;
 140                 compatible = "fixed-clock";
 141                 clock-frequency = <16000000>;
 142                 clock-accuracy = <300000000>;
 143                 clock-output-names = "iosc";
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-0.2";
 148                 method = "smc";
 149         };
 150
 151         sound_spdif {
 152                 compatible = "simple-audio-card";
 153                 simple-audio-card,name = "On-board SPDIF";
 154
 155                 simple-audio-card,cpu {
 156                         sound-dai = <&spdif>;
 157                 };
 158
 159                 simple-audio-card,codec {
 160                         sound-dai = <&spdif_out>;
 161                 };
 162         };
 163
 164         spdif_out: spdif-out {
 165                 #sound-dai-cells = <0>;
 166                 compatible = "linux,spdif-dit";
 167         };
 168
 169         timer {
 170                 compatible = "arm,armv8-timer";
 171                 interrupts = <GIC_PPI 13
 172                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 173                              <GIC_PPI 14
 174                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 175                              <GIC_PPI 11
 176                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 177                              <GIC_PPI 10
 178                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 179         };
 180
 181         soc {
 182                 compatible = "simple-bus";
 183                 #address-cells = <1>;
 184                 #size-cells = <1>;
 185                 ranges;
 186
 187                 de2@1000000 {
 188                         compatible = "allwinner,sun50i-a64-de2";
 189                         reg = <0x1000000 0x400000>;
 190                         allwinner,sram = <&de2_sram 1>;
 191                         #address-cells = <1>;
 192                         #size-cells = <1>;
 193                         ranges = <0 0x1000000 0x400000>;
 194
 195                         display_clocks: clock@0 {
 196                                 compatible = "allwinner,sun50i-a64-de2-clk";
 197                                 reg = <0x0 0x100000>;
 198                                 clocks = <&ccu CLK_DE>,
 199                                          <&ccu CLK_BUS_DE>;
 200                                 clock-names = "mod",
 201                                               "bus";
 202                                 resets = <&ccu RST_BUS_DE>;
 203                                 #clock-cells = <1>;
 204                                 #reset-cells = <1>;
 205                         };
 206                 };
 207
 208                 syscon: syscon@1c00000 {
 209                         compatible = "allwinner,sun50i-a64-system-control";
 210                         reg = <0x01c00000 0x1000>;
 211                         #address-cells = <1>;
 212                         #size-cells = <1>;
 213                         ranges;
 214
 215                         sram_c: sram@18000 {
 216                                 compatible = "mmio-sram";
 217                                 reg = <0x00018000 0x28000>;
 218                                 #address-cells = <1>;
 219                                 #size-cells = <1>;
 220                                 ranges = <0 0x00018000 0x28000>;
 221
 222                                 de2_sram: sram-section@0 {
 223                                         compatible = "allwinner,sun50i-a64-sram-c";
 224                                         reg = <0x0000 0x28000>;
 225                                 };
 226                         };
 227                 };
 228
 229                 dma: dma-controller@1c02000 {
 230                         compatible = "allwinner,sun50i-a64-dma";
 231                         reg = <0x01c02000 0x1000>;
 232                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 233                         clocks = <&ccu CLK_BUS_DMA>;
 234                         dma-channels = <8>;
 235                         dma-requests = <27>;
 236                         resets = <&ccu RST_BUS_DMA>;
 237                         #dma-cells = <1>;
 238                 };
 239
 240                 mmc0: mmc@1c0f000 {
 241                         compatible = "allwinner,sun50i-a64-mmc";
 242                         reg = <0x01c0f000 0x1000>;
 243                         clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
 244                         clock-names = "ahb", "mmc";
 245                         resets = <&ccu RST_BUS_MMC0>;
 246                         reset-names = "ahb";
 247                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 248                         max-frequency = <150000000>;
 249                         status = "disabled";
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                 };
 253
 254                 mmc1: mmc@1c10000 {
 255                         compatible = "allwinner,sun50i-a64-mmc";
 256                         reg = <0x01c10000 0x1000>;
 257                         clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
 258                         clock-names = "ahb", "mmc";
 259                         resets = <&ccu RST_BUS_MMC1>;
 260                         reset-names = "ahb";
 261                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 262                         max-frequency = <150000000>;
 263                         status = "disabled";
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                 };
 267
 268                 mmc2: mmc@1c11000 {
 269                         compatible = "allwinner,sun50i-a64-emmc";
 270                         reg = <0x01c11000 0x1000>;
 271                         clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
 272                         clock-names = "ahb", "mmc";
 273                         resets = <&ccu RST_BUS_MMC2>;
 274                         reset-names = "ahb";
 275                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 276                         max-frequency = <200000000>;
 277                         status = "disabled";
 278                         #address-cells = <1>;
 279                         #size-cells = <0>;
 280                 };
 281
 282                 sid: eeprom@1c14000 {
 283                         compatible = "allwinner,sun50i-a64-sid";
 284                         reg = <0x1c14000 0x400>;
 285                 };
 286
 287                 usb_otg: usb@1c19000 {
 288                         compatible = "allwinner,sun8i-a33-musb";
 289                         reg = <0x01c19000 0x0400>;
 290                         clocks = <&ccu CLK_BUS_OTG>;
 291                         resets = <&ccu RST_BUS_OTG>;
 292                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 293                         interrupt-names = "mc";
 294                         phys = <&usbphy 0>;
 295                         phy-names = "usb";
 296                         extcon = <&usbphy 0>;
 297                         status = "disabled";
 298                 };
 299
 300                 usbphy: phy@1c19400 {
 301                         compatible = "allwinner,sun50i-a64-usb-phy";
 302                         reg = <0x01c19400 0x14>,
 303                               <0x01c1a800 0x4>,
 304                               <0x01c1b800 0x4>;
 305                         reg-names = "phy_ctrl",
 306                                     "pmu0",
 307                                     "pmu1";
 308                         clocks = <&ccu CLK_USB_PHY0>,
 309                                  <&ccu CLK_USB_PHY1>;
 310                         clock-names = "usb0_phy",
 311                                       "usb1_phy";
 312                         resets = <&ccu RST_USB_PHY0>,
 313                                  <&ccu RST_USB_PHY1>;
 314                         reset-names = "usb0_reset",
 315                                       "usb1_reset";
 316                         status = "disabled";
 317                         #phy-cells = <1>;
 318                 };
 319
 320                 ehci0: usb@1c1a000 {
 321                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 322                         reg = <0x01c1a000 0x100>;
 323                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 324                         clocks = <&ccu CLK_BUS_OHCI0>,
 325                                  <&ccu CLK_BUS_EHCI0>,
 326                                  <&ccu CLK_USB_OHCI0>;
 327                         resets = <&ccu RST_BUS_OHCI0>,
 328                                  <&ccu RST_BUS_EHCI0>;
 329                         status = "disabled";
 330                 };
 331
 332                 ohci0: usb@1c1a400 {
 333                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 334                         reg = <0x01c1a400 0x100>;
 335                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 336                         clocks = <&ccu CLK_BUS_OHCI0>,
 337                                  <&ccu CLK_USB_OHCI0>;
 338                         resets = <&ccu RST_BUS_OHCI0>;
 339                         status = "disabled";
 340                 };
 341
 342                 ehci1: usb@1c1b000 {
 343                         compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 344                         reg = <0x01c1b000 0x100>;
 345                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 346                         clocks = <&ccu CLK_BUS_OHCI1>,
 347                                  <&ccu CLK_BUS_EHCI1>,
 348                                  <&ccu CLK_USB_OHCI1>;
 349                         resets = <&ccu RST_BUS_OHCI1>,
 350                                  <&ccu RST_BUS_EHCI1>;
 351                         phys = <&usbphy 1>;
 352                         phy-names = "usb";
 353                         status = "disabled";
 354                 };
 355
 356                 ohci1: usb@1c1b400 {
 357                         compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
 358                         reg = <0x01c1b400 0x100>;
 359                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 360                         clocks = <&ccu CLK_BUS_OHCI1>,
 361                                  <&ccu CLK_USB_OHCI1>;
 362                         resets = <&ccu RST_BUS_OHCI1>;
 363                         phys = <&usbphy 1>;
 364                         phy-names = "usb";
 365                         status = "disabled";
 366                 };
 367
 368                 ccu: clock@1c20000 {
 369                         compatible = "allwinner,sun50i-a64-ccu";
 370                         reg = <0x01c20000 0x400>;
 371                         clocks = <&osc24M>, <&osc32k>;
 372                         clock-names = "hosc", "losc";
 373                         #clock-cells = <1>;
 374                         #reset-cells = <1>;
 375                 };
 376
 377                 pio: pinctrl@1c20800 {
 378                         compatible = "allwinner,sun50i-a64-pinctrl";
 379                         reg = <0x01c20800 0x400>;
 380                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 381                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 382                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&ccu 58>;
 384                         gpio-controller;
 385                         #gpio-cells = <3>;
 386                         interrupt-controller;
 387                         #interrupt-cells = <3>;
 388
 389                         i2c0_pins: i2c0_pins {
 390                                 pins = "PH0", "PH1";
 391                                 function = "i2c0";
 392                         };
 393
 394                         i2c1_pins: i2c1_pins {
 395                                 pins = "PH2", "PH3";
 396                                 function = "i2c1";
 397                         };
 398
 399                         mmc0_pins: mmc0-pins {
 400                                 pins = "PF0", "PF1", "PF2", "PF3",
 401                                        "PF4", "PF5";
 402                                 function = "mmc0";
 403                                 drive-strength = <30>;
 404                                 bias-pull-up;
 405                         };
 406
 407                         mmc1_pins: mmc1-pins {
 408                                 pins = "PG0", "PG1", "PG2", "PG3",
 409                                        "PG4", "PG5";
 410                                 function = "mmc1";
 411                                 drive-strength = <30>;
 412                                 bias-pull-up;
 413                         };
 414
 415                         mmc2_pins: mmc2-pins {
 416                                 pins = "PC5", "PC6", "PC8", "PC9",
 417                                        "PC10","PC11", "PC12", "PC13",
 418                                        "PC14", "PC15", "PC16";
 419                                 function = "mmc2";
 420                                 drive-strength = <30>;
 421                                 bias-pull-up;
 422                         };
 423
 424                         mmc2_ds_pin: mmc2-ds-pin {
 425                                 pins = "PC1";
 426                                 function = "mmc2";
 427                                 drive-strength = <30>;
 428                                 bias-pull-up;
 429                         };
 430
 431                         pwm_pin: pwm_pin {
 432                                 pins = "PD22";
 433                                 function = "pwm";
 434                         };
 435
 436                         rmii_pins: rmii_pins {
 437                                 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
 438                                        "PD18", "PD19", "PD20", "PD22", "PD23";
 439                                 function = "emac";
 440                                 drive-strength = <40>;
 441                         };
 442
 443                         rgmii_pins: rgmii_pins {
 444                                 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
 445                                        "PD13", "PD15", "PD16", "PD17", "PD18",
 446                                        "PD19", "PD20", "PD21", "PD22", "PD23";
 447                                 function = "emac";
 448                                 drive-strength = <40>;
 449                         };
 450
 451                         spdif_tx_pin: spdif {
 452                                 pins = "PH8";
 453                                 function = "spdif";
 454                         };
 455
 456                         spi0_pins: spi0 {
 457                                 pins = "PC0", "PC1", "PC2", "PC3";
 458                                 function = "spi0";
 459                         };
 460
 461                         spi1_pins: spi1 {
 462                                 pins = "PD0", "PD1", "PD2", "PD3";
 463                                 function = "spi1";
 464                         };
 465
 466                         uart0_pins_a: uart0 {
 467                                 pins = "PB8", "PB9";
 468                                 function = "uart0";
 469                         };
 470
 471                         uart1_pins: uart1_pins {
 472                                 pins = "PG6", "PG7";
 473                                 function = "uart1";
 474                         };
 475
 476                         uart1_rts_cts_pins: uart1_rts_cts_pins {
 477                                 pins = "PG8", "PG9";
 478                                 function = "uart1";
 479                         };
 480
 481                         uart2_pins: uart2-pins {
 482                                 pins = "PB0", "PB1";
 483                                 function = "uart2";
 484                         };
 485
 486                         uart3_pins: uart3-pins {
 487                                 pins = "PD0", "PD1";
 488                                 function = "uart3";
 489                         };
 490
 491                         uart4_pins: uart4-pins {
 492                                 pins = "PD2", "PD3";
 493                                 function = "uart4";
 494                         };
 495
 496                         uart4_rts_cts_pins: uart4-rts-cts-pins {
 497                                 pins = "PD4", "PD5";
 498                                 function = "uart4";
 499                         };
 500                 };
 501
 502                 spdif: spdif@1c21000 {
 503                         #sound-dai-cells = <0>;
 504                         compatible = "allwinner,sun50i-a64-spdif",
 505                                      "allwinner,sun8i-h3-spdif";
 506                         reg = <0x01c21000 0x400>;
 507                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 508                         clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
 509                         resets = <&ccu RST_BUS_SPDIF>;
 510                         clock-names = "apb", "spdif";
 511                         dmas = <&dma 2>;
 512                         dma-names = "tx";
 513                         pinctrl-names = "default";
 514                         pinctrl-0 = <&spdif_tx_pin>;
 515                         status = "disabled";
 516                 };
 517
 518                 i2s0: i2s@1c22000 {
 519                         #sound-dai-cells = <0>;
 520                         compatible = "allwinner,sun50i-a64-i2s",
 521                                      "allwinner,sun8i-h3-i2s";
 522                         reg = <0x01c22000 0x400>;
 523                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
 525                         clock-names = "apb", "mod";
 526                         resets = <&ccu RST_BUS_I2S0>;
 527                         dma-names = "rx", "tx";
 528                         dmas = <&dma 3>, <&dma 3>;
 529                         status = "disabled";
 530                 };
 531
 532                 i2s1: i2s@1c22400 {
 533                         #sound-dai-cells = <0>;
 534                         compatible = "allwinner,sun50i-a64-i2s",
 535                                      "allwinner,sun8i-h3-i2s";
 536                         reg = <0x01c22400 0x400>;
 537                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
 539                         clock-names = "apb", "mod";
 540                         resets = <&ccu RST_BUS_I2S1>;
 541                         dma-names = "rx", "tx";
 542                         dmas = <&dma 4>, <&dma 4>;
 543                         status = "disabled";
 544                 };
 545
 546                 uart0: serial@1c28000 {
 547                         compatible = "snps,dw-apb-uart";
 548                         reg = <0x01c28000 0x400>;
 549                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 550                         reg-shift = <2>;
 551                         reg-io-width = <4>;
 552                         clocks = <&ccu CLK_BUS_UART0>;
 553                         resets = <&ccu RST_BUS_UART0>;
 554                         status = "disabled";
 555                 };
 556
 557                 uart1: serial@1c28400 {
 558                         compatible = "snps,dw-apb-uart";
 559                         reg = <0x01c28400 0x400>;
 560                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 561                         reg-shift = <2>;
 562                         reg-io-width = <4>;
 563                         clocks = <&ccu CLK_BUS_UART1>;
 564                         resets = <&ccu RST_BUS_UART1>;
 565                         status = "disabled";
 566                 };
 567
 568                 uart2: serial@1c28800 {
 569                         compatible = "snps,dw-apb-uart";
 570                         reg = <0x01c28800 0x400>;
 571                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 572                         reg-shift = <2>;
 573                         reg-io-width = <4>;
 574                         clocks = <&ccu CLK_BUS_UART2>;
 575                         resets = <&ccu RST_BUS_UART2>;
 576                         status = "disabled";
 577                 };
 578
 579                 uart3: serial@1c28c00 {
 580                         compatible = "snps,dw-apb-uart";
 581                         reg = <0x01c28c00 0x400>;
 582                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 583                         reg-shift = <2>;
 584                         reg-io-width = <4>;
 585                         clocks = <&ccu CLK_BUS_UART3>;
 586                         resets = <&ccu RST_BUS_UART3>;
 587                         status = "disabled";
 588                 };
 589
 590                 uart4: serial@1c29000 {
 591                         compatible = "snps,dw-apb-uart";
 592                         reg = <0x01c29000 0x400>;
 593                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 594                         reg-shift = <2>;
 595                         reg-io-width = <4>;
 596                         clocks = <&ccu CLK_BUS_UART4>;
 597                         resets = <&ccu RST_BUS_UART4>;
 598                         status = "disabled";
 599                 };
 600
 601                 i2c0: i2c@1c2ac00 {
 602                         compatible = "allwinner,sun6i-a31-i2c";
 603                         reg = <0x01c2ac00 0x400>;
 604                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 605                         clocks = <&ccu CLK_BUS_I2C0>;
 606                         resets = <&ccu RST_BUS_I2C0>;
 607                         status = "disabled";
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                 };
 611
 612                 i2c1: i2c@1c2b000 {
 613                         compatible = "allwinner,sun6i-a31-i2c";
 614                         reg = <0x01c2b000 0x400>;
 615                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&ccu CLK_BUS_I2C1>;
 617                         resets = <&ccu RST_BUS_I2C1>;
 618                         status = "disabled";
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                 };
 622
 623                 i2c2: i2c@1c2b400 {
 624                         compatible = "allwinner,sun6i-a31-i2c";
 625                         reg = <0x01c2b400 0x400>;
 626                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 627                         clocks = <&ccu CLK_BUS_I2C2>;
 628                         resets = <&ccu RST_BUS_I2C2>;
 629                         status = "disabled";
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632                 };
 633
 634
 635                 spi0: spi@1c68000 {
 636                         compatible = "allwinner,sun8i-h3-spi";
 637                         reg = <0x01c68000 0x1000>;
 638                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 639                         clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
 640                         clock-names = "ahb", "mod";
 641                         dmas = <&dma 23>, <&dma 23>;
 642                         dma-names = "rx", "tx";
 643                         pinctrl-names = "default";
 644                         pinctrl-0 = <&spi0_pins>;
 645                         resets = <&ccu RST_BUS_SPI0>;
 646                         status = "disabled";
 647                         num-cs = <1>;
 648                         #address-cells = <1>;
 649                         #size-cells = <0>;
 650                 };
 651
 652                 spi1: spi@1c69000 {
 653                         compatible = "allwinner,sun8i-h3-spi";
 654                         reg = <0x01c69000 0x1000>;
 655                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 656                         clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
 657                         clock-names = "ahb", "mod";
 658                         dmas = <&dma 24>, <&dma 24>;
 659                         dma-names = "rx", "tx";
 660                         pinctrl-names = "default";
 661                         pinctrl-0 = <&spi1_pins>;
 662                         resets = <&ccu RST_BUS_SPI1>;
 663                         status = "disabled";
 664                         num-cs = <1>;
 665                         #address-cells = <1>;
 666                         #size-cells = <0>;
 667                 };
 668
 669                 emac: ethernet@1c30000 {
 670                         compatible = "allwinner,sun50i-a64-emac";
 671                         syscon = <&syscon>;
 672                         reg = <0x01c30000 0x10000>;
 673                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 674                         interrupt-names = "macirq";
 675                         resets = <&ccu RST_BUS_EMAC>;
 676                         reset-names = "stmmaceth";
 677                         clocks = <&ccu CLK_BUS_EMAC>;
 678                         clock-names = "stmmaceth";
 679                         status = "disabled";
 680
 681                         mdio: mdio {
 682                                 compatible = "snps,dwmac-mdio";
 683                                 #address-cells = <1>;
 684                                 #size-cells = <0>;
 685                         };
 686                 };
 687
 688                 gic: interrupt-controller@1c81000 {
 689                         compatible = "arm,gic-400";
 690                         reg = <0x01c81000 0x1000>,
 691                               <0x01c82000 0x2000>,
 692                               <0x01c84000 0x2000>,
 693                               <0x01c86000 0x2000>;
 694                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 695                         interrupt-controller;
 696                         #interrupt-cells = <3>;
 697                 };
 698
 699                 pwm: pwm@1c21400 {
 700                         compatible = "allwinner,sun50i-a64-pwm",
 701                                      "allwinner,sun5i-a13-pwm";
 702                         reg = <0x01c21400 0x400>;
 703                         clocks = <&osc24M>;
 704                         pinctrl-names = "default";
 705                         pinctrl-0 = <&pwm_pin>;
 706                         #pwm-cells = <3>;
 707                         status = "disabled";
 708                 };
 709
 710                 rtc: rtc@1f00000 {
 711                         compatible = "allwinner,sun6i-a31-rtc";
 712                         reg = <0x01f00000 0x54>;
 713                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 715                         clock-output-names = "rtc-osc32k", "rtc-osc32k-out";
 716                         clocks = <&osc32k>;
 717                         #clock-cells = <1>;
 718                 };
 719
 720                 r_intc: interrupt-controller@1f00c00 {
 721                         compatible = "allwinner,sun50i-a64-r-intc",
 722                                      "allwinner,sun6i-a31-r-intc";
 723                         interrupt-controller;
 724                         #interrupt-cells = <2>;
 725                         reg = <0x01f00c00 0x400>;
 726                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 727                 };
 728
 729                 r_ccu: clock@1f01400 {
 730                         compatible = "allwinner,sun50i-a64-r-ccu";
 731                         reg = <0x01f01400 0x100>;
 732                         clocks = <&osc24M>, <&osc32k>, <&iosc>,
 733                                  <&ccu 11>;
 734                         clock-names = "hosc", "losc", "iosc", "pll-periph";
 735                         #clock-cells = <1>;
 736                         #reset-cells = <1>;
 737                 };
 738
 739                 r_i2c: i2c@1f02400 {
 740                         compatible = "allwinner,sun50i-a64-i2c",
 741                                      "allwinner,sun6i-a31-i2c";
 742                         reg = <0x01f02400 0x400>;
 743                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 744                         clocks = <&r_ccu CLK_APB0_I2C>;
 745                         resets = <&r_ccu RST_APB0_I2C>;
 746                         status = "disabled";
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749                 };
 750
 751                 r_pwm: pwm@1f03800 {
 752                         compatible = "allwinner,sun50i-a64-pwm",
 753                                      "allwinner,sun5i-a13-pwm";
 754                         reg = <0x01f03800 0x400>;
 755                         clocks = <&osc24M>;
 756                         pinctrl-names = "default";
 757                         pinctrl-0 = <&r_pwm_pin>;
 758                         #pwm-cells = <3>;
 759                         status = "disabled";
 760                 };
 761
 762                 r_pio: pinctrl@1f02c00 {
 763                         compatible = "allwinner,sun50i-a64-r-pinctrl";
 764                         reg = <0x01f02c00 0x400>;
 765                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 766                         clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 767                         clock-names = "apb", "hosc", "losc";
 768                         gpio-controller;
 769                         #gpio-cells = <3>;
 770                         interrupt-controller;
 771                         #interrupt-cells = <3>;
 772
 773                         r_i2c_pins_a: i2c-a {
 774                                 pins = "PL8", "PL9";
 775                                 function = "s_i2c";
 776                         };
 777
 778                         r_pwm_pin: pwm {
 779                                 pins = "PL10";
 780                                 function = "s_pwm";
 781                         };
 782
 783                         r_rsb_pins: rsb {
 784                                 pins = "PL0", "PL1";
 785                                 function = "s_rsb";
 786                         };
 787                 };
 788
 789                 r_rsb: rsb@1f03400 {
 790                         compatible = "allwinner,sun8i-a23-rsb";
 791                         reg = <0x01f03400 0x400>;
 792                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 793                         clocks = <&r_ccu 6>;
 794                         clock-frequency = <3000000>;
 795                         resets = <&r_ccu 2>;
 796                         pinctrl-names = "default";
 797                         pinctrl-0 = <&r_rsb_pins>;
 798                         status = "disabled";
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801                 };
 802
 803                 wdt0: watchdog@1c20ca0 {
 804                         compatible = "allwinner,sun50i-a64-wdt",
 805                                      "allwinner,sun6i-a31-wdt";
 806                         reg = <0x01c20ca0 0x20>;
 807                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 808                 };
 809         };
 810 };