arch/arm/mm/mm-armv.c

   1 /*
   2  *  linux/arch/arm/mm/mm-armv.c
   3  *
   4  *  Copyright (C) 1998-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  Page table sludge for ARM v3 and v4 processor architectures.
  11  */
  12 #include <linux/config.h>
  13 #include <linux/module.h>
  14 #include <linux/mm.h>
  15 #include <linux/init.h>
  16 #include <linux/bootmem.h>
  17 #include <linux/highmem.h>
  18 #include <linux/nodemask.h>
  19
  20 #include <asm/pgalloc.h>
  21 #include <asm/page.h>
  22 #include <asm/setup.h>
  23 #include <asm/tlbflush.h>
  24
  25 #include <asm/mach/map.h>
  26
  27 #define CPOLICY_UNCACHED        0
  28 #define CPOLICY_BUFFERED        1
  29 #define CPOLICY_WRITETHROUGH    2
  30 #define CPOLICY_WRITEBACK       3
  31 #define CPOLICY_WRITEALLOC      4
  32
  33 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  34 static unsigned int ecc_mask __initdata = 0;
  35 pgprot_t pgprot_kernel;
  36
  37 EXPORT_SYMBOL(pgprot_kernel);
  38
  39 pmd_t *top_pmd;
  40
  41 struct cachepolicy {
  42         const char      policy[16];
  43         unsigned int    cr_mask;
  44         unsigned int    pmd;
  45         unsigned int    pte;
  46 };
  47
  48 static struct cachepolicy cache_policies[] __initdata = {
  49         {
  50                 .policy         = "uncached",
  51                 .cr_mask        = CR_W|CR_C,
  52                 .pmd            = PMD_SECT_UNCACHED,
  53                 .pte            = 0,
  54         }, {
  55                 .policy         = "buffered",
  56                 .cr_mask        = CR_C,
  57                 .pmd            = PMD_SECT_BUFFERED,
  58                 .pte            = PTE_BUFFERABLE,
  59         }, {
  60                 .policy         = "writethrough",
  61                 .cr_mask        = 0,
  62                 .pmd            = PMD_SECT_WT,
  63                 .pte            = PTE_CACHEABLE,
  64         }, {
  65                 .policy         = "writeback",
  66                 .cr_mask        = 0,
  67                 .pmd            = PMD_SECT_WB,
  68                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  69         }, {
  70                 .policy         = "writealloc",
  71                 .cr_mask        = 0,
  72                 .pmd            = PMD_SECT_WBWA,
  73                 .pte            = PTE_BUFFERABLE|PTE_CACHEABLE,
  74         }
  75 };
  76
  77 /*
  78  * These are useful for identifing cache coherency
  79  * problems by allowing the cache or the cache and
  80  * writebuffer to be turned off.  (Note: the write
  81  * buffer should not be on and the cache off).
  82  */
  83 static void __init early_cachepolicy(char **p)
  84 {
  85         int i;
  86
  87         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
  88                 int len = strlen(cache_policies[i].policy);
  89
  90                 if (memcmp(*p, cache_policies[i].policy, len) == 0) {
  91                         cachepolicy = i;
  92                         cr_alignment &= ~cache_policies[i].cr_mask;
  93                         cr_no_alignment &= ~cache_policies[i].cr_mask;
  94                         *p += len;
  95                         break;
  96                 }
  97         }
  98         if (i == ARRAY_SIZE(cache_policies))
  99                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 100         flush_cache_all();
 101         set_cr(cr_alignment);
 102 }
 103
 104 static void __init early_nocache(char **__unused)
 105 {
 106         char *p = "buffered";
 107         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 108         early_cachepolicy(&p);
 109 }
 110
 111 static void __init early_nowrite(char **__unused)
 112 {
 113         char *p = "uncached";
 114         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 115         early_cachepolicy(&p);
 116 }
 117
 118 static void __init early_ecc(char **p)
 119 {
 120         if (memcmp(*p, "on", 2) == 0) {
 121                 ecc_mask = PMD_PROTECTION;
 122                 *p += 2;
 123         } else if (memcmp(*p, "off", 3) == 0) {
 124                 ecc_mask = 0;
 125                 *p += 3;
 126         }
 127 }
 128
 129 __early_param("nocache", early_nocache);
 130 __early_param("nowb", early_nowrite);
 131 __early_param("cachepolicy=", early_cachepolicy);
 132 __early_param("ecc=", early_ecc);
 133
 134 static int __init noalign_setup(char *__unused)
 135 {
 136         cr_alignment &= ~CR_A;
 137         cr_no_alignment &= ~CR_A;
 138         set_cr(cr_alignment);
 139         return 1;
 140 }
 141
 142 __setup("noalign", noalign_setup);
 143
 144 #define FIRST_KERNEL_PGD_NR     (FIRST_USER_PGD_NR + USER_PTRS_PER_PGD)
 145
 146 static inline pmd_t *pmd_off(pgd_t *pgd, unsigned long virt)
 147 {
 148         return pmd_offset(pgd, virt);
 149 }
 150
 151 static inline pmd_t *pmd_off_k(unsigned long virt)
 152 {
 153         return pmd_off(pgd_offset_k(virt), virt);
 154 }
 155
 156 /*
 157  * need to get a 16k page for level 1
 158  */
 159 pgd_t *get_pgd_slow(struct mm_struct *mm)
 160 {
 161         pgd_t *new_pgd, *init_pgd;
 162         pmd_t *new_pmd, *init_pmd;
 163         pte_t *new_pte, *init_pte;
 164
 165         new_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL, 2);
 166         if (!new_pgd)
 167                 goto no_pgd;
 168
 169         memzero(new_pgd, FIRST_KERNEL_PGD_NR * sizeof(pgd_t));
 170
 171         /*
 172          * Copy over the kernel and IO PGD entries
 173          */
 174         init_pgd = pgd_offset_k(0);
 175         memcpy(new_pgd + FIRST_KERNEL_PGD_NR, init_pgd + FIRST_KERNEL_PGD_NR,
 176                        (PTRS_PER_PGD - FIRST_KERNEL_PGD_NR) * sizeof(pgd_t));
 177
 178         clean_dcache_area(new_pgd, PTRS_PER_PGD * sizeof(pgd_t));
 179
 180         if (!vectors_high()) {
 181                 /*
 182                  * On ARM, first page must always be allocated since it
 183                  * contains the machine vectors.
 184                  */
 185                 new_pmd = pmd_alloc(mm, new_pgd, 0);
 186                 if (!new_pmd)
 187                         goto no_pmd;
 188
 189                 new_pte = pte_alloc_map(mm, new_pmd, 0);
 190                 if (!new_pte)
 191                         goto no_pte;
 192
 193                 init_pmd = pmd_offset(init_pgd, 0);
 194                 init_pte = pte_offset_map_nested(init_pmd, 0);
 195                 set_pte(new_pte, *init_pte);
 196                 pte_unmap_nested(init_pte);
 197                 pte_unmap(new_pte);
 198         }
 199
 200         return new_pgd;
 201
 202 no_pte:
 203         pmd_free(new_pmd);
 204 no_pmd:
 205         free_pages((unsigned long)new_pgd, 2);
 206 no_pgd:
 207         return NULL;
 208 }
 209
 210 void free_pgd_slow(pgd_t *pgd)
 211 {
 212         pmd_t *pmd;
 213         struct page *pte;
 214
 215         if (!pgd)
 216                 return;
 217
 218         /* pgd is always present and good */
 219         pmd = pmd_off(pgd, 0);
 220         if (pmd_none(*pmd))
 221                 goto free;
 222         if (pmd_bad(*pmd)) {
 223                 pmd_ERROR(*pmd);
 224                 pmd_clear(pmd);
 225                 goto free;
 226         }
 227
 228         pte = pmd_page(*pmd);
 229         pmd_clear(pmd);
 230         dec_page_state(nr_page_table_pages);
 231         pte_lock_deinit(pte);
 232         pte_free(pte);
 233         pmd_free(pmd);
 234 free:
 235         free_pages((unsigned long) pgd, 2);
 236 }
 237
 238 /*
 239  * Create a SECTION PGD between VIRT and PHYS in domain
 240  * DOMAIN with protection PROT.  This operates on half-
 241  * pgdir entry increments.
 242  */
 243 static inline void
 244 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
 245 {
 246         pmd_t *pmdp = pmd_off_k(virt);
 247
 248         if (virt & (1 << 20))
 249                 pmdp++;
 250
 251         *pmdp = __pmd(phys | prot);
 252         flush_pmd_entry(pmdp);
 253 }
 254
 255 /*
 256  * Create a SUPER SECTION PGD between VIRT and PHYS with protection PROT
 257  */
 258 static inline void
 259 alloc_init_supersection(unsigned long virt, unsigned long phys, int prot)
 260 {
 261         int i;
 262
 263         for (i = 0; i < 16; i += 1) {
 264                 alloc_init_section(virt, phys, prot | PMD_SECT_SUPER);
 265
 266                 virt += (PGDIR_SIZE / 2);
 267         }
 268 }
 269
 270 /*
 271  * Add a PAGE mapping between VIRT and PHYS in domain
 272  * DOMAIN with protection PROT.  Note that due to the
 273  * way we map the PTEs, we must allocate two PTE_SIZE'd
 274  * blocks - one for the Linux pte table, and one for
 275  * the hardware pte table.
 276  */
 277 static inline void
 278 alloc_init_page(unsigned long virt, unsigned long phys, unsigned int prot_l1, pgprot_t prot)
 279 {
 280         pmd_t *pmdp = pmd_off_k(virt);
 281         pte_t *ptep;
 282
 283         if (pmd_none(*pmdp)) {
 284                 ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
 285                                                sizeof(pte_t));
 286
 287                 __pmd_populate(pmdp, __pa(ptep) | prot_l1);
 288         }
 289         ptep = pte_offset_kernel(pmdp, virt);
 290
 291         set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot));
 292 }
 293
 294 struct mem_types {
 295         unsigned int    prot_pte;
 296         unsigned int    prot_l1;
 297         unsigned int    prot_sect;
 298         unsigned int    domain;
 299 };
 300
 301 static struct mem_types mem_types[] __initdata = {
 302         [MT_DEVICE] = {
 303                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 304                                 L_PTE_WRITE,
 305                 .prot_l1   = PMD_TYPE_TABLE,
 306                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 307                                 PMD_SECT_AP_WRITE,
 308                 .domain    = DOMAIN_IO,
 309         },
 310         [MT_CACHECLEAN] = {
 311                 .prot_sect = PMD_TYPE_SECT,
 312                 .domain    = DOMAIN_KERNEL,
 313         },
 314         [MT_MINICLEAN] = {
 315                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_MINICACHE,
 316                 .domain    = DOMAIN_KERNEL,
 317         },
 318         [MT_LOW_VECTORS] = {
 319                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 320                                 L_PTE_EXEC,
 321                 .prot_l1   = PMD_TYPE_TABLE,
 322                 .domain    = DOMAIN_USER,
 323         },
 324         [MT_HIGH_VECTORS] = {
 325                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 326                                 L_PTE_USER | L_PTE_EXEC,
 327                 .prot_l1   = PMD_TYPE_TABLE,
 328                 .domain    = DOMAIN_USER,
 329         },
 330         [MT_MEMORY] = {
 331                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 332                 .domain    = DOMAIN_KERNEL,
 333         },
 334         [MT_ROM] = {
 335                 .prot_sect = PMD_TYPE_SECT,
 336                 .domain    = DOMAIN_KERNEL,
 337         },
 338         [MT_IXP2000_DEVICE] = { /* IXP2400 requires XCB=101 for on-chip I/O */
 339                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 340                                 L_PTE_WRITE,
 341                 .prot_l1   = PMD_TYPE_TABLE,
 342                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_UNCACHED |
 343                                 PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE |
 344                                 PMD_SECT_TEX(1),
 345                 .domain    = DOMAIN_IO,
 346         }
 347 };
 348
 349 /*
 350  * Adjust the PMD section entries according to the CPU in use.
 351  */
 352 void __init build_mem_type_table(void)
 353 {
 354         struct cachepolicy *cp;
 355         unsigned int cr = get_cr();
 356         unsigned int user_pgprot, kern_pgprot;
 357         int cpu_arch = cpu_architecture();
 358         int i;
 359
 360 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 361         if (cachepolicy > CPOLICY_BUFFERED)
 362                 cachepolicy = CPOLICY_BUFFERED;
 363 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 364         if (cachepolicy > CPOLICY_WRITETHROUGH)
 365                 cachepolicy = CPOLICY_WRITETHROUGH;
 366 #endif
 367         if (cpu_arch < CPU_ARCH_ARMv5) {
 368                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 369                         cachepolicy = CPOLICY_WRITEBACK;
 370                 ecc_mask = 0;
 371         }
 372
 373         if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
 374                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 375                         if (mem_types[i].prot_l1)
 376                                 mem_types[i].prot_l1 |= PMD_BIT4;
 377                         if (mem_types[i].prot_sect)
 378                                 mem_types[i].prot_sect |= PMD_BIT4;
 379                 }
 380         }
 381
 382         cp = &cache_policies[cachepolicy];
 383         kern_pgprot = user_pgprot = cp->pte;
 384
 385         /*
 386          * ARMv6 and above have extended page tables.
 387          */
 388         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 389                 /*
 390                  * bit 4 becomes XN which we must clear for the
 391                  * kernel memory mapping.
 392                  */
 393                 mem_types[MT_MEMORY].prot_sect &= ~PMD_BIT4;
 394                 mem_types[MT_ROM].prot_sect &= ~PMD_BIT4;
 395
 396                 /*
 397                  * Mark cache clean areas and XIP ROM read only
 398                  * from SVC mode and no access from userspace.
 399                  */
 400                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 401                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 402                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 403
 404                 /*
 405                  * Mark the device area as "shared device"
 406                  */
 407                 mem_types[MT_DEVICE].prot_pte |= L_PTE_BUFFERABLE;
 408                 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 409
 410                 /*
 411                  * User pages need to be mapped with the ASID
 412                  * (iow, non-global)
 413                  */
 414                 user_pgprot |= L_PTE_ASID;
 415
 416 #ifdef CONFIG_SMP
 417                 /*
 418                  * Mark memory with the "shared" attribute for SMP systems
 419                  */
 420                 user_pgprot |= L_PTE_SHARED;
 421                 kern_pgprot |= L_PTE_SHARED;
 422                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 423 #endif
 424         }
 425
 426         for (i = 0; i < 16; i++) {
 427                 unsigned long v = pgprot_val(protection_map[i]);
 428                 v = (v & ~(L_PTE_BUFFERABLE|L_PTE_CACHEABLE)) | user_pgprot;
 429                 protection_map[i] = __pgprot(v);
 430         }
 431
 432         mem_types[MT_LOW_VECTORS].prot_pte |= kern_pgprot;
 433         mem_types[MT_HIGH_VECTORS].prot_pte |= kern_pgprot;
 434
 435         if (cpu_arch >= CPU_ARCH_ARMv5) {
 436 #ifndef CONFIG_SMP
 437                 /*
 438                  * Only use write-through for non-SMP systems
 439                  */
 440                 mem_types[MT_LOW_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
 441                 mem_types[MT_HIGH_VECTORS].prot_pte &= ~L_PTE_BUFFERABLE;
 442 #endif
 443         } else {
 444                 mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
 445         }
 446
 447         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 448                                  L_PTE_DIRTY | L_PTE_WRITE |
 449                                  L_PTE_EXEC | kern_pgprot);
 450
 451         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 452         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 453         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 454         mem_types[MT_ROM].prot_sect |= cp->pmd;
 455
 456         switch (cp->pmd) {
 457         case PMD_SECT_WT:
 458                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 459                 break;
 460         case PMD_SECT_WB:
 461         case PMD_SECT_WBWA:
 462                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 463                 break;
 464         }
 465         printk("Memory policy: ECC %sabled, Data cache %s\n",
 466                 ecc_mask ? "en" : "dis", cp->policy);
 467 }
 468
 469 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 470
 471 /*
 472  * Create the page directory entries and any necessary
 473  * page tables for the mapping specified by `md'.  We
 474  * are able to cope here with varying sizes and address
 475  * offsets, and we take full advantage of sections and
 476  * supersections.
 477  */
 478 void __init create_mapping(struct map_desc *md)
 479 {
 480         unsigned long virt, length;
 481         int prot_sect, prot_l1, domain;
 482         pgprot_t prot_pte;
 483         unsigned long off = (u32)__pfn_to_phys(md->pfn);
 484
 485         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 486                 printk(KERN_WARNING "BUG: not creating mapping for "
 487                        "0x%08llx at 0x%08lx in user region\n",
 488                        __pfn_to_phys((u64)md->pfn), md->virtual);
 489                 return;
 490         }
 491
 492         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 493             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 494                 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
 495                        "overlaps vmalloc space\n",
 496                        __pfn_to_phys((u64)md->pfn), md->virtual);
 497         }
 498
 499         domain    = mem_types[md->type].domain;
 500         prot_pte  = __pgprot(mem_types[md->type].prot_pte);
 501         prot_l1   = mem_types[md->type].prot_l1 | PMD_DOMAIN(domain);
 502         prot_sect = mem_types[md->type].prot_sect | PMD_DOMAIN(domain);
 503
 504         /*
 505          * Catch 36-bit addresses
 506          */
 507         if(md->pfn >= 0x100000) {
 508                 if(domain) {
 509                         printk(KERN_ERR "MM: invalid domain in supersection "
 510                                 "mapping for 0x%08llx at 0x%08lx\n",
 511                                 __pfn_to_phys((u64)md->pfn), md->virtual);
 512                         return;
 513                 }
 514                 if((md->virtual | md->length | __pfn_to_phys(md->pfn))
 515                         & ~SUPERSECTION_MASK) {
 516                         printk(KERN_ERR "MM: cannot create mapping for "
 517                                 "0x%08llx at 0x%08lx invalid alignment\n",
 518                                 __pfn_to_phys((u64)md->pfn), md->virtual);
 519                         return;
 520                 }
 521
 522                 /*
 523                  * Shift bits [35:32] of address into bits [23:20] of PMD
 524                  * (See ARMv6 spec).
 525                  */
 526                 off |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 527         }
 528
 529         virt   = md->virtual;
 530         off   -= virt;
 531         length = md->length;
 532
 533         if (mem_types[md->type].prot_l1 == 0 &&
 534             (virt & 0xfffff || (virt + off) & 0xfffff || (virt + length) & 0xfffff)) {
 535                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 536                        "be mapped using pages, ignoring.\n",
 537                        __pfn_to_phys(md->pfn), md->virtual);
 538                 return;
 539         }
 540
 541         while ((virt & 0xfffff || (virt + off) & 0xfffff) && length >= PAGE_SIZE) {
 542                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 543
 544                 virt   += PAGE_SIZE;
 545                 length -= PAGE_SIZE;
 546         }
 547
 548         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 549          *      Since domain assignments can in fact be arbitrary, the
 550          *      'domain == 0' check below is required to insure that ARMv6
 551          *      supersections are only allocated for domain 0 regardless
 552          *      of the actual domain assignments in use.
 553          */
 554         if (cpu_architecture() >= CPU_ARCH_ARMv6 && domain == 0) {
 555                 /*
 556                  * Align to supersection boundary if !high pages.
 557                  * High pages have already been checked for proper
 558                  * alignment above and they will fail the SUPSERSECTION_MASK
 559                  * check because of the way the address is encoded into
 560                  * offset.
 561                  */
 562                 if (md->pfn <= 0x100000) {
 563                         while ((virt & ~SUPERSECTION_MASK ||
 564                                 (virt + off) & ~SUPERSECTION_MASK) &&
 565                                 length >= (PGDIR_SIZE / 2)) {
 566                                 alloc_init_section(virt, virt + off, prot_sect);
 567
 568                                 virt   += (PGDIR_SIZE / 2);
 569                                 length -= (PGDIR_SIZE / 2);
 570                         }
 571                 }
 572
 573                 while (length >= SUPERSECTION_SIZE) {
 574                         alloc_init_supersection(virt, virt + off, prot_sect);
 575
 576                         virt   += SUPERSECTION_SIZE;
 577                         length -= SUPERSECTION_SIZE;
 578                 }
 579         }
 580
 581         /*
 582          * A section mapping covers half a "pgdir" entry.
 583          */
 584         while (length >= (PGDIR_SIZE / 2)) {
 585                 alloc_init_section(virt, virt + off, prot_sect);
 586
 587                 virt   += (PGDIR_SIZE / 2);
 588                 length -= (PGDIR_SIZE / 2);
 589         }
 590
 591         while (length >= PAGE_SIZE) {
 592                 alloc_init_page(virt, virt + off, prot_l1, prot_pte);
 593
 594                 virt   += PAGE_SIZE;
 595                 length -= PAGE_SIZE;
 596         }
 597 }
 598
 599 /*
 600  * In order to soft-boot, we need to insert a 1:1 mapping in place of
 601  * the user-mode pages.  This will then ensure that we have predictable
 602  * results when turning the mmu off
 603  */
 604 void setup_mm_for_reboot(char mode)
 605 {
 606         unsigned long base_pmdval;
 607         pgd_t *pgd;
 608         int i;
 609
 610         if (current->mm && current->mm->pgd)
 611                 pgd = current->mm->pgd;
 612         else
 613                 pgd = init_mm.pgd;
 614
 615         base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
 616         if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ)
 617                 base_pmdval |= PMD_BIT4;
 618
 619         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
 620                 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
 621                 pmd_t *pmd;
 622
 623                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
 624                 pmd[0] = __pmd(pmdval);
 625                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
 626                 flush_pmd_entry(pmd);
 627         }
 628 }
 629
 630 /*
 631  * Create the architecture specific mappings
 632  */
 633 void __init iotable_init(struct map_desc *io_desc, int nr)
 634 {
 635         int i;
 636
 637         for (i = 0; i < nr; i++)
 638                 create_mapping(io_desc + i);
 639 }