1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Chen-Yu Tsai
5 * Chen-Yu Tsai <wens@csie.org>
7 * arch/arm/mach-sunxi/mc_smp.c
9 * Based on Allwinner code, arch/arm/mach-exynos/mcpm-exynos.c, and
10 * arch/arm/mach-hisi/platmcpm.c
11 * Cluster cache enable trampoline code adapted from MCPM framework
14 #include <linux/arm-cci.h>
15 #include <linux/cpu_pm.h>
16 #include <linux/delay.h>
18 #include <linux/iopoll.h>
19 #include <linux/irqchip/arm-gic.h>
21 #include <linux/of_address.h>
22 #include <linux/of_device.h>
23 #include <linux/smp.h>
25 #include <asm/cacheflush.h>
27 #include <asm/cputype.h>
28 #include <asm/idmap.h>
29 #include <asm/smp_plat.h>
30 #include <asm/suspend.h>
32 #define SUNXI_CPUS_PER_CLUSTER 4
33 #define SUNXI_NR_CLUSTERS 2
36 #define TIMEOUT_USEC 100000
38 #define CPUCFG_CX_CTRL_REG0(c) (0x10 * (c))
39 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(n) BIT(n)
40 #define CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL 0xf
41 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7 BIT(4)
42 #define CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15 BIT(0)
43 #define CPUCFG_CX_CTRL_REG1(c) (0x10 * (c) + 0x4)
44 #define CPUCFG_CX_CTRL_REG1_ACINACTM BIT(0)
45 #define CPUCFG_CX_STATUS(c) (0x30 + 0x4 * (c))
46 #define CPUCFG_CX_STATUS_STANDBYWFI(n) BIT(16 + (n))
47 #define CPUCFG_CX_STATUS_STANDBYWFIL2 BIT(0)
48 #define CPUCFG_CX_RST_CTRL(c) (0x80 + 0x4 * (c))
49 #define CPUCFG_CX_RST_CTRL_DBG_SOC_RST BIT(24)
50 #define CPUCFG_CX_RST_CTRL_ETM_RST(n) BIT(20 + (n))
51 #define CPUCFG_CX_RST_CTRL_ETM_RST_ALL (0xf << 20)
52 #define CPUCFG_CX_RST_CTRL_DBG_RST(n) BIT(16 + (n))
53 #define CPUCFG_CX_RST_CTRL_DBG_RST_ALL (0xf << 16)
54 #define CPUCFG_CX_RST_CTRL_H_RST BIT(12)
55 #define CPUCFG_CX_RST_CTRL_L2_RST BIT(8)
56 #define CPUCFG_CX_RST_CTRL_CX_RST(n) BIT(4 + (n))
57 #define CPUCFG_CX_RST_CTRL_CORE_RST(n) BIT(n)
58 #define CPUCFG_CX_RST_CTRL_CORE_RST_ALL (0xf << 0)
60 #define PRCM_CPU_PO_RST_CTRL(c) (0x4 + 0x4 * (c))
61 #define PRCM_CPU_PO_RST_CTRL_CORE(n) BIT(n)
62 #define PRCM_CPU_PO_RST_CTRL_CORE_ALL 0xf
63 #define PRCM_PWROFF_GATING_REG(c) (0x100 + 0x4 * (c))
64 /* The power off register for clusters are different from a80 and a83t */
65 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I BIT(0)
66 #define PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I BIT(4)
67 #define PRCM_PWROFF_GATING_REG_CORE(n) BIT(n)
68 #define PRCM_PWR_SWITCH_REG(c, cpu) (0x140 + 0x10 * (c) + 0x4 * (cpu))
69 #define PRCM_CPU_SOFT_ENTRY_REG 0x164
71 /* R_CPUCFG registers, specific to sun8i-a83t */
72 #define R_CPUCFG_CLUSTER_PO_RST_CTRL(c) (0x30 + (c) * 0x4)
73 #define R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(n) BIT(n)
74 #define R_CPUCFG_CPU_SOFT_ENTRY_REG 0x01a4
76 #define CPU0_SUPPORT_HOTPLUG_MAGIC0 0xFA50392F
77 #define CPU0_SUPPORT_HOTPLUG_MAGIC1 0x790DCA3A
79 static void __iomem *cpucfg_base;
80 static void __iomem *prcm_base;
81 static void __iomem *sram_b_smp_base;
82 static void __iomem *r_cpucfg_base;
84 extern void sunxi_mc_smp_secondary_startup(void);
85 extern void sunxi_mc_smp_resume(void);
88 static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
90 struct device_node *node;
91 int cpu = cluster * SUNXI_CPUS_PER_CLUSTER + core;
93 node = of_cpu_device_node_get(cpu);
95 /* In case of_cpu_device_node_get fails */
97 node = of_get_cpu_node(cpu, NULL);
101 * There's no point in returning an error, since we
102 * would be mid way in a core or cluster power sequence.
104 pr_err("%s: Couldn't get CPU cluster %u core %u device node\n",
105 __func__, cluster, core);
110 return of_device_is_compatible(node, "arm,cortex-a15");
113 static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
118 /* control sequence from Allwinner A80 user manual v1.2 PRCM section */
119 reg = readl(prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
122 pr_debug("power clamp for cluster %u cpu %u already open\n",
127 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
129 writel(0xfe, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
131 writel(0xf8, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
133 writel(0xf0, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
135 writel(0x00, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
138 writel(0xff, prcm_base + PRCM_PWR_SWITCH_REG(cluster, cpu));
145 static void sunxi_cpu0_hotplug_support_set(bool enable)
148 writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
149 writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
151 writel(0x0, sram_b_smp_base);
152 writel(0x0, sram_b_smp_base + 0x4);
156 static int sunxi_cpu_powerup(unsigned int cpu, unsigned int cluster)
160 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
161 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
164 /* Set hotplug support magic flags for cpu0 */
165 if (cluster == 0 && cpu == 0)
166 sunxi_cpu0_hotplug_support_set(true);
168 /* assert processor power-on reset */
169 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
170 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE(cpu);
171 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
174 /* assert cpu power-on reset */
175 reg = readl(r_cpucfg_base +
176 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
177 reg &= ~(R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu));
178 writel(reg, r_cpucfg_base +
179 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
183 /* Cortex-A7: hold L1 reset disable signal low */
184 if (!sunxi_core_is_cortex_a15(cpu, cluster)) {
185 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
186 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE(cpu);
187 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
190 /* assert processor related resets */
191 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
192 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
195 * Allwinner code also asserts resets for NEON on A15. According
196 * to ARM manuals, asserting power-on reset is sufficient.
198 if (!sunxi_core_is_cortex_a15(cpu, cluster))
199 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
201 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
203 /* open power switch */
204 sunxi_cpu_power_switch_set(cpu, cluster, true);
206 /* Handle A83T bit swap */
212 /* clear processor power gate */
213 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
214 reg &= ~PRCM_PWROFF_GATING_REG_CORE(cpu);
215 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
218 /* Handle A83T bit swap */
224 /* de-assert processor power-on reset */
225 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
226 reg |= PRCM_CPU_PO_RST_CTRL_CORE(cpu);
227 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
230 reg = readl(r_cpucfg_base +
231 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
232 reg |= R_CPUCFG_CLUSTER_PO_RST_CTRL_CORE(cpu);
233 writel(reg, r_cpucfg_base +
234 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
238 /* de-assert all processor resets */
239 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
240 reg |= CPUCFG_CX_RST_CTRL_DBG_RST(cpu);
241 reg |= CPUCFG_CX_RST_CTRL_CORE_RST(cpu);
242 if (!sunxi_core_is_cortex_a15(cpu, cluster))
243 reg |= CPUCFG_CX_RST_CTRL_ETM_RST(cpu);
245 reg |= CPUCFG_CX_RST_CTRL_CX_RST(cpu); /* NEON */
246 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
251 static int sunxi_cluster_powerup(unsigned int cluster)
255 pr_debug("%s: cluster %u\n", __func__, cluster);
256 if (cluster >= SUNXI_NR_CLUSTERS)
259 /* For A83T, assert cluster cores resets */
261 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
262 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL; /* Core Reset */
263 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
267 /* assert ACINACTM */
268 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
269 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
270 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
272 /* assert cluster processor power-on resets */
273 reg = readl(prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
274 reg &= ~PRCM_CPU_PO_RST_CTRL_CORE_ALL;
275 writel(reg, prcm_base + PRCM_CPU_PO_RST_CTRL(cluster));
277 /* assert cluster cores resets */
279 reg = readl(r_cpucfg_base +
280 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
281 reg &= ~CPUCFG_CX_RST_CTRL_CORE_RST_ALL;
282 writel(reg, r_cpucfg_base +
283 R_CPUCFG_CLUSTER_PO_RST_CTRL(cluster));
287 /* assert cluster resets */
288 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
289 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
290 reg &= ~CPUCFG_CX_RST_CTRL_DBG_RST_ALL;
291 reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
292 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
295 * Allwinner code also asserts resets for NEON on A15. According
296 * to ARM manuals, asserting power-on reset is sufficient.
298 if (!sunxi_core_is_cortex_a15(0, cluster))
299 reg &= ~CPUCFG_CX_RST_CTRL_ETM_RST_ALL;
301 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
303 /* hold L1/L2 reset disable signals low */
304 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
305 if (sunxi_core_is_cortex_a15(0, cluster)) {
306 /* Cortex-A15: hold L2RSTDISABLE low */
307 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A15;
309 /* Cortex-A7: hold L1RSTDISABLE and L2RSTDISABLE low */
310 reg &= ~CPUCFG_CX_CTRL_REG0_L1_RST_DISABLE_ALL;
311 reg &= ~CPUCFG_CX_CTRL_REG0_L2_RST_DISABLE_A7;
313 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG0(cluster));
315 /* clear cluster power gate */
316 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
318 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
320 reg &= ~PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
321 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
324 /* de-assert cluster resets */
325 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
326 reg |= CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
327 reg |= CPUCFG_CX_RST_CTRL_H_RST;
328 reg |= CPUCFG_CX_RST_CTRL_L2_RST;
329 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
331 /* de-assert ACINACTM */
332 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
333 reg &= ~CPUCFG_CX_CTRL_REG1_ACINACTM;
334 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
340 * This bit is shared between the initial nocache_trampoline call to
341 * enable CCI-400 and proper cluster cache disable before power down.
343 static void sunxi_cluster_cache_disable_without_axi(void)
345 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) {
347 * On the Cortex-A15 we need to disable
348 * L2 prefetching before flushing the cache.
351 "mcr p15, 1, %0, c15, c0, 3\n"
357 /* Flush all cache levels for this cluster. */
358 v7_exit_coherency_flush(all);
361 * Disable cluster-level coherency by masking
362 * incoming snoops and DVM messages:
364 cci_disable_port_by_cpu(read_cpuid_mpidr());
367 static int sunxi_mc_smp_cpu_table[SUNXI_NR_CLUSTERS][SUNXI_CPUS_PER_CLUSTER];
368 int sunxi_mc_smp_first_comer;
370 static DEFINE_SPINLOCK(boot_lock);
372 static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
376 for (i = 0; i < SUNXI_CPUS_PER_CLUSTER; i++)
377 if (sunxi_mc_smp_cpu_table[cluster][i])
382 static void sunxi_mc_smp_secondary_init(unsigned int cpu)
384 /* Clear hotplug support magic flags for cpu0 */
386 sunxi_cpu0_hotplug_support_set(false);
389 static int sunxi_mc_smp_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
391 unsigned int mpidr, cpu, cluster;
393 mpidr = cpu_logical_map(l_cpu);
394 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
395 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
399 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
402 spin_lock_irq(&boot_lock);
404 if (sunxi_mc_smp_cpu_table[cluster][cpu])
407 if (sunxi_mc_smp_cluster_is_down(cluster)) {
408 sunxi_mc_smp_first_comer = true;
409 sunxi_cluster_powerup(cluster);
411 sunxi_mc_smp_first_comer = false;
414 /* This is read by incoming CPUs with their cache and MMU disabled */
415 sync_cache_w(&sunxi_mc_smp_first_comer);
416 sunxi_cpu_powerup(cpu, cluster);
419 sunxi_mc_smp_cpu_table[cluster][cpu]++;
420 spin_unlock_irq(&boot_lock);
425 #ifdef CONFIG_HOTPLUG_CPU
426 static void sunxi_cluster_cache_disable(void)
428 unsigned int cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
431 pr_debug("%s: cluster %u\n", __func__, cluster);
433 sunxi_cluster_cache_disable_without_axi();
435 /* last man standing, assert ACINACTM */
436 reg = readl(cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
437 reg |= CPUCFG_CX_CTRL_REG1_ACINACTM;
438 writel(reg, cpucfg_base + CPUCFG_CX_CTRL_REG1(cluster));
441 static void sunxi_mc_smp_cpu_die(unsigned int l_cpu)
443 unsigned int mpidr, cpu, cluster;
446 mpidr = cpu_logical_map(l_cpu);
447 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
448 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
449 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
451 spin_lock(&boot_lock);
452 sunxi_mc_smp_cpu_table[cluster][cpu]--;
453 if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
454 /* A power_up request went ahead of us. */
455 pr_debug("%s: aborting due to a power up request\n",
457 spin_unlock(&boot_lock);
459 } else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
460 pr_err("Cluster %d CPU%d boots multiple times\n",
465 last_man = sunxi_mc_smp_cluster_is_down(cluster);
466 spin_unlock(&boot_lock);
470 sunxi_cluster_cache_disable();
472 v7_exit_coherency_flush(louis);
478 static int sunxi_cpu_powerdown(unsigned int cpu, unsigned int cluster)
482 pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
483 if (cpu >= SUNXI_CPUS_PER_CLUSTER || cluster >= SUNXI_NR_CLUSTERS)
486 /* gate processor power */
487 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
488 reg |= PRCM_PWROFF_GATING_REG_CORE(cpu);
489 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
492 /* close power switch */
493 sunxi_cpu_power_switch_set(cpu, cluster, false);
498 static int sunxi_cluster_powerdown(unsigned int cluster)
502 pr_debug("%s: cluster %u\n", __func__, cluster);
503 if (cluster >= SUNXI_NR_CLUSTERS)
506 /* assert cluster resets or system will hang */
507 pr_debug("%s: assert cluster reset\n", __func__);
508 reg = readl(cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
509 reg &= ~CPUCFG_CX_RST_CTRL_DBG_SOC_RST;
510 reg &= ~CPUCFG_CX_RST_CTRL_H_RST;
511 reg &= ~CPUCFG_CX_RST_CTRL_L2_RST;
512 writel(reg, cpucfg_base + CPUCFG_CX_RST_CTRL(cluster));
514 /* gate cluster power */
515 pr_debug("%s: gate cluster power\n", __func__);
516 reg = readl(prcm_base + PRCM_PWROFF_GATING_REG(cluster));
518 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN8I;
520 reg |= PRCM_PWROFF_GATING_REG_CLUSTER_SUN9I;
521 writel(reg, prcm_base + PRCM_PWROFF_GATING_REG(cluster));
527 static int sunxi_mc_smp_cpu_kill(unsigned int l_cpu)
529 unsigned int mpidr, cpu, cluster;
530 unsigned int tries, count;
534 mpidr = cpu_logical_map(l_cpu);
535 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
536 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
538 /* This should never happen */
539 if (WARN_ON(cluster >= SUNXI_NR_CLUSTERS ||
540 cpu >= SUNXI_CPUS_PER_CLUSTER))
543 /* wait for CPU core to die and enter WFI */
544 count = TIMEOUT_USEC / POLL_USEC;
545 spin_lock_irq(&boot_lock);
546 for (tries = 0; tries < count; tries++) {
547 spin_unlock_irq(&boot_lock);
548 usleep_range(POLL_USEC / 2, POLL_USEC);
549 spin_lock_irq(&boot_lock);
552 * If the user turns off a bunch of cores at the same
553 * time, the kernel might call cpu_kill before some of
554 * them are ready. This is because boot_lock serializes
555 * both cpu_die and cpu_kill callbacks. Either one could
556 * run first. We should wait for cpu_die to complete.
558 if (sunxi_mc_smp_cpu_table[cluster][cpu])
561 reg = readl(cpucfg_base + CPUCFG_CX_STATUS(cluster));
562 if (reg & CPUCFG_CX_STATUS_STANDBYWFI(cpu))
566 if (tries >= count) {
571 /* power down CPU core */
572 sunxi_cpu_powerdown(cpu, cluster);
574 if (!sunxi_mc_smp_cluster_is_down(cluster))
577 /* wait for cluster L2 WFI */
578 ret = readl_poll_timeout(cpucfg_base + CPUCFG_CX_STATUS(cluster), reg,
579 reg & CPUCFG_CX_STATUS_STANDBYWFIL2,
580 POLL_USEC, TIMEOUT_USEC);
583 * Ignore timeout on the cluster. Leaving the cluster on
584 * will not affect system execution, just use a bit more
585 * power. But returning an error here will only confuse
586 * the user as the CPU has already been shutdown.
592 /* Power down cluster */
593 sunxi_cluster_powerdown(cluster);
596 spin_unlock_irq(&boot_lock);
597 pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
598 __func__, cluster, cpu, ret);
602 static bool sunxi_mc_smp_cpu_can_disable(unsigned int cpu)
604 /* CPU0 hotplug not handled for sun8i-a83t */
612 static const struct smp_operations sunxi_mc_smp_smp_ops __initconst = {
613 .smp_secondary_init = sunxi_mc_smp_secondary_init,
614 .smp_boot_secondary = sunxi_mc_smp_boot_secondary,
615 #ifdef CONFIG_HOTPLUG_CPU
616 .cpu_die = sunxi_mc_smp_cpu_die,
617 .cpu_kill = sunxi_mc_smp_cpu_kill,
618 .cpu_can_disable = sunxi_mc_smp_cpu_can_disable,
622 static bool __init sunxi_mc_smp_cpu_table_init(void)
624 unsigned int mpidr, cpu, cluster;
626 mpidr = read_cpuid_mpidr();
627 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
628 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
630 if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER) {
631 pr_err("%s: boot CPU is out of bounds!\n", __func__);
634 sunxi_mc_smp_cpu_table[cluster][cpu] = 1;
639 * Adapted from arch/arm/common/mc_smp_entry.c
641 * We need the trampoline code to enable CCI-400 on the first cluster
643 typedef typeof(cpu_reset) phys_reset_t;
645 static int __init nocache_trampoline(unsigned long __unused)
647 phys_reset_t phys_reset;
649 setup_mm_for_reboot();
650 sunxi_cluster_cache_disable_without_axi();
652 phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
653 phys_reset(__pa_symbol(sunxi_mc_smp_resume), false);
657 static int __init sunxi_mc_smp_loopback(void)
662 * We're going to soft-restart the current CPU through the
663 * low-level MCPM code by leveraging the suspend/resume
664 * infrastructure. Let's play it safe by using cpu_pm_enter()
665 * in case the CPU init code path resets the VFP or similar.
667 sunxi_mc_smp_first_comer = true;
670 ret = cpu_pm_enter();
672 ret = cpu_suspend(0, nocache_trampoline);
677 sunxi_mc_smp_first_comer = false;
683 * This holds any device nodes that we requested resources for,
684 * so that we may easily release resources in the error path.
686 struct sunxi_mc_smp_nodes {
687 struct device_node *prcm_node;
688 struct device_node *cpucfg_node;
689 struct device_node *sram_node;
690 struct device_node *r_cpucfg_node;
693 /* This structure holds SoC-specific bits tied to an enable-method string. */
694 struct sunxi_mc_smp_data {
695 const char *enable_method;
696 int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
700 static void __init sunxi_mc_smp_put_nodes(struct sunxi_mc_smp_nodes *nodes)
702 of_node_put(nodes->prcm_node);
703 of_node_put(nodes->cpucfg_node);
704 of_node_put(nodes->sram_node);
705 of_node_put(nodes->r_cpucfg_node);
706 memset(nodes, 0, sizeof(*nodes));
709 static int __init sun9i_a80_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
711 nodes->prcm_node = of_find_compatible_node(NULL, NULL,
712 "allwinner,sun9i-a80-prcm");
713 if (!nodes->prcm_node) {
714 pr_err("%s: PRCM not available\n", __func__);
718 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
719 "allwinner,sun9i-a80-cpucfg");
720 if (!nodes->cpucfg_node) {
721 pr_err("%s: CPUCFG not available\n", __func__);
725 nodes->sram_node = of_find_compatible_node(NULL, NULL,
726 "allwinner,sun9i-a80-smp-sram");
727 if (!nodes->sram_node) {
728 pr_err("%s: Secure SRAM not available\n", __func__);
735 static int __init sun8i_a83t_get_smp_nodes(struct sunxi_mc_smp_nodes *nodes)
737 nodes->prcm_node = of_find_compatible_node(NULL, NULL,
738 "allwinner,sun8i-a83t-r-ccu");
739 if (!nodes->prcm_node) {
740 pr_err("%s: PRCM not available\n", __func__);
744 nodes->cpucfg_node = of_find_compatible_node(NULL, NULL,
745 "allwinner,sun8i-a83t-cpucfg");
746 if (!nodes->cpucfg_node) {
747 pr_err("%s: CPUCFG not available\n", __func__);
751 nodes->r_cpucfg_node = of_find_compatible_node(NULL, NULL,
752 "allwinner,sun8i-a83t-r-cpucfg");
753 if (!nodes->r_cpucfg_node) {
754 pr_err("%s: RCPUCFG not available\n", __func__);
761 static const struct sunxi_mc_smp_data sunxi_mc_smp_data[] __initconst = {
763 .enable_method = "allwinner,sun9i-a80-smp",
764 .get_smp_nodes = sun9i_a80_get_smp_nodes,
767 .enable_method = "allwinner,sun8i-a83t-smp",
768 .get_smp_nodes = sun8i_a83t_get_smp_nodes,
773 static int __init sunxi_mc_smp_init(void)
775 struct sunxi_mc_smp_nodes nodes = { 0 };
776 struct device_node *node;
782 * Don't bother checking the "cpus" node, as an enable-method
783 * property in that node is undocumented.
785 node = of_cpu_device_node_get(0);
790 * We can't actually use the enable-method magic in the kernel.
791 * Our loopback / trampoline code uses the CPU suspend framework,
792 * which requires the identity mapping be available. It would not
793 * yet be available if we used the .init_cpus or .prepare_cpus
794 * callbacks in smp_operations, which we would use if we were to
795 * use CPU_METHOD_OF_DECLARE
797 for (i = 0; i < ARRAY_SIZE(sunxi_mc_smp_data); i++) {
798 ret = of_property_match_string(node, "enable-method",
799 sunxi_mc_smp_data[i].enable_method);
804 is_a83t = sunxi_mc_smp_data[i].is_a83t;
810 if (!sunxi_mc_smp_cpu_table_init())
814 pr_err("%s: CCI-400 not available\n", __func__);
818 /* Get needed device tree nodes */
819 ret = sunxi_mc_smp_data[i].get_smp_nodes(&nodes);
824 * Unfortunately we can not request the I/O region for the PRCM.
825 * It is shared with the PRCM clock.
827 prcm_base = of_iomap(nodes.prcm_node, 0);
829 pr_err("%s: failed to map PRCM registers\n", __func__);
834 cpucfg_base = of_io_request_and_map(nodes.cpucfg_node, 0,
836 if (IS_ERR(cpucfg_base)) {
837 ret = PTR_ERR(cpucfg_base);
838 pr_err("%s: failed to map CPUCFG registers: %d\n",
844 r_cpucfg_base = of_io_request_and_map(nodes.r_cpucfg_node,
846 if (IS_ERR(r_cpucfg_base)) {
847 ret = PTR_ERR(r_cpucfg_base);
848 pr_err("%s: failed to map R-CPUCFG registers\n",
850 goto err_unmap_release_cpucfg;
853 sram_b_smp_base = of_io_request_and_map(nodes.sram_node, 0,
855 if (IS_ERR(sram_b_smp_base)) {
856 ret = PTR_ERR(sram_b_smp_base);
857 pr_err("%s: failed to map secure SRAM\n", __func__);
858 goto err_unmap_release_cpucfg;
862 /* Configure CCI-400 for boot cluster */
863 ret = sunxi_mc_smp_loopback();
865 pr_err("%s: failed to configure boot cluster: %d\n",
867 goto err_unmap_release_sram_rcpucfg;
870 /* We don't need the device nodes anymore */
871 sunxi_mc_smp_put_nodes(&nodes);
873 /* Set the hardware entry point address */
875 addr = r_cpucfg_base + R_CPUCFG_CPU_SOFT_ENTRY_REG;
877 addr = prcm_base + PRCM_CPU_SOFT_ENTRY_REG;
878 writel(__pa_symbol(sunxi_mc_smp_secondary_startup), addr);
880 /* Actually enable multi cluster SMP */
881 smp_set_ops(&sunxi_mc_smp_smp_ops);
883 pr_info("sunxi multi cluster SMP support installed\n");
887 err_unmap_release_sram_rcpucfg:
889 iounmap(r_cpucfg_base);
890 of_address_to_resource(nodes.r_cpucfg_node, 0, &res);
892 iounmap(sram_b_smp_base);
893 of_address_to_resource(nodes.sram_node, 0, &res);
895 release_mem_region(res.start, resource_size(&res));
896 err_unmap_release_cpucfg:
897 iounmap(cpucfg_base);
898 of_address_to_resource(nodes.cpucfg_node, 0, &res);
899 release_mem_region(res.start, resource_size(&res));
903 sunxi_mc_smp_put_nodes(&nodes);
907 early_initcall(sunxi_mc_smp_init);