arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17
  18 #include <linux/platform_data/i2c-omap.h>
  19 #include <linux/power/smartreflex.h>
  20 #include <linux/platform_data/hsmmc-omap.h>
  21
  22 #include <linux/omap-dma.h>
  23 #include "l3_3xxx.h"
  24 #include "l4_3xxx.h"
  25
  26 #include "soc.h"
  27 #include "omap_hwmod.h"
  28 #include "omap_hwmod_common_data.h"
  29 #include "prm-regbits-34xx.h"
  30 #include "cm-regbits-34xx.h"
  31
  32 #include "i2c.h"
  33 #include "wd_timer.h"
  34 #include "serial.h"
  35
  36 /*
  37  * OMAP3xxx hardware module integration data
  38  *
  39  * All of the data in this section should be autogeneratable from the
  40  * TI hardware database or other technical documentation.  Data that
  41  * is driver-specific or driver-kernel integration-specific belongs
  42  * elsewhere.
  43  */
  44
  45 #define AM35XX_IPSS_USBOTGSS_BASE      0x5C040000
  46
  47 /*
  48  * IP blocks
  49  */
  50
  51 /* L3 */
  52
  53 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  54         .name           = "l3_main",
  55         .class          = &l3_hwmod_class,
  56         .flags          = HWMOD_NO_IDLEST,
  57 };
  58
  59 /* L4 CORE */
  60 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  61         .name           = "l4_core",
  62         .class          = &l4_hwmod_class,
  63         .flags          = HWMOD_NO_IDLEST,
  64 };
  65
  66 /* L4 PER */
  67 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  68         .name           = "l4_per",
  69         .class          = &l4_hwmod_class,
  70         .flags          = HWMOD_NO_IDLEST,
  71 };
  72
  73 /* L4 WKUP */
  74 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  75         .name           = "l4_wkup",
  76         .class          = &l4_hwmod_class,
  77         .flags          = HWMOD_NO_IDLEST,
  78 };
  79
  80 /* L4 SEC */
  81 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  82         .name           = "l4_sec",
  83         .class          = &l4_hwmod_class,
  84         .flags          = HWMOD_NO_IDLEST,
  85 };
  86
  87 /* MPU */
  88
  89 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  90         .name           = "mpu",
  91         .class          = &mpu_hwmod_class,
  92         .main_clk       = "arm_fck",
  93 };
  94
  95 /* IVA2 (IVA2) */
  96 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
  97         { .name = "logic", .rst_shift = 0, .st_shift = 8 },
  98         { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
  99         { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 100 };
 101
 102 static struct omap_hwmod omap3xxx_iva_hwmod = {
 103         .name           = "iva",
 104         .class          = &iva_hwmod_class,
 105         .clkdm_name     = "iva2_clkdm",
 106         .rst_lines      = omap3xxx_iva_resets,
 107         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 108         .main_clk       = "iva2_ck",
 109         .prcm = {
 110                 .omap2 = {
 111                         .module_offs = OMAP3430_IVA2_MOD,
 112                         .idlest_reg_id = 1,
 113                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
 114                 },
 115         },
 116 };
 117
 118 /*
 119  * 'debugss' class
 120  * debug and emulation sub system
 121  */
 122
 123 static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
 124         .name   = "debugss",
 125 };
 126
 127 /* debugss */
 128 static struct omap_hwmod omap3xxx_debugss_hwmod = {
 129         .name           = "debugss",
 130         .class          = &omap3xxx_debugss_hwmod_class,
 131         .clkdm_name     = "emu_clkdm",
 132         .main_clk       = "emu_src_ck",
 133         .flags          = HWMOD_NO_IDLEST,
 134 };
 135
 136 /* timer class */
 137 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 138         .rev_offs       = 0x0000,
 139         .sysc_offs      = 0x0010,
 140         .syss_offs      = 0x0014,
 141         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 142                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 143                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 144                            SYSS_HAS_RESET_STATUS),
 145         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 146         .sysc_fields    = &omap_hwmod_sysc_type1,
 147 };
 148
 149 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 150         .name = "timer",
 151         .sysc = &omap3xxx_timer_sysc,
 152 };
 153
 154 /* timer1 */
 155 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 156         .name           = "timer1",
 157         .main_clk       = "gpt1_fck",
 158         .prcm           = {
 159                 .omap2 = {
 160                         .module_offs = WKUP_MOD,
 161                         .idlest_reg_id = 1,
 162                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 163                 },
 164         },
 165         .class          = &omap3xxx_timer_hwmod_class,
 166         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 167 };
 168
 169 /* timer2 */
 170 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 171         .name           = "timer2",
 172         .main_clk       = "gpt2_fck",
 173         .prcm           = {
 174                 .omap2 = {
 175                         .module_offs = OMAP3430_PER_MOD,
 176                         .idlest_reg_id = 1,
 177                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 178                 },
 179         },
 180         .class          = &omap3xxx_timer_hwmod_class,
 181         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 182 };
 183
 184 /* timer3 */
 185 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 186         .name           = "timer3",
 187         .main_clk       = "gpt3_fck",
 188         .prcm           = {
 189                 .omap2 = {
 190                         .module_offs = OMAP3430_PER_MOD,
 191                         .idlest_reg_id = 1,
 192                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 193                 },
 194         },
 195         .class          = &omap3xxx_timer_hwmod_class,
 196         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 197 };
 198
 199 /* timer4 */
 200 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 201         .name           = "timer4",
 202         .main_clk       = "gpt4_fck",
 203         .prcm           = {
 204                 .omap2 = {
 205                         .module_offs = OMAP3430_PER_MOD,
 206                         .idlest_reg_id = 1,
 207                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 208                 },
 209         },
 210         .class          = &omap3xxx_timer_hwmod_class,
 211         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 212 };
 213
 214 /* timer5 */
 215 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 216         .name           = "timer5",
 217         .main_clk       = "gpt5_fck",
 218         .prcm           = {
 219                 .omap2 = {
 220                         .module_offs = OMAP3430_PER_MOD,
 221                         .idlest_reg_id = 1,
 222                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 223                 },
 224         },
 225         .class          = &omap3xxx_timer_hwmod_class,
 226         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 227 };
 228
 229 /* timer6 */
 230 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 231         .name           = "timer6",
 232         .main_clk       = "gpt6_fck",
 233         .prcm           = {
 234                 .omap2 = {
 235                         .module_offs = OMAP3430_PER_MOD,
 236                         .idlest_reg_id = 1,
 237                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 238                 },
 239         },
 240         .class          = &omap3xxx_timer_hwmod_class,
 241         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 242 };
 243
 244 /* timer7 */
 245 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 246         .name           = "timer7",
 247         .main_clk       = "gpt7_fck",
 248         .prcm           = {
 249                 .omap2 = {
 250                         .module_offs = OMAP3430_PER_MOD,
 251                         .idlest_reg_id = 1,
 252                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 253                 },
 254         },
 255         .class          = &omap3xxx_timer_hwmod_class,
 256         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 257 };
 258
 259 /* timer8 */
 260 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 261         .name           = "timer8",
 262         .main_clk       = "gpt8_fck",
 263         .prcm           = {
 264                 .omap2 = {
 265                         .module_offs = OMAP3430_PER_MOD,
 266                         .idlest_reg_id = 1,
 267                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 268                 },
 269         },
 270         .class          = &omap3xxx_timer_hwmod_class,
 271         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 272 };
 273
 274 /* timer9 */
 275 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 276         .name           = "timer9",
 277         .main_clk       = "gpt9_fck",
 278         .prcm           = {
 279                 .omap2 = {
 280                         .module_offs = OMAP3430_PER_MOD,
 281                         .idlest_reg_id = 1,
 282                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 283                 },
 284         },
 285         .class          = &omap3xxx_timer_hwmod_class,
 286         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 287 };
 288
 289 /* timer10 */
 290 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 291         .name           = "timer10",
 292         .main_clk       = "gpt10_fck",
 293         .prcm           = {
 294                 .omap2 = {
 295                         .module_offs = CORE_MOD,
 296                         .idlest_reg_id = 1,
 297                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 298                 },
 299         },
 300         .class          = &omap3xxx_timer_hwmod_class,
 301         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 302 };
 303
 304 /* timer11 */
 305 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 306         .name           = "timer11",
 307         .main_clk       = "gpt11_fck",
 308         .prcm           = {
 309                 .omap2 = {
 310                         .module_offs = CORE_MOD,
 311                         .idlest_reg_id = 1,
 312                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 313                 },
 314         },
 315         .class          = &omap3xxx_timer_hwmod_class,
 316         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 317 };
 318
 319 /* timer12 */
 320 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 321         .name           = "timer12",
 322         .main_clk       = "gpt12_fck",
 323         .prcm           = {
 324                 .omap2 = {
 325                         .module_offs = WKUP_MOD,
 326                         .idlest_reg_id = 1,
 327                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 328                 },
 329         },
 330         .class          = &omap3xxx_timer_hwmod_class,
 331         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
 332 };
 333
 334 /*
 335  * 'wd_timer' class
 336  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 337  * overflow condition
 338  */
 339
 340 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 341         .rev_offs       = 0x0000,
 342         .sysc_offs      = 0x0010,
 343         .syss_offs      = 0x0014,
 344         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 345                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 346                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 347                            SYSS_HAS_RESET_STATUS),
 348         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 349         .sysc_fields    = &omap_hwmod_sysc_type1,
 350 };
 351
 352 /* I2C common */
 353 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 354         .rev_offs       = 0x00,
 355         .sysc_offs      = 0x20,
 356         .syss_offs      = 0x10,
 357         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 358                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 359                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 360         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 361         .sysc_fields    = &omap_hwmod_sysc_type1,
 362 };
 363
 364 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 365         .name           = "wd_timer",
 366         .sysc           = &omap3xxx_wd_timer_sysc,
 367         .pre_shutdown   = &omap2_wd_timer_disable,
 368         .reset          = &omap2_wd_timer_reset,
 369 };
 370
 371 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 372         .name           = "wd_timer2",
 373         .class          = &omap3xxx_wd_timer_hwmod_class,
 374         .main_clk       = "wdt2_fck",
 375         .prcm           = {
 376                 .omap2 = {
 377                         .module_offs = WKUP_MOD,
 378                         .idlest_reg_id = 1,
 379                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 380                 },
 381         },
 382         /*
 383          * XXX: Use software supervised mode, HW supervised smartidle seems to
 384          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 385          */
 386         .flags          = HWMOD_SWSUP_SIDLE,
 387 };
 388
 389 /* UART1 */
 390 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 391         .name           = "uart1",
 392         .main_clk       = "uart1_fck",
 393         .flags          = DEBUG_TI81XXUART1_FLAGS | HWMOD_SWSUP_SIDLE,
 394         .prcm           = {
 395                 .omap2 = {
 396                         .module_offs = CORE_MOD,
 397                         .idlest_reg_id = 1,
 398                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 399                 },
 400         },
 401         .class          = &omap2_uart_class,
 402 };
 403
 404 /* UART2 */
 405 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 406         .name           = "uart2",
 407         .main_clk       = "uart2_fck",
 408         .flags          = DEBUG_TI81XXUART2_FLAGS | HWMOD_SWSUP_SIDLE,
 409         .prcm           = {
 410                 .omap2 = {
 411                         .module_offs = CORE_MOD,
 412                         .idlest_reg_id = 1,
 413                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 414                 },
 415         },
 416         .class          = &omap2_uart_class,
 417 };
 418
 419 /* UART3 */
 420 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 421         .name           = "uart3",
 422         .main_clk       = "uart3_fck",
 423         .flags          = DEBUG_OMAP3UART3_FLAGS | DEBUG_TI81XXUART3_FLAGS |
 424                                 HWMOD_SWSUP_SIDLE,
 425         .prcm           = {
 426                 .omap2 = {
 427                         .module_offs = OMAP3430_PER_MOD,
 428                         .idlest_reg_id = 1,
 429                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 430                 },
 431         },
 432         .class          = &omap2_uart_class,
 433 };
 434
 435 /* UART4 */
 436
 437
 438 static struct omap_hwmod omap36xx_uart4_hwmod = {
 439         .name           = "uart4",
 440         .main_clk       = "uart4_fck",
 441         .flags          = DEBUG_OMAP3UART4_FLAGS | HWMOD_SWSUP_SIDLE,
 442         .prcm           = {
 443                 .omap2 = {
 444                         .module_offs = OMAP3430_PER_MOD,
 445                         .idlest_reg_id = 1,
 446                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 447                 },
 448         },
 449         .class          = &omap2_uart_class,
 450 };
 451
 452
 453
 454 /*
 455  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 456  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 457  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 458  * should not be needed.  The functional clock structure of the AM35xx
 459  * UART4 is extremely unclear and opaque; it is unclear what the role
 460  * of uart1/2_fck is for the UART4.  Any clarification from either
 461  * empirical testing or the AM3505/3517 hardware designers would be
 462  * most welcome.
 463  */
 464 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 465         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 466 };
 467
 468 static struct omap_hwmod am35xx_uart4_hwmod = {
 469         .name           = "uart4",
 470         .main_clk       = "uart4_fck",
 471         .prcm           = {
 472                 .omap2 = {
 473                         .module_offs = CORE_MOD,
 474                         .idlest_reg_id = 1,
 475                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 476                 },
 477         },
 478         .opt_clks       = am35xx_uart4_opt_clks,
 479         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 480         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 481         .class          = &omap2_uart_class,
 482 };
 483
 484 static struct omap_hwmod_class i2c_class = {
 485         .name   = "i2c",
 486         .sysc   = &i2c_sysc,
 487         .reset  = &omap_i2c_reset,
 488 };
 489
 490 /* dss */
 491 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 492         /*
 493          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 494          * driver does not use these clocks.
 495          */
 496         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 497         { .role = "tv_clk", .clk = "dss_tv_fck" },
 498         /* required only on OMAP3430 */
 499         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 500 };
 501
 502 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 503         .name           = "dss_core",
 504         .class          = &omap2_dss_hwmod_class,
 505         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 506         .prcm           = {
 507                 .omap2 = {
 508                         .module_offs = OMAP3430_DSS_MOD,
 509                         .idlest_reg_id = 1,
 510                 },
 511         },
 512         .opt_clks       = dss_opt_clks,
 513         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 514         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 515 };
 516
 517 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 518         .name           = "dss_core",
 519         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 520         .class          = &omap2_dss_hwmod_class,
 521         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 522         .prcm           = {
 523                 .omap2 = {
 524                         .module_offs = OMAP3430_DSS_MOD,
 525                         .idlest_reg_id = 1,
 526                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 527                 },
 528         },
 529         .opt_clks       = dss_opt_clks,
 530         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 531 };
 532
 533 /*
 534  * 'dispc' class
 535  * display controller
 536  */
 537
 538 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 539         .rev_offs       = 0x0000,
 540         .sysc_offs      = 0x0010,
 541         .syss_offs      = 0x0014,
 542         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 543                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 544                            SYSC_HAS_ENAWAKEUP),
 545         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 546                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 547         .sysc_fields    = &omap_hwmod_sysc_type1,
 548 };
 549
 550 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 551         .name   = "dispc",
 552         .sysc   = &omap3_dispc_sysc,
 553 };
 554
 555 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 556         .name           = "dss_dispc",
 557         .class          = &omap3_dispc_hwmod_class,
 558         .main_clk       = "dss1_alwon_fck",
 559         .prcm           = {
 560                 .omap2 = {
 561                         .module_offs = OMAP3430_DSS_MOD,
 562                 },
 563         },
 564         .flags          = HWMOD_NO_IDLEST,
 565         .dev_attr       = &omap2_3_dss_dispc_dev_attr,
 566 };
 567
 568 /*
 569  * 'dsi' class
 570  * display serial interface controller
 571  */
 572
 573 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
 574         .rev_offs       = 0x0000,
 575         .sysc_offs      = 0x0010,
 576         .syss_offs      = 0x0014,
 577         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 578                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 579                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 580         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 581         .sysc_fields    = &omap_hwmod_sysc_type1,
 582 };
 583
 584 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 585         .name = "dsi",
 586         .sysc   = &omap3xxx_dsi_sysc,
 587 };
 588
 589 /* dss_dsi1 */
 590 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 591         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 592 };
 593
 594 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 595         .name           = "dss_dsi1",
 596         .class          = &omap3xxx_dsi_hwmod_class,
 597         .main_clk       = "dss1_alwon_fck",
 598         .prcm           = {
 599                 .omap2 = {
 600                         .module_offs = OMAP3430_DSS_MOD,
 601                 },
 602         },
 603         .opt_clks       = dss_dsi1_opt_clks,
 604         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 605         .flags          = HWMOD_NO_IDLEST,
 606 };
 607
 608 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 609         { .role = "ick", .clk = "dss_ick" },
 610 };
 611
 612 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 613         .name           = "dss_rfbi",
 614         .class          = &omap2_rfbi_hwmod_class,
 615         .main_clk       = "dss1_alwon_fck",
 616         .prcm           = {
 617                 .omap2 = {
 618                         .module_offs = OMAP3430_DSS_MOD,
 619                 },
 620         },
 621         .opt_clks       = dss_rfbi_opt_clks,
 622         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 623         .flags          = HWMOD_NO_IDLEST,
 624 };
 625
 626 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 627         /* required only on OMAP3430 */
 628         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 629 };
 630
 631 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 632         .name           = "dss_venc",
 633         .class          = &omap2_venc_hwmod_class,
 634         .main_clk       = "dss_tv_fck",
 635         .prcm           = {
 636                 .omap2 = {
 637                         .module_offs = OMAP3430_DSS_MOD,
 638                 },
 639         },
 640         .opt_clks       = dss_venc_opt_clks,
 641         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 642         .flags          = HWMOD_NO_IDLEST,
 643 };
 644
 645 /* I2C1 */
 646 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 647         .name           = "i2c1",
 648         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 649         .main_clk       = "i2c1_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .module_offs = CORE_MOD,
 653                         .idlest_reg_id = 1,
 654                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 655                 },
 656         },
 657         .class          = &i2c_class,
 658 };
 659
 660 /* I2C2 */
 661 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 662         .name           = "i2c2",
 663         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 664         .main_clk       = "i2c2_fck",
 665         .prcm           = {
 666                 .omap2 = {
 667                         .module_offs = CORE_MOD,
 668                         .idlest_reg_id = 1,
 669                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 670                 },
 671         },
 672         .class          = &i2c_class,
 673 };
 674
 675 /* I2C3 */
 676 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 677         .name           = "i2c3",
 678         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 679         .main_clk       = "i2c3_fck",
 680         .prcm           = {
 681                 .omap2 = {
 682                         .module_offs = CORE_MOD,
 683                         .idlest_reg_id = 1,
 684                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 685                 },
 686         },
 687         .class          = &i2c_class,
 688 };
 689
 690 /*
 691  * 'gpio' class
 692  * general purpose io module
 693  */
 694
 695 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 696         .rev_offs       = 0x0000,
 697         .sysc_offs      = 0x0010,
 698         .syss_offs      = 0x0014,
 699         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 700                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 701                            SYSS_HAS_RESET_STATUS),
 702         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 703         .sysc_fields    = &omap_hwmod_sysc_type1,
 704 };
 705
 706 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 707         .name = "gpio",
 708         .sysc = &omap3xxx_gpio_sysc,
 709 };
 710
 711 /* gpio1 */
 712 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 713         { .role = "dbclk", .clk = "gpio1_dbck", },
 714 };
 715
 716 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 717         .name           = "gpio1",
 718         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 719         .main_clk       = "gpio1_ick",
 720         .opt_clks       = gpio1_opt_clks,
 721         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 722         .prcm           = {
 723                 .omap2 = {
 724                         .module_offs = WKUP_MOD,
 725                         .idlest_reg_id = 1,
 726                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 727                 },
 728         },
 729         .class          = &omap3xxx_gpio_hwmod_class,
 730 };
 731
 732 /* gpio2 */
 733 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 734         { .role = "dbclk", .clk = "gpio2_dbck", },
 735 };
 736
 737 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 738         .name           = "gpio2",
 739         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 740         .main_clk       = "gpio2_ick",
 741         .opt_clks       = gpio2_opt_clks,
 742         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 743         .prcm           = {
 744                 .omap2 = {
 745                         .module_offs = OMAP3430_PER_MOD,
 746                         .idlest_reg_id = 1,
 747                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 748                 },
 749         },
 750         .class          = &omap3xxx_gpio_hwmod_class,
 751 };
 752
 753 /* gpio3 */
 754 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 755         { .role = "dbclk", .clk = "gpio3_dbck", },
 756 };
 757
 758 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 759         .name           = "gpio3",
 760         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 761         .main_clk       = "gpio3_ick",
 762         .opt_clks       = gpio3_opt_clks,
 763         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 764         .prcm           = {
 765                 .omap2 = {
 766                         .module_offs = OMAP3430_PER_MOD,
 767                         .idlest_reg_id = 1,
 768                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 769                 },
 770         },
 771         .class          = &omap3xxx_gpio_hwmod_class,
 772 };
 773
 774 /* gpio4 */
 775 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 776         { .role = "dbclk", .clk = "gpio4_dbck", },
 777 };
 778
 779 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 780         .name           = "gpio4",
 781         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 782         .main_clk       = "gpio4_ick",
 783         .opt_clks       = gpio4_opt_clks,
 784         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 785         .prcm           = {
 786                 .omap2 = {
 787                         .module_offs = OMAP3430_PER_MOD,
 788                         .idlest_reg_id = 1,
 789                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 790                 },
 791         },
 792         .class          = &omap3xxx_gpio_hwmod_class,
 793 };
 794
 795 /* gpio5 */
 796
 797 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 798         { .role = "dbclk", .clk = "gpio5_dbck", },
 799 };
 800
 801 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 802         .name           = "gpio5",
 803         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 804         .main_clk       = "gpio5_ick",
 805         .opt_clks       = gpio5_opt_clks,
 806         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 807         .prcm           = {
 808                 .omap2 = {
 809                         .module_offs = OMAP3430_PER_MOD,
 810                         .idlest_reg_id = 1,
 811                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 812                 },
 813         },
 814         .class          = &omap3xxx_gpio_hwmod_class,
 815 };
 816
 817 /* gpio6 */
 818
 819 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 820         { .role = "dbclk", .clk = "gpio6_dbck", },
 821 };
 822
 823 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 824         .name           = "gpio6",
 825         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 826         .main_clk       = "gpio6_ick",
 827         .opt_clks       = gpio6_opt_clks,
 828         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 829         .prcm           = {
 830                 .omap2 = {
 831                         .module_offs = OMAP3430_PER_MOD,
 832                         .idlest_reg_id = 1,
 833                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
 834                 },
 835         },
 836         .class          = &omap3xxx_gpio_hwmod_class,
 837 };
 838
 839 /* dma attributes */
 840 static struct omap_dma_dev_attr dma_dev_attr = {
 841         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 842                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 843         .lch_count = 32,
 844 };
 845
 846 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
 847         .rev_offs       = 0x0000,
 848         .sysc_offs      = 0x002c,
 849         .syss_offs      = 0x0028,
 850         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 851                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 852                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
 853                            SYSS_HAS_RESET_STATUS),
 854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 855                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 856         .sysc_fields    = &omap_hwmod_sysc_type1,
 857 };
 858
 859 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
 860         .name = "dma",
 861         .sysc = &omap3xxx_dma_sysc,
 862 };
 863
 864 /* dma_system */
 865 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
 866         .name           = "dma",
 867         .class          = &omap3xxx_dma_hwmod_class,
 868         .main_clk       = "core_l3_ick",
 869         .prcm = {
 870                 .omap2 = {
 871                         .module_offs            = CORE_MOD,
 872                         .idlest_reg_id          = 1,
 873                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
 874                 },
 875         },
 876         .dev_attr       = &dma_dev_attr,
 877         .flags          = HWMOD_NO_IDLEST,
 878 };
 879
 880 /*
 881  * 'mcbsp' class
 882  * multi channel buffered serial port controller
 883  */
 884
 885 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
 886         .rev_offs       = -ENODEV,
 887         .sysc_offs      = 0x008c,
 888         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
 889                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 890         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 891         .sysc_fields    = &omap_hwmod_sysc_type1,
 892 };
 893
 894 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
 895         .name = "mcbsp",
 896         .sysc = &omap3xxx_mcbsp_sysc,
 897 };
 898
 899 /* McBSP functional clock mapping */
 900 static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
 901         { .role = "pad_fck", .clk = "mcbsp_clks" },
 902         { .role = "prcm_fck", .clk = "core_96m_fck" },
 903 };
 904
 905 static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
 906         { .role = "pad_fck", .clk = "mcbsp_clks" },
 907         { .role = "prcm_fck", .clk = "per_96m_fck" },
 908 };
 909
 910 /* mcbsp1 */
 911 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
 912         .name           = "mcbsp1",
 913         .class          = &omap3xxx_mcbsp_hwmod_class,
 914         .main_clk       = "mcbsp1_fck",
 915         .prcm           = {
 916                 .omap2 = {
 917                         .module_offs = CORE_MOD,
 918                         .idlest_reg_id = 1,
 919                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
 920                 },
 921         },
 922         .opt_clks       = mcbsp15_opt_clks,
 923         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
 924 };
 925
 926 /* mcbsp2 */
 927 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
 928         .name           = "mcbsp2",
 929         .class          = &omap3xxx_mcbsp_hwmod_class,
 930         .main_clk       = "mcbsp2_fck",
 931         .prcm           = {
 932                 .omap2 = {
 933                         .module_offs = OMAP3430_PER_MOD,
 934                         .idlest_reg_id = 1,
 935                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
 936                 },
 937         },
 938         .opt_clks       = mcbsp234_opt_clks,
 939         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
 940 };
 941
 942 /* mcbsp3 */
 943 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
 944         .name           = "mcbsp3",
 945         .class          = &omap3xxx_mcbsp_hwmod_class,
 946         .main_clk       = "mcbsp3_fck",
 947         .prcm           = {
 948                 .omap2 = {
 949                         .module_offs = OMAP3430_PER_MOD,
 950                         .idlest_reg_id = 1,
 951                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
 952                 },
 953         },
 954         .opt_clks       = mcbsp234_opt_clks,
 955         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
 956 };
 957
 958 /* mcbsp4 */
 959 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
 960         .name           = "mcbsp4",
 961         .class          = &omap3xxx_mcbsp_hwmod_class,
 962         .main_clk       = "mcbsp4_fck",
 963         .prcm           = {
 964                 .omap2 = {
 965                         .module_offs = OMAP3430_PER_MOD,
 966                         .idlest_reg_id = 1,
 967                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
 968                 },
 969         },
 970         .opt_clks       = mcbsp234_opt_clks,
 971         .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
 972 };
 973
 974 /* mcbsp5 */
 975 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
 976         .name           = "mcbsp5",
 977         .class          = &omap3xxx_mcbsp_hwmod_class,
 978         .main_clk       = "mcbsp5_fck",
 979         .prcm           = {
 980                 .omap2 = {
 981                         .module_offs = CORE_MOD,
 982                         .idlest_reg_id = 1,
 983                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
 984                 },
 985         },
 986         .opt_clks       = mcbsp15_opt_clks,
 987         .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
 988 };
 989
 990 /* 'mcbsp sidetone' class */
 991 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
 992         .rev_offs       = -ENODEV,
 993         .sysc_offs      = 0x0010,
 994         .sysc_flags     = SYSC_HAS_AUTOIDLE,
 995         .sysc_fields    = &omap_hwmod_sysc_type1,
 996 };
 997
 998 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
 999         .name = "mcbsp_sidetone",
1000         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1001 };
1002
1003 /* mcbsp2_sidetone */
1004 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1005         .name           = "mcbsp2_sidetone",
1006         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1007         .main_clk       = "mcbsp2_ick",
1008         .flags          = HWMOD_NO_IDLEST,
1009 };
1010
1011 /* mcbsp3_sidetone */
1012 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1013         .name           = "mcbsp3_sidetone",
1014         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1015         .main_clk       = "mcbsp3_ick",
1016         .flags          = HWMOD_NO_IDLEST,
1017 };
1018
1019 /* SR common */
1020 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1021         .rev_offs       = -ENODEV,
1022         .sysc_offs      = 0x24,
1023         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1024         .sysc_fields    = &omap34xx_sr_sysc_fields,
1025 };
1026
1027 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1028         .name = "smartreflex",
1029         .sysc = &omap34xx_sr_sysc,
1030 };
1031
1032 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1033         .rev_offs       = -ENODEV,
1034         .sysc_offs      = 0x38,
1035         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1036         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1037                         SYSC_NO_CACHE),
1038         .sysc_fields    = &omap36xx_sr_sysc_fields,
1039 };
1040
1041 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1042         .name = "smartreflex",
1043         .sysc = &omap36xx_sr_sysc,
1044 };
1045
1046 /* SR1 */
1047 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1048         .sensor_voltdm_name   = "mpu_iva",
1049 };
1050
1051
1052 static struct omap_hwmod omap34xx_sr1_hwmod = {
1053         .name           = "smartreflex_mpu_iva",
1054         .class          = &omap34xx_smartreflex_hwmod_class,
1055         .main_clk       = "sr1_fck",
1056         .prcm           = {
1057                 .omap2 = {
1058                         .module_offs = WKUP_MOD,
1059                         .idlest_reg_id = 1,
1060                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1061                 },
1062         },
1063         .dev_attr       = &sr1_dev_attr,
1064         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1065 };
1066
1067 static struct omap_hwmod omap36xx_sr1_hwmod = {
1068         .name           = "smartreflex_mpu_iva",
1069         .class          = &omap36xx_smartreflex_hwmod_class,
1070         .main_clk       = "sr1_fck",
1071         .prcm           = {
1072                 .omap2 = {
1073                         .module_offs = WKUP_MOD,
1074                         .idlest_reg_id = 1,
1075                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1076                 },
1077         },
1078         .dev_attr       = &sr1_dev_attr,
1079 };
1080
1081 /* SR2 */
1082 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1083         .sensor_voltdm_name     = "core",
1084 };
1085
1086
1087 static struct omap_hwmod omap34xx_sr2_hwmod = {
1088         .name           = "smartreflex_core",
1089         .class          = &omap34xx_smartreflex_hwmod_class,
1090         .main_clk       = "sr2_fck",
1091         .prcm           = {
1092                 .omap2 = {
1093                         .module_offs = WKUP_MOD,
1094                         .idlest_reg_id = 1,
1095                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1096                 },
1097         },
1098         .dev_attr       = &sr2_dev_attr,
1099         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1100 };
1101
1102 static struct omap_hwmod omap36xx_sr2_hwmod = {
1103         .name           = "smartreflex_core",
1104         .class          = &omap36xx_smartreflex_hwmod_class,
1105         .main_clk       = "sr2_fck",
1106         .prcm           = {
1107                 .omap2 = {
1108                         .module_offs = WKUP_MOD,
1109                         .idlest_reg_id = 1,
1110                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1111                 },
1112         },
1113         .dev_attr       = &sr2_dev_attr,
1114 };
1115
1116 /*
1117  * 'mailbox' class
1118  * mailbox module allowing communication between the on-chip processors
1119  * using a queued mailbox-interrupt mechanism.
1120  */
1121
1122 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1123         .rev_offs       = 0x000,
1124         .sysc_offs      = 0x010,
1125         .syss_offs      = 0x014,
1126         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1127                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1128         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1129         .sysc_fields    = &omap_hwmod_sysc_type1,
1130 };
1131
1132 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1133         .name = "mailbox",
1134         .sysc = &omap3xxx_mailbox_sysc,
1135 };
1136
1137 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1138         .name           = "mailbox",
1139         .class          = &omap3xxx_mailbox_hwmod_class,
1140         .main_clk       = "mailboxes_ick",
1141         .prcm           = {
1142                 .omap2 = {
1143                         .module_offs = CORE_MOD,
1144                         .idlest_reg_id = 1,
1145                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1146                 },
1147         },
1148 };
1149
1150 /*
1151  * 'mcspi' class
1152  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1153  * bus
1154  */
1155
1156 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1157         .rev_offs       = 0x0000,
1158         .sysc_offs      = 0x0010,
1159         .syss_offs      = 0x0014,
1160         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1161                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1162                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1164         .sysc_fields    = &omap_hwmod_sysc_type1,
1165 };
1166
1167 static struct omap_hwmod_class omap34xx_mcspi_class = {
1168         .name = "mcspi",
1169         .sysc = &omap34xx_mcspi_sysc,
1170 };
1171
1172 /* mcspi1 */
1173 static struct omap_hwmod omap34xx_mcspi1 = {
1174         .name           = "mcspi1",
1175         .main_clk       = "mcspi1_fck",
1176         .prcm           = {
1177                 .omap2 = {
1178                         .module_offs = CORE_MOD,
1179                         .idlest_reg_id = 1,
1180                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1181                 },
1182         },
1183         .class          = &omap34xx_mcspi_class,
1184 };
1185
1186 /* mcspi2 */
1187 static struct omap_hwmod omap34xx_mcspi2 = {
1188         .name           = "mcspi2",
1189         .main_clk       = "mcspi2_fck",
1190         .prcm           = {
1191                 .omap2 = {
1192                         .module_offs = CORE_MOD,
1193                         .idlest_reg_id = 1,
1194                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1195                 },
1196         },
1197         .class          = &omap34xx_mcspi_class,
1198 };
1199
1200 /* mcspi3 */
1201 static struct omap_hwmod omap34xx_mcspi3 = {
1202         .name           = "mcspi3",
1203         .main_clk       = "mcspi3_fck",
1204         .prcm           = {
1205                 .omap2 = {
1206                         .module_offs = CORE_MOD,
1207                         .idlest_reg_id = 1,
1208                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1209                 },
1210         },
1211         .class          = &omap34xx_mcspi_class,
1212 };
1213
1214 /* mcspi4 */
1215 static struct omap_hwmod omap34xx_mcspi4 = {
1216         .name           = "mcspi4",
1217         .main_clk       = "mcspi4_fck",
1218         .prcm           = {
1219                 .omap2 = {
1220                         .module_offs = CORE_MOD,
1221                         .idlest_reg_id = 1,
1222                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1223                 },
1224         },
1225         .class          = &omap34xx_mcspi_class,
1226 };
1227
1228 /* usbhsotg */
1229 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1230         .rev_offs       = 0x0400,
1231         .sysc_offs      = 0x0404,
1232         .syss_offs      = 0x0408,
1233         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1234                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1235                           SYSC_HAS_AUTOIDLE),
1236         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1237                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1238         .sysc_fields    = &omap_hwmod_sysc_type1,
1239 };
1240
1241 static struct omap_hwmod_class usbotg_class = {
1242         .name = "usbotg",
1243         .sysc = &omap3xxx_usbhsotg_sysc,
1244 };
1245
1246 /* usb_otg_hs */
1247
1248 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1249         .name           = "usb_otg_hs",
1250         .main_clk       = "hsotgusb_ick",
1251         .prcm           = {
1252                 .omap2 = {
1253                         .module_offs = CORE_MOD,
1254                         .idlest_reg_id = 1,
1255                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1256                 },
1257         },
1258         .class          = &usbotg_class,
1259
1260         /*
1261          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1262          * broken when autoidle is enabled
1263          * workaround is to disable the autoidle bit at module level.
1264          *
1265          * Enabling the device in any other MIDLEMODE setting but force-idle
1266          * causes core_pwrdm not enter idle states at least on OMAP3630.
1267          * Note that musb has OTG_FORCESTDBY register that controls MSTANDBY
1268          * signal when MIDLEMODE is set to force-idle.
1269          */
1270         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
1271                           HWMOD_FORCE_MSTANDBY | HWMOD_RECONFIG_IO_CHAIN,
1272 };
1273
1274 /* usb_otg_hs */
1275
1276 static struct omap_hwmod_class am35xx_usbotg_class = {
1277         .name = "am35xx_usbotg",
1278 };
1279
1280 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1281         .name           = "am35x_otg_hs",
1282         .main_clk       = "hsotgusb_fck",
1283         .class          = &am35xx_usbotg_class,
1284         .flags          = HWMOD_NO_IDLEST,
1285 };
1286
1287 /* MMC/SD/SDIO common */
1288 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1289         .rev_offs       = 0x1fc,
1290         .sysc_offs      = 0x10,
1291         .syss_offs      = 0x14,
1292         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1293                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1294                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1295         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1296         .sysc_fields    = &omap_hwmod_sysc_type1,
1297 };
1298
1299 static struct omap_hwmod_class omap34xx_mmc_class = {
1300         .name = "mmc",
1301         .sysc = &omap34xx_mmc_sysc,
1302 };
1303
1304 /* MMC/SD/SDIO1 */
1305
1306
1307
1308 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1309         { .role = "dbck", .clk = "omap_32k_fck", },
1310 };
1311
1312 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1313         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1314 };
1315
1316 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1317 static struct omap_hsmmc_dev_attr mmc1_pre_es3_dev_attr = {
1318         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1319                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1320 };
1321
1322 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1323         .name           = "mmc1",
1324         .opt_clks       = omap34xx_mmc1_opt_clks,
1325         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1326         .main_clk       = "mmchs1_fck",
1327         .prcm           = {
1328                 .omap2 = {
1329                         .module_offs = CORE_MOD,
1330                         .idlest_reg_id = 1,
1331                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1332                 },
1333         },
1334         .dev_attr       = &mmc1_pre_es3_dev_attr,
1335         .class          = &omap34xx_mmc_class,
1336 };
1337
1338 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1339         .name           = "mmc1",
1340         .opt_clks       = omap34xx_mmc1_opt_clks,
1341         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1342         .main_clk       = "mmchs1_fck",
1343         .prcm           = {
1344                 .omap2 = {
1345                         .module_offs = CORE_MOD,
1346                         .idlest_reg_id = 1,
1347                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1348                 },
1349         },
1350         .dev_attr       = &mmc1_dev_attr,
1351         .class          = &omap34xx_mmc_class,
1352 };
1353
1354 /* MMC/SD/SDIO2 */
1355
1356
1357
1358 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1359         { .role = "dbck", .clk = "omap_32k_fck", },
1360 };
1361
1362 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1363 static struct omap_hsmmc_dev_attr mmc2_pre_es3_dev_attr = {
1364         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1365 };
1366
1367 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1368         .name           = "mmc2",
1369         .opt_clks       = omap34xx_mmc2_opt_clks,
1370         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1371         .main_clk       = "mmchs2_fck",
1372         .prcm           = {
1373                 .omap2 = {
1374                         .module_offs = CORE_MOD,
1375                         .idlest_reg_id = 1,
1376                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1377                 },
1378         },
1379         .dev_attr       = &mmc2_pre_es3_dev_attr,
1380         .class          = &omap34xx_mmc_class,
1381 };
1382
1383 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1384         .name           = "mmc2",
1385         .opt_clks       = omap34xx_mmc2_opt_clks,
1386         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1387         .main_clk       = "mmchs2_fck",
1388         .prcm           = {
1389                 .omap2 = {
1390                         .module_offs = CORE_MOD,
1391                         .idlest_reg_id = 1,
1392                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1393                 },
1394         },
1395         .class          = &omap34xx_mmc_class,
1396 };
1397
1398 /* MMC/SD/SDIO3 */
1399
1400
1401
1402 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1403         { .role = "dbck", .clk = "omap_32k_fck", },
1404 };
1405
1406 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1407         .name           = "mmc3",
1408         .opt_clks       = omap34xx_mmc3_opt_clks,
1409         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1410         .main_clk       = "mmchs3_fck",
1411         .prcm           = {
1412                 .omap2 = {
1413                         .module_offs = CORE_MOD,
1414                         .idlest_reg_id = 1,
1415                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1416                 },
1417         },
1418         .class          = &omap34xx_mmc_class,
1419 };
1420
1421 /*
1422  * 'usb_host_hs' class
1423  * high-speed multi-port usb host controller
1424  */
1425
1426 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1427         .rev_offs       = 0x0000,
1428         .sysc_offs      = 0x0010,
1429         .syss_offs      = 0x0014,
1430         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1431                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1432                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1433                            SYSS_HAS_RESET_STATUS),
1434         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1435                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1436         .sysc_fields    = &omap_hwmod_sysc_type1,
1437 };
1438
1439 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1440         .name = "usb_host_hs",
1441         .sysc = &omap3xxx_usb_host_hs_sysc,
1442 };
1443
1444
1445 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1446         .name           = "usb_host_hs",
1447         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1448         .clkdm_name     = "usbhost_clkdm",
1449         .main_clk       = "usbhost_48m_fck",
1450         .prcm = {
1451                 .omap2 = {
1452                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1453                         .idlest_reg_id = 1,
1454                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1455                 },
1456         },
1457
1458         /*
1459          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1460          * id: i660
1461          *
1462          * Description:
1463          * In the following configuration :
1464          * - USBHOST module is set to smart-idle mode
1465          * - PRCM asserts idle_req to the USBHOST module ( This typically
1466          *   happens when the system is going to a low power mode : all ports
1467          *   have been suspended, the master part of the USBHOST module has
1468          *   entered the standby state, and SW has cut the functional clocks)
1469          * - an USBHOST interrupt occurs before the module is able to answer
1470          *   idle_ack, typically a remote wakeup IRQ.
1471          * Then the USB HOST module will enter a deadlock situation where it
1472          * is no more accessible nor functional.
1473          *
1474          * Workaround:
1475          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1476          */
1477
1478         /*
1479          * Errata: USB host EHCI may stall when entering smart-standby mode
1480          * Id: i571
1481          *
1482          * Description:
1483          * When the USBHOST module is set to smart-standby mode, and when it is
1484          * ready to enter the standby state (i.e. all ports are suspended and
1485          * all attached devices are in suspend mode), then it can wrongly assert
1486          * the Mstandby signal too early while there are still some residual OCP
1487          * transactions ongoing. If this condition occurs, the internal state
1488          * machine may go to an undefined state and the USB link may be stuck
1489          * upon the next resume.
1490          *
1491          * Workaround:
1492          * Don't use smart standby; use only force standby,
1493          * hence HWMOD_SWSUP_MSTANDBY
1494          */
1495
1496         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1497 };
1498
1499 /*
1500  * 'usb_tll_hs' class
1501  * usb_tll_hs module is the adapter on the usb_host_hs ports
1502  */
1503 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1504         .rev_offs       = 0x0000,
1505         .sysc_offs      = 0x0010,
1506         .syss_offs      = 0x0014,
1507         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1508                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1509                            SYSC_HAS_AUTOIDLE),
1510         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1511         .sysc_fields    = &omap_hwmod_sysc_type1,
1512 };
1513
1514 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1515         .name = "usb_tll_hs",
1516         .sysc = &omap3xxx_usb_tll_hs_sysc,
1517 };
1518
1519
1520 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1521         .name           = "usb_tll_hs",
1522         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
1523         .clkdm_name     = "core_l4_clkdm",
1524         .main_clk       = "usbtll_fck",
1525         .prcm = {
1526                 .omap2 = {
1527                         .module_offs = CORE_MOD,
1528                         .idlest_reg_id = 3,
1529                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1530                 },
1531         },
1532 };
1533
1534 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1535         .name           = "hdq1w",
1536         .main_clk       = "hdq_fck",
1537         .prcm           = {
1538                 .omap2 = {
1539                         .module_offs = CORE_MOD,
1540                         .idlest_reg_id = 1,
1541                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1542                 },
1543         },
1544         .class          = &omap2_hdq1w_class,
1545 };
1546
1547 /* SAD2D */
1548 static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
1549         { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
1550         { .name = "rst_modem_sw", .rst_shift = 1 },
1551 };
1552
1553 static struct omap_hwmod_class omap3xxx_sad2d_class = {
1554         .name                   = "sad2d",
1555 };
1556
1557 static struct omap_hwmod omap3xxx_sad2d_hwmod = {
1558         .name           = "sad2d",
1559         .rst_lines      = omap3xxx_sad2d_resets,
1560         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
1561         .main_clk       = "sad2d_ick",
1562         .prcm           = {
1563                 .omap2 = {
1564                         .module_offs = CORE_MOD,
1565                         .idlest_reg_id = 1,
1566                         .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
1567                 },
1568         },
1569         .class          = &omap3xxx_sad2d_class,
1570 };
1571
1572 /*
1573  * '32K sync counter' class
1574  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1575  */
1576 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1577         .rev_offs       = 0x0000,
1578         .sysc_offs      = 0x0004,
1579         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1580         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
1581         .sysc_fields    = &omap_hwmod_sysc_type1,
1582 };
1583
1584 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
1585         .name   = "counter",
1586         .sysc   = &omap3xxx_counter_sysc,
1587 };
1588
1589 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
1590         .name           = "counter_32k",
1591         .class          = &omap3xxx_counter_hwmod_class,
1592         .clkdm_name     = "wkup_clkdm",
1593         .flags          = HWMOD_SWSUP_SIDLE,
1594         .main_clk       = "wkup_32k_fck",
1595         .prcm           = {
1596                 .omap2  = {
1597                         .module_offs = WKUP_MOD,
1598                         .idlest_reg_id = 1,
1599                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
1600                 },
1601         },
1602 };
1603
1604 /*
1605  * 'gpmc' class
1606  * general purpose memory controller
1607  */
1608
1609 static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
1610         .rev_offs       = 0x0000,
1611         .sysc_offs      = 0x0010,
1612         .syss_offs      = 0x0014,
1613         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1614                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1616         .sysc_fields    = &omap_hwmod_sysc_type1,
1617 };
1618
1619 static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
1620         .name   = "gpmc",
1621         .sysc   = &omap3xxx_gpmc_sysc,
1622 };
1623
1624 static struct omap_hwmod omap3xxx_gpmc_hwmod = {
1625         .name           = "gpmc",
1626         .class          = &omap3xxx_gpmc_hwmod_class,
1627         .clkdm_name     = "core_l3_clkdm",
1628         .main_clk       = "gpmc_fck",
1629         /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1630         .flags          = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1631 };
1632
1633 /*
1634  * interfaces
1635  */
1636
1637 /* L3 -> L4_CORE interface */
1638 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
1639         .master = &omap3xxx_l3_main_hwmod,
1640         .slave  = &omap3xxx_l4_core_hwmod,
1641         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1642 };
1643
1644 /* L3 -> L4_PER interface */
1645 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
1646         .master = &omap3xxx_l3_main_hwmod,
1647         .slave  = &omap3xxx_l4_per_hwmod,
1648         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1649 };
1650
1651
1652 /* MPU -> L3 interface */
1653 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
1654         .master   = &omap3xxx_mpu_hwmod,
1655         .slave    = &omap3xxx_l3_main_hwmod,
1656         .user   = OCP_USER_MPU,
1657 };
1658
1659
1660 /* l3 -> debugss */
1661 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
1662         .master         = &omap3xxx_l3_main_hwmod,
1663         .slave          = &omap3xxx_debugss_hwmod,
1664         .user           = OCP_USER_MPU,
1665 };
1666
1667 /* DSS -> l3 */
1668 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
1669         .master         = &omap3430es1_dss_core_hwmod,
1670         .slave          = &omap3xxx_l3_main_hwmod,
1671         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1672 };
1673
1674 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
1675         .master         = &omap3xxx_dss_core_hwmod,
1676         .slave          = &omap3xxx_l3_main_hwmod,
1677         .fw = {
1678                 .omap2 = {
1679                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
1680                         .flags  = OMAP_FIREWALL_L3,
1681                 },
1682         },
1683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1684 };
1685
1686 /* l3_core -> usbhsotg interface */
1687 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
1688         .master         = &omap3xxx_usbhsotg_hwmod,
1689         .slave          = &omap3xxx_l3_main_hwmod,
1690         .clk            = "core_l3_ick",
1691         .user           = OCP_USER_MPU,
1692 };
1693
1694 /* l3_core -> am35xx_usbhsotg interface */
1695 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
1696         .master         = &am35xx_usbhsotg_hwmod,
1697         .slave          = &omap3xxx_l3_main_hwmod,
1698         .clk            = "hsotgusb_ick",
1699         .user           = OCP_USER_MPU,
1700 };
1701
1702 /* l3_core -> sad2d interface */
1703 static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
1704         .master         = &omap3xxx_sad2d_hwmod,
1705         .slave          = &omap3xxx_l3_main_hwmod,
1706         .clk            = "core_l3_ick",
1707         .user           = OCP_USER_MPU,
1708 };
1709
1710 /* L4_CORE -> L4_WKUP interface */
1711 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
1712         .master = &omap3xxx_l4_core_hwmod,
1713         .slave  = &omap3xxx_l4_wkup_hwmod,
1714         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1715 };
1716
1717 /* L4 CORE -> MMC1 interface */
1718 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
1719         .master         = &omap3xxx_l4_core_hwmod,
1720         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
1721         .clk            = "mmchs1_ick",
1722         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1723         .flags          = OMAP_FIREWALL_L4,
1724 };
1725
1726 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
1727         .master         = &omap3xxx_l4_core_hwmod,
1728         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
1729         .clk            = "mmchs1_ick",
1730         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1731         .flags          = OMAP_FIREWALL_L4,
1732 };
1733
1734 /* L4 CORE -> MMC2 interface */
1735 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
1736         .master         = &omap3xxx_l4_core_hwmod,
1737         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
1738         .clk            = "mmchs2_ick",
1739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1740         .flags          = OMAP_FIREWALL_L4,
1741 };
1742
1743 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
1744         .master         = &omap3xxx_l4_core_hwmod,
1745         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
1746         .clk            = "mmchs2_ick",
1747         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1748         .flags          = OMAP_FIREWALL_L4,
1749 };
1750
1751 /* L4 CORE -> MMC3 interface */
1752
1753 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
1754         .master         = &omap3xxx_l4_core_hwmod,
1755         .slave          = &omap3xxx_mmc3_hwmod,
1756         .clk            = "mmchs3_ick",
1757         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1758         .flags          = OMAP_FIREWALL_L4,
1759 };
1760
1761 /* L4 CORE -> UART1 interface */
1762
1763 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
1764         .master         = &omap3xxx_l4_core_hwmod,
1765         .slave          = &omap3xxx_uart1_hwmod,
1766         .clk            = "uart1_ick",
1767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1768 };
1769
1770 /* L4 CORE -> UART2 interface */
1771
1772 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
1773         .master         = &omap3xxx_l4_core_hwmod,
1774         .slave          = &omap3xxx_uart2_hwmod,
1775         .clk            = "uart2_ick",
1776         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1777 };
1778
1779 /* L4 PER -> UART3 interface */
1780
1781 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
1782         .master         = &omap3xxx_l4_per_hwmod,
1783         .slave          = &omap3xxx_uart3_hwmod,
1784         .clk            = "uart3_ick",
1785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1786 };
1787
1788 /* L4 PER -> UART4 interface */
1789
1790 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
1791         .master         = &omap3xxx_l4_per_hwmod,
1792         .slave          = &omap36xx_uart4_hwmod,
1793         .clk            = "uart4_ick",
1794         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1795 };
1796
1797 /* AM35xx: L4 CORE -> UART4 interface */
1798
1799 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
1800         .master         = &omap3xxx_l4_core_hwmod,
1801         .slave          = &am35xx_uart4_hwmod,
1802         .clk            = "uart4_ick",
1803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1804 };
1805
1806 /* L4 CORE -> I2C1 interface */
1807 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
1808         .master         = &omap3xxx_l4_core_hwmod,
1809         .slave          = &omap3xxx_i2c1_hwmod,
1810         .clk            = "i2c1_ick",
1811         .fw = {
1812                 .omap2 = {
1813                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
1814                         .l4_prot_group = 7,
1815                         .flags  = OMAP_FIREWALL_L4,
1816                 },
1817         },
1818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1819 };
1820
1821 /* L4 CORE -> I2C2 interface */
1822 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
1823         .master         = &omap3xxx_l4_core_hwmod,
1824         .slave          = &omap3xxx_i2c2_hwmod,
1825         .clk            = "i2c2_ick",
1826         .fw = {
1827                 .omap2 = {
1828                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
1829                         .l4_prot_group = 7,
1830                         .flags = OMAP_FIREWALL_L4,
1831                 },
1832         },
1833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1834 };
1835
1836 /* L4 CORE -> I2C3 interface */
1837
1838 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
1839         .master         = &omap3xxx_l4_core_hwmod,
1840         .slave          = &omap3xxx_i2c3_hwmod,
1841         .clk            = "i2c3_ick",
1842         .fw = {
1843                 .omap2 = {
1844                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
1845                         .l4_prot_group = 7,
1846                         .flags = OMAP_FIREWALL_L4,
1847                 },
1848         },
1849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1850 };
1851
1852 /* L4 CORE -> SR1 interface */
1853 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
1854         .master         = &omap3xxx_l4_core_hwmod,
1855         .slave          = &omap34xx_sr1_hwmod,
1856         .clk            = "sr_l4_ick",
1857         .user           = OCP_USER_MPU,
1858 };
1859
1860 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
1861         .master         = &omap3xxx_l4_core_hwmod,
1862         .slave          = &omap36xx_sr1_hwmod,
1863         .clk            = "sr_l4_ick",
1864         .user           = OCP_USER_MPU,
1865 };
1866
1867 /* L4 CORE -> SR2 interface */
1868
1869 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
1870         .master         = &omap3xxx_l4_core_hwmod,
1871         .slave          = &omap34xx_sr2_hwmod,
1872         .clk            = "sr_l4_ick",
1873         .user           = OCP_USER_MPU,
1874 };
1875
1876 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
1877         .master         = &omap3xxx_l4_core_hwmod,
1878         .slave          = &omap36xx_sr2_hwmod,
1879         .clk            = "sr_l4_ick",
1880         .user           = OCP_USER_MPU,
1881 };
1882
1883
1884 /* l4_core -> usbhsotg  */
1885 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
1886         .master         = &omap3xxx_l4_core_hwmod,
1887         .slave          = &omap3xxx_usbhsotg_hwmod,
1888         .clk            = "l4_ick",
1889         .user           = OCP_USER_MPU,
1890 };
1891
1892
1893 /* l4_core -> usbhsotg  */
1894 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
1895         .master         = &omap3xxx_l4_core_hwmod,
1896         .slave          = &am35xx_usbhsotg_hwmod,
1897         .clk            = "hsotgusb_ick",
1898         .user           = OCP_USER_MPU,
1899 };
1900
1901 /* L4_WKUP -> L4_SEC interface */
1902 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
1903         .master = &omap3xxx_l4_wkup_hwmod,
1904         .slave  = &omap3xxx_l4_sec_hwmod,
1905         .user   = OCP_USER_MPU | OCP_USER_SDMA,
1906 };
1907
1908 /* IVA2 <- L3 interface */
1909 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
1910         .master         = &omap3xxx_l3_main_hwmod,
1911         .slave          = &omap3xxx_iva_hwmod,
1912         .clk            = "core_l3_ick",
1913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1914 };
1915
1916
1917 /* l4_wkup -> timer1 */
1918 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
1919         .master         = &omap3xxx_l4_wkup_hwmod,
1920         .slave          = &omap3xxx_timer1_hwmod,
1921         .clk            = "gpt1_ick",
1922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1923 };
1924
1925
1926 /* l4_per -> timer2 */
1927 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
1928         .master         = &omap3xxx_l4_per_hwmod,
1929         .slave          = &omap3xxx_timer2_hwmod,
1930         .clk            = "gpt2_ick",
1931         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1932 };
1933
1934
1935 /* l4_per -> timer3 */
1936 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
1937         .master         = &omap3xxx_l4_per_hwmod,
1938         .slave          = &omap3xxx_timer3_hwmod,
1939         .clk            = "gpt3_ick",
1940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1941 };
1942
1943
1944 /* l4_per -> timer4 */
1945 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
1946         .master         = &omap3xxx_l4_per_hwmod,
1947         .slave          = &omap3xxx_timer4_hwmod,
1948         .clk            = "gpt4_ick",
1949         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1950 };
1951
1952
1953 /* l4_per -> timer5 */
1954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
1955         .master         = &omap3xxx_l4_per_hwmod,
1956         .slave          = &omap3xxx_timer5_hwmod,
1957         .clk            = "gpt5_ick",
1958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1959 };
1960
1961
1962 /* l4_per -> timer6 */
1963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
1964         .master         = &omap3xxx_l4_per_hwmod,
1965         .slave          = &omap3xxx_timer6_hwmod,
1966         .clk            = "gpt6_ick",
1967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1968 };
1969
1970
1971 /* l4_per -> timer7 */
1972 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
1973         .master         = &omap3xxx_l4_per_hwmod,
1974         .slave          = &omap3xxx_timer7_hwmod,
1975         .clk            = "gpt7_ick",
1976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1977 };
1978
1979
1980 /* l4_per -> timer8 */
1981 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
1982         .master         = &omap3xxx_l4_per_hwmod,
1983         .slave          = &omap3xxx_timer8_hwmod,
1984         .clk            = "gpt8_ick",
1985         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1986 };
1987
1988
1989 /* l4_per -> timer9 */
1990 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1991         .master         = &omap3xxx_l4_per_hwmod,
1992         .slave          = &omap3xxx_timer9_hwmod,
1993         .clk            = "gpt9_ick",
1994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1995 };
1996
1997 /* l4_core -> timer10 */
1998 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1999         .master         = &omap3xxx_l4_core_hwmod,
2000         .slave          = &omap3xxx_timer10_hwmod,
2001         .clk            = "gpt10_ick",
2002         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2003 };
2004
2005 /* l4_core -> timer11 */
2006 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2007         .master         = &omap3xxx_l4_core_hwmod,
2008         .slave          = &omap3xxx_timer11_hwmod,
2009         .clk            = "gpt11_ick",
2010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2011 };
2012
2013
2014 /* l4_core -> timer12 */
2015 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2016         .master         = &omap3xxx_l4_sec_hwmod,
2017         .slave          = &omap3xxx_timer12_hwmod,
2018         .clk            = "gpt12_ick",
2019         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2020 };
2021
2022 /* l4_wkup -> wd_timer2 */
2023
2024 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2025         .master         = &omap3xxx_l4_wkup_hwmod,
2026         .slave          = &omap3xxx_wd_timer2_hwmod,
2027         .clk            = "wdt2_ick",
2028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2029 };
2030
2031 /* l4_core -> dss */
2032 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2033         .master         = &omap3xxx_l4_core_hwmod,
2034         .slave          = &omap3430es1_dss_core_hwmod,
2035         .clk            = "dss_ick",
2036         .fw = {
2037                 .omap2 = {
2038                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2039                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2040                         .flags  = OMAP_FIREWALL_L4,
2041                 },
2042         },
2043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2044 };
2045
2046 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2047         .master         = &omap3xxx_l4_core_hwmod,
2048         .slave          = &omap3xxx_dss_core_hwmod,
2049         .clk            = "dss_ick",
2050         .fw = {
2051                 .omap2 = {
2052                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2053                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2054                         .flags  = OMAP_FIREWALL_L4,
2055                 },
2056         },
2057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2058 };
2059
2060 /* l4_core -> dss_dispc */
2061 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2062         .master         = &omap3xxx_l4_core_hwmod,
2063         .slave          = &omap3xxx_dss_dispc_hwmod,
2064         .clk            = "dss_ick",
2065         .fw = {
2066                 .omap2 = {
2067                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2068                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2069                         .flags  = OMAP_FIREWALL_L4,
2070                 },
2071         },
2072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2073 };
2074
2075 /* l4_core -> dss_dsi1 */
2076 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2077         .master         = &omap3xxx_l4_core_hwmod,
2078         .slave          = &omap3xxx_dss_dsi1_hwmod,
2079         .clk            = "dss_ick",
2080         .fw = {
2081                 .omap2 = {
2082                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2083                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2084                         .flags  = OMAP_FIREWALL_L4,
2085                 },
2086         },
2087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2088 };
2089
2090 /* l4_core -> dss_rfbi */
2091 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2092         .master         = &omap3xxx_l4_core_hwmod,
2093         .slave          = &omap3xxx_dss_rfbi_hwmod,
2094         .clk            = "dss_ick",
2095         .fw = {
2096                 .omap2 = {
2097                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2098                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2099                         .flags  = OMAP_FIREWALL_L4,
2100                 },
2101         },
2102         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2103 };
2104
2105 /* l4_core -> dss_venc */
2106 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2107         .master         = &omap3xxx_l4_core_hwmod,
2108         .slave          = &omap3xxx_dss_venc_hwmod,
2109         .clk            = "dss_ick",
2110         .fw = {
2111                 .omap2 = {
2112                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2113                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2114                         .flags  = OMAP_FIREWALL_L4,
2115                 },
2116         },
2117         .flags          = OCPIF_SWSUP_IDLE,
2118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2119 };
2120
2121 /* l4_wkup -> gpio1 */
2122
2123 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2124         .master         = &omap3xxx_l4_wkup_hwmod,
2125         .slave          = &omap3xxx_gpio1_hwmod,
2126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2127 };
2128
2129 /* l4_per -> gpio2 */
2130
2131 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2132         .master         = &omap3xxx_l4_per_hwmod,
2133         .slave          = &omap3xxx_gpio2_hwmod,
2134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2135 };
2136
2137 /* l4_per -> gpio3 */
2138
2139 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2140         .master         = &omap3xxx_l4_per_hwmod,
2141         .slave          = &omap3xxx_gpio3_hwmod,
2142         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2143 };
2144
2145 /*
2146  * 'mmu' class
2147  * The memory management unit performs virtual to physical address translation
2148  * for its requestors.
2149  */
2150
2151 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2152         .rev_offs       = 0x000,
2153         .sysc_offs      = 0x010,
2154         .syss_offs      = 0x014,
2155         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2156                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2157         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2158         .sysc_fields    = &omap_hwmod_sysc_type1,
2159 };
2160
2161 static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
2162         .name = "mmu",
2163         .sysc = &mmu_sysc,
2164 };
2165
2166 /* mmu isp */
2167 static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
2168
2169 /* l4_core -> mmu isp */
2170 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
2171         .master         = &omap3xxx_l4_core_hwmod,
2172         .slave          = &omap3xxx_mmu_isp_hwmod,
2173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2174 };
2175
2176 static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
2177         .name           = "mmu_isp",
2178         .class          = &omap3xxx_mmu_hwmod_class,
2179         .main_clk       = "cam_ick",
2180         .flags          = HWMOD_NO_IDLEST,
2181 };
2182
2183 /* mmu iva */
2184
2185 static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
2186
2187 static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
2188         { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
2189 };
2190
2191 /* l3_main -> iva mmu */
2192 static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
2193         .master         = &omap3xxx_l3_main_hwmod,
2194         .slave          = &omap3xxx_mmu_iva_hwmod,
2195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2196 };
2197
2198 static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
2199         .name           = "mmu_iva",
2200         .class          = &omap3xxx_mmu_hwmod_class,
2201         .clkdm_name     = "iva2_clkdm",
2202         .rst_lines      = omap3xxx_mmu_iva_resets,
2203         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
2204         .main_clk       = "iva2_ck",
2205         .prcm = {
2206                 .omap2 = {
2207                         .module_offs = OMAP3430_IVA2_MOD,
2208                         .idlest_reg_id = 1,
2209                         .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
2210                 },
2211         },
2212         .flags          = HWMOD_NO_IDLEST,
2213 };
2214
2215 /* l4_per -> gpio4 */
2216
2217 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2218         .master         = &omap3xxx_l4_per_hwmod,
2219         .slave          = &omap3xxx_gpio4_hwmod,
2220         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2221 };
2222
2223 /* l4_per -> gpio5 */
2224
2225 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2226         .master         = &omap3xxx_l4_per_hwmod,
2227         .slave          = &omap3xxx_gpio5_hwmod,
2228         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2229 };
2230
2231 /* l4_per -> gpio6 */
2232
2233 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2234         .master         = &omap3xxx_l4_per_hwmod,
2235         .slave          = &omap3xxx_gpio6_hwmod,
2236         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2237 };
2238
2239 /* dma_system -> L3 */
2240 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2241         .master         = &omap3xxx_dma_system_hwmod,
2242         .slave          = &omap3xxx_l3_main_hwmod,
2243         .clk            = "core_l3_ick",
2244         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2245 };
2246
2247 /* l4_cfg -> dma_system */
2248 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2249         .master         = &omap3xxx_l4_core_hwmod,
2250         .slave          = &omap3xxx_dma_system_hwmod,
2251         .clk            = "core_l4_ick",
2252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2253 };
2254
2255
2256 /* l4_core -> mcbsp1 */
2257 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2258         .master         = &omap3xxx_l4_core_hwmod,
2259         .slave          = &omap3xxx_mcbsp1_hwmod,
2260         .clk            = "mcbsp1_ick",
2261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2262 };
2263
2264
2265 /* l4_per -> mcbsp2 */
2266 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2267         .master         = &omap3xxx_l4_per_hwmod,
2268         .slave          = &omap3xxx_mcbsp2_hwmod,
2269         .clk            = "mcbsp2_ick",
2270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2271 };
2272
2273
2274 /* l4_per -> mcbsp3 */
2275 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2276         .master         = &omap3xxx_l4_per_hwmod,
2277         .slave          = &omap3xxx_mcbsp3_hwmod,
2278         .clk            = "mcbsp3_ick",
2279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2280 };
2281
2282
2283 /* l4_per -> mcbsp4 */
2284 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2285         .master         = &omap3xxx_l4_per_hwmod,
2286         .slave          = &omap3xxx_mcbsp4_hwmod,
2287         .clk            = "mcbsp4_ick",
2288         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2289 };
2290
2291
2292 /* l4_core -> mcbsp5 */
2293 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2294         .master         = &omap3xxx_l4_core_hwmod,
2295         .slave          = &omap3xxx_mcbsp5_hwmod,
2296         .clk            = "mcbsp5_ick",
2297         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2298 };
2299
2300
2301 /* l4_per -> mcbsp2_sidetone */
2302 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2303         .master         = &omap3xxx_l4_per_hwmod,
2304         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2305         .clk            = "mcbsp2_ick",
2306         .user           = OCP_USER_MPU,
2307 };
2308
2309
2310 /* l4_per -> mcbsp3_sidetone */
2311 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2312         .master         = &omap3xxx_l4_per_hwmod,
2313         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2314         .clk            = "mcbsp3_ick",
2315         .user           = OCP_USER_MPU,
2316 };
2317
2318 /* l4_core -> mailbox */
2319 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2320         .master         = &omap3xxx_l4_core_hwmod,
2321         .slave          = &omap3xxx_mailbox_hwmod,
2322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2323 };
2324
2325 /* l4 core -> mcspi1 interface */
2326 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2327         .master         = &omap3xxx_l4_core_hwmod,
2328         .slave          = &omap34xx_mcspi1,
2329         .clk            = "mcspi1_ick",
2330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2331 };
2332
2333 /* l4 core -> mcspi2 interface */
2334 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2335         .master         = &omap3xxx_l4_core_hwmod,
2336         .slave          = &omap34xx_mcspi2,
2337         .clk            = "mcspi2_ick",
2338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2339 };
2340
2341 /* l4 core -> mcspi3 interface */
2342 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2343         .master         = &omap3xxx_l4_core_hwmod,
2344         .slave          = &omap34xx_mcspi3,
2345         .clk            = "mcspi3_ick",
2346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2347 };
2348
2349 /* l4 core -> mcspi4 interface */
2350
2351 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2352         .master         = &omap3xxx_l4_core_hwmod,
2353         .slave          = &omap34xx_mcspi4,
2354         .clk            = "mcspi4_ick",
2355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2356 };
2357
2358 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
2359         .master         = &omap3xxx_usb_host_hs_hwmod,
2360         .slave          = &omap3xxx_l3_main_hwmod,
2361         .clk            = "core_l3_ick",
2362         .user           = OCP_USER_MPU,
2363 };
2364
2365
2366 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
2367         .master         = &omap3xxx_l4_core_hwmod,
2368         .slave          = &omap3xxx_usb_host_hs_hwmod,
2369         .clk            = "usbhost_ick",
2370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2371 };
2372
2373
2374 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
2375         .master         = &omap3xxx_l4_core_hwmod,
2376         .slave          = &omap3xxx_usb_tll_hs_hwmod,
2377         .clk            = "usbtll_ick",
2378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2379 };
2380
2381 /* l4_core -> hdq1w interface */
2382 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
2383         .master         = &omap3xxx_l4_core_hwmod,
2384         .slave          = &omap3xxx_hdq1w_hwmod,
2385         .clk            = "hdq_ick",
2386         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2387         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
2388 };
2389
2390 /* l4_wkup -> 32ksync_counter */
2391
2392
2393 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
2394         .master         = &omap3xxx_l4_wkup_hwmod,
2395         .slave          = &omap3xxx_counter_32k_hwmod,
2396         .clk            = "omap_32ksync_ick",
2397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2398 };
2399
2400 /* am35xx has Davinci MDIO & EMAC */
2401 static struct omap_hwmod_class am35xx_mdio_class = {
2402         .name = "davinci_mdio",
2403 };
2404
2405 static struct omap_hwmod am35xx_mdio_hwmod = {
2406         .name           = "davinci_mdio",
2407         .class          = &am35xx_mdio_class,
2408         .flags          = HWMOD_NO_IDLEST,
2409 };
2410
2411 /*
2412  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2413  * but this will probably require some additional hwmod core support,
2414  * so is left as a future to-do item.
2415  */
2416 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
2417         .master         = &am35xx_mdio_hwmod,
2418         .slave          = &omap3xxx_l3_main_hwmod,
2419         .clk            = "emac_fck",
2420         .user           = OCP_USER_MPU,
2421 };
2422
2423 /* l4_core -> davinci mdio  */
2424 /*
2425  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2426  * but this will probably require some additional hwmod core support,
2427  * so is left as a future to-do item.
2428  */
2429 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
2430         .master         = &omap3xxx_l4_core_hwmod,
2431         .slave          = &am35xx_mdio_hwmod,
2432         .clk            = "emac_fck",
2433         .user           = OCP_USER_MPU,
2434 };
2435
2436 static struct omap_hwmod_class am35xx_emac_class = {
2437         .name = "davinci_emac",
2438 };
2439
2440 static struct omap_hwmod am35xx_emac_hwmod = {
2441         .name           = "davinci_emac",
2442         .class          = &am35xx_emac_class,
2443         /*
2444          * According to Mark Greer, the MPU will not return from WFI
2445          * when the EMAC signals an interrupt.
2446          * http://www.spinics.net/lists/arm-kernel/msg174734.html
2447          */
2448         .flags          = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
2449 };
2450
2451 /* l3_core -> davinci emac interface */
2452 /*
2453  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
2454  * but this will probably require some additional hwmod core support,
2455  * so is left as a future to-do item.
2456  */
2457 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
2458         .master         = &am35xx_emac_hwmod,
2459         .slave          = &omap3xxx_l3_main_hwmod,
2460         .clk            = "emac_ick",
2461         .user           = OCP_USER_MPU,
2462 };
2463
2464 /* l4_core -> davinci emac  */
2465 /*
2466  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
2467  * but this will probably require some additional hwmod core support,
2468  * so is left as a future to-do item.
2469  */
2470 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
2471         .master         = &omap3xxx_l4_core_hwmod,
2472         .slave          = &am35xx_emac_hwmod,
2473         .clk            = "emac_ick",
2474         .user           = OCP_USER_MPU,
2475 };
2476
2477 static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
2478         .master         = &omap3xxx_l3_main_hwmod,
2479         .slave          = &omap3xxx_gpmc_hwmod,
2480         .clk            = "core_l3_ick",
2481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2482 };
2483
2484 /* l4_core -> SHAM2 (SHA1/MD5) (similar to omap24xx) */
2485 static struct omap_hwmod_class_sysconfig omap3_sham_sysc = {
2486         .rev_offs       = 0x5c,
2487         .sysc_offs      = 0x60,
2488         .syss_offs      = 0x64,
2489         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2490                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2491         .sysc_fields    = &omap3_sham_sysc_fields,
2492 };
2493
2494 static struct omap_hwmod_class omap3xxx_sham_class = {
2495         .name   = "sham",
2496         .sysc   = &omap3_sham_sysc,
2497 };
2498
2499
2500
2501 static struct omap_hwmod omap3xxx_sham_hwmod = {
2502         .name           = "sham",
2503         .main_clk       = "sha12_ick",
2504         .prcm           = {
2505                 .omap2 = {
2506                         .module_offs = CORE_MOD,
2507                         .idlest_reg_id = 1,
2508                         .idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
2509                 },
2510         },
2511         .class          = &omap3xxx_sham_class,
2512 };
2513
2514
2515 static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
2516         .master         = &omap3xxx_l4_core_hwmod,
2517         .slave          = &omap3xxx_sham_hwmod,
2518         .clk            = "sha12_ick",
2519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2520 };
2521
2522 /* l4_core -> AES */
2523 static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
2524         .rev_offs       = 0x44,
2525         .sysc_offs      = 0x48,
2526         .syss_offs      = 0x4c,
2527         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2528                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2529         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2530         .sysc_fields    = &omap3xxx_aes_sysc_fields,
2531 };
2532
2533 static struct omap_hwmod_class omap3xxx_aes_class = {
2534         .name   = "aes",
2535         .sysc   = &omap3_aes_sysc,
2536 };
2537
2538
2539 static struct omap_hwmod omap3xxx_aes_hwmod = {
2540         .name           = "aes",
2541         .main_clk       = "aes2_ick",
2542         .prcm           = {
2543                 .omap2 = {
2544                         .module_offs = CORE_MOD,
2545                         .idlest_reg_id = 1,
2546                         .idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
2547                 },
2548         },
2549         .class          = &omap3xxx_aes_class,
2550 };
2551
2552
2553 static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
2554         .master         = &omap3xxx_l4_core_hwmod,
2555         .slave          = &omap3xxx_aes_hwmod,
2556         .clk            = "aes2_ick",
2557         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2558 };
2559
2560 /*
2561  * 'ssi' class
2562  * synchronous serial interface (multichannel and full-duplex serial if)
2563  */
2564
2565 static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
2566         .rev_offs       = 0x0000,
2567         .sysc_offs      = 0x0010,
2568         .syss_offs      = 0x0014,
2569         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
2570                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2571         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2572         .sysc_fields    = &omap_hwmod_sysc_type1,
2573 };
2574
2575 static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
2576         .name   = "ssi",
2577         .sysc   = &omap34xx_ssi_sysc,
2578 };
2579
2580 static struct omap_hwmod omap3xxx_ssi_hwmod = {
2581         .name           = "ssi",
2582         .class          = &omap3xxx_ssi_hwmod_class,
2583         .clkdm_name     = "core_l4_clkdm",
2584         .main_clk       = "ssi_ssr_fck",
2585         .prcm           = {
2586                 .omap2 = {
2587                         .module_offs            = CORE_MOD,
2588                         .idlest_reg_id          = 1,
2589                         .idlest_idle_bit        = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
2590                 },
2591         },
2592 };
2593
2594 /* L4 CORE -> SSI */
2595 static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
2596         .master         = &omap3xxx_l4_core_hwmod,
2597         .slave          = &omap3xxx_ssi_hwmod,
2598         .clk            = "ssi_ick",
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
2603         &omap3xxx_l3_main__l4_core,
2604         &omap3xxx_l3_main__l4_per,
2605         &omap3xxx_mpu__l3_main,
2606         &omap3xxx_l3_main__l4_debugss,
2607         &omap3xxx_l4_core__l4_wkup,
2608         &omap3xxx_l4_core__mmc3,
2609         &omap3_l4_core__uart1,
2610         &omap3_l4_core__uart2,
2611         &omap3_l4_per__uart3,
2612         &omap3_l4_core__i2c1,
2613         &omap3_l4_core__i2c2,
2614         &omap3_l4_core__i2c3,
2615         &omap3xxx_l4_wkup__l4_sec,
2616         &omap3xxx_l4_wkup__timer1,
2617         &omap3xxx_l4_per__timer2,
2618         &omap3xxx_l4_per__timer3,
2619         &omap3xxx_l4_per__timer4,
2620         &omap3xxx_l4_per__timer5,
2621         &omap3xxx_l4_per__timer6,
2622         &omap3xxx_l4_per__timer7,
2623         &omap3xxx_l4_per__timer8,
2624         &omap3xxx_l4_per__timer9,
2625         &omap3xxx_l4_core__timer10,
2626         &omap3xxx_l4_core__timer11,
2627         &omap3xxx_l4_wkup__wd_timer2,
2628         &omap3xxx_l4_wkup__gpio1,
2629         &omap3xxx_l4_per__gpio2,
2630         &omap3xxx_l4_per__gpio3,
2631         &omap3xxx_l4_per__gpio4,
2632         &omap3xxx_l4_per__gpio5,
2633         &omap3xxx_l4_per__gpio6,
2634         &omap3xxx_dma_system__l3,
2635         &omap3xxx_l4_core__dma_system,
2636         &omap3xxx_l4_core__mcbsp1,
2637         &omap3xxx_l4_per__mcbsp2,
2638         &omap3xxx_l4_per__mcbsp3,
2639         &omap3xxx_l4_per__mcbsp4,
2640         &omap3xxx_l4_core__mcbsp5,
2641         &omap3xxx_l4_per__mcbsp2_sidetone,
2642         &omap3xxx_l4_per__mcbsp3_sidetone,
2643         &omap34xx_l4_core__mcspi1,
2644         &omap34xx_l4_core__mcspi2,
2645         &omap34xx_l4_core__mcspi3,
2646         &omap34xx_l4_core__mcspi4,
2647         &omap3xxx_l4_wkup__counter_32k,
2648         &omap3xxx_l3_main__gpmc,
2649         NULL,
2650 };
2651
2652 /* GP-only hwmod links */
2653 static struct omap_hwmod_ocp_if *omap34xx_gp_hwmod_ocp_ifs[] __initdata = {
2654         &omap3xxx_l4_sec__timer12,
2655         NULL,
2656 };
2657
2658 static struct omap_hwmod_ocp_if *omap36xx_gp_hwmod_ocp_ifs[] __initdata = {
2659         &omap3xxx_l4_sec__timer12,
2660         NULL,
2661 };
2662
2663 static struct omap_hwmod_ocp_if *am35xx_gp_hwmod_ocp_ifs[] __initdata = {
2664         &omap3xxx_l4_sec__timer12,
2665         NULL,
2666 };
2667
2668 /* crypto hwmod links */
2669 static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
2670         &omap3xxx_l4_core__sham,
2671         NULL,
2672 };
2673
2674 static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
2675         &omap3xxx_l4_core__aes,
2676         NULL,
2677 };
2678
2679 static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
2680         &omap3xxx_l4_core__sham,
2681         NULL
2682 };
2683
2684 static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
2685         &omap3xxx_l4_core__aes,
2686         NULL
2687 };
2688
2689 /*
2690  * Apparently the SHA/MD5 and AES accelerator IP blocks are
2691  * only present on some AM35xx chips, and no one knows which
2692  * ones.  See
2693  * http://www.spinics.net/lists/arm-kernel/msg215466.html So
2694  * if you need these IP blocks on an AM35xx, try uncommenting
2695  * the following lines.
2696  */
2697 static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
2698         /* &omap3xxx_l4_core__sham, */
2699         NULL
2700 };
2701
2702 static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
2703         /* &omap3xxx_l4_core__aes, */
2704         NULL,
2705 };
2706
2707 /* 3430ES1-only hwmod links */
2708 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
2709         &omap3430es1_dss__l3,
2710         &omap3430es1_l4_core__dss,
2711         NULL,
2712 };
2713
2714 /* 3430ES2+-only hwmod links */
2715 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
2716         &omap3xxx_dss__l3,
2717         &omap3xxx_l4_core__dss,
2718         &omap3xxx_usbhsotg__l3,
2719         &omap3xxx_l4_core__usbhsotg,
2720         &omap3xxx_usb_host_hs__l3_main_2,
2721         &omap3xxx_l4_core__usb_host_hs,
2722         &omap3xxx_l4_core__usb_tll_hs,
2723         NULL,
2724 };
2725
2726 /* <= 3430ES3-only hwmod links */
2727 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
2728         &omap3xxx_l4_core__pre_es3_mmc1,
2729         &omap3xxx_l4_core__pre_es3_mmc2,
2730         NULL,
2731 };
2732
2733 /* 3430ES3+-only hwmod links */
2734 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
2735         &omap3xxx_l4_core__es3plus_mmc1,
2736         &omap3xxx_l4_core__es3plus_mmc2,
2737         NULL,
2738 };
2739
2740 /* 34xx-only hwmod links (all ES revisions) */
2741 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
2742         &omap3xxx_l3__iva,
2743         &omap34xx_l4_core__sr1,
2744         &omap34xx_l4_core__sr2,
2745         &omap3xxx_l4_core__mailbox,
2746         &omap3xxx_l4_core__hdq1w,
2747         &omap3xxx_sad2d__l3,
2748         &omap3xxx_l4_core__mmu_isp,
2749         &omap3xxx_l3_main__mmu_iva,
2750         &omap3xxx_l4_core__ssi,
2751         NULL,
2752 };
2753
2754 /* 36xx-only hwmod links (all ES revisions) */
2755 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
2756         &omap3xxx_l3__iva,
2757         &omap36xx_l4_per__uart4,
2758         &omap3xxx_dss__l3,
2759         &omap3xxx_l4_core__dss,
2760         &omap36xx_l4_core__sr1,
2761         &omap36xx_l4_core__sr2,
2762         &omap3xxx_usbhsotg__l3,
2763         &omap3xxx_l4_core__usbhsotg,
2764         &omap3xxx_l4_core__mailbox,
2765         &omap3xxx_usb_host_hs__l3_main_2,
2766         &omap3xxx_l4_core__usb_host_hs,
2767         &omap3xxx_l4_core__usb_tll_hs,
2768         &omap3xxx_l4_core__es3plus_mmc1,
2769         &omap3xxx_l4_core__es3plus_mmc2,
2770         &omap3xxx_l4_core__hdq1w,
2771         &omap3xxx_sad2d__l3,
2772         &omap3xxx_l4_core__mmu_isp,
2773         &omap3xxx_l3_main__mmu_iva,
2774         &omap3xxx_l4_core__ssi,
2775         NULL,
2776 };
2777
2778 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
2779         &omap3xxx_dss__l3,
2780         &omap3xxx_l4_core__dss,
2781         &am35xx_usbhsotg__l3,
2782         &am35xx_l4_core__usbhsotg,
2783         &am35xx_l4_core__uart4,
2784         &omap3xxx_usb_host_hs__l3_main_2,
2785         &omap3xxx_l4_core__usb_host_hs,
2786         &omap3xxx_l4_core__usb_tll_hs,
2787         &omap3xxx_l4_core__es3plus_mmc1,
2788         &omap3xxx_l4_core__es3plus_mmc2,
2789         &omap3xxx_l4_core__hdq1w,
2790         &am35xx_mdio__l3,
2791         &am35xx_l4_core__mdio,
2792         &am35xx_emac__l3,
2793         &am35xx_l4_core__emac,
2794         NULL,
2795 };
2796
2797 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
2798         &omap3xxx_l4_core__dss_dispc,
2799         &omap3xxx_l4_core__dss_dsi1,
2800         &omap3xxx_l4_core__dss_rfbi,
2801         &omap3xxx_l4_core__dss_venc,
2802         NULL,
2803 };
2804
2805 /**
2806  * omap3xxx_hwmod_is_hs_ip_block_usable - is a security IP block accessible?
2807  * @bus: struct device_node * for the top-level OMAP DT data
2808  * @dev_name: device name used in the DT file
2809  *
2810  * Determine whether a "secure" IP block @dev_name is usable by Linux.
2811  * There doesn't appear to be a 100% reliable way to determine this,
2812  * so we rely on heuristics.  If @bus is null, meaning there's no DT
2813  * data, then we only assume the IP block is accessible if the OMAP is
2814  * fused as a 'general-purpose' SoC.  If however DT data is present,
2815  * test to see if the IP block is described in the DT data and set to
2816  * 'status = "okay"'.  If so then we assume the ODM has configured the
2817  * OMAP firewalls to allow access to the IP block.
2818  *
2819  * Return: 0 if device named @dev_name is not likely to be accessible,
2820  * or 1 if it is likely to be accessible.
2821  */
2822 static bool __init omap3xxx_hwmod_is_hs_ip_block_usable(struct device_node *bus,
2823                                                         const char *dev_name)
2824 {
2825         struct device_node *node;
2826         bool available;
2827
2828         if (!bus)
2829                 return omap_type() == OMAP2_DEVICE_TYPE_GP;
2830
2831         node = of_get_child_by_name(bus, dev_name);
2832         available = of_device_is_available(node);
2833         of_node_put(node);
2834
2835         return available;
2836 }
2837
2838 int __init omap3xxx_hwmod_init(void)
2839 {
2840         int r;
2841         struct omap_hwmod_ocp_if **h = NULL, **h_gp = NULL, **h_sham = NULL;
2842         struct omap_hwmod_ocp_if **h_aes = NULL;
2843         struct device_node *bus;
2844         unsigned int rev;
2845
2846         omap_hwmod_init();
2847
2848         /* Register hwmod links common to all OMAP3 */
2849         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
2850         if (r < 0)
2851                 return r;
2852
2853         rev = omap_rev();
2854
2855         /*
2856          * Register hwmod links common to individual OMAP3 families, all
2857          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
2858          * All possible revisions should be included in this conditional.
2859          */
2860         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2861             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
2862             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
2863                 h = omap34xx_hwmod_ocp_ifs;
2864                 h_gp = omap34xx_gp_hwmod_ocp_ifs;
2865                 h_sham = omap34xx_sham_hwmod_ocp_ifs;
2866                 h_aes = omap34xx_aes_hwmod_ocp_ifs;
2867         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
2868                 h = am35xx_hwmod_ocp_ifs;
2869                 h_gp = am35xx_gp_hwmod_ocp_ifs;
2870                 h_sham = am35xx_sham_hwmod_ocp_ifs;
2871                 h_aes = am35xx_aes_hwmod_ocp_ifs;
2872         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
2873                    rev == OMAP3630_REV_ES1_2) {
2874                 h = omap36xx_hwmod_ocp_ifs;
2875                 h_gp = omap36xx_gp_hwmod_ocp_ifs;
2876                 h_sham = omap36xx_sham_hwmod_ocp_ifs;
2877                 h_aes = omap36xx_aes_hwmod_ocp_ifs;
2878         } else {
2879                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
2880                 return -EINVAL;
2881         }
2882
2883         r = omap_hwmod_register_links(h);
2884         if (r < 0)
2885                 return r;
2886
2887         /* Register GP-only hwmod links. */
2888         if (h_gp && omap_type() == OMAP2_DEVICE_TYPE_GP) {
2889                 r = omap_hwmod_register_links(h_gp);
2890                 if (r < 0)
2891                         return r;
2892         }
2893
2894         /*
2895          * Register crypto hwmod links only if they are not disabled in DT.
2896          * If DT information is missing, enable them only for GP devices.
2897          */
2898
2899         bus = of_find_node_by_name(NULL, "ocp");
2900
2901         if (h_sham && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "sham")) {
2902                 r = omap_hwmod_register_links(h_sham);
2903                 if (r < 0)
2904                         goto put_node;
2905         }
2906
2907         if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
2908                 r = omap_hwmod_register_links(h_aes);
2909                 if (r < 0)
2910                         goto put_node;
2911         }
2912         of_node_put(bus);
2913
2914         /*
2915          * Register hwmod links specific to certain ES levels of a
2916          * particular family of silicon (e.g., 34xx ES1.0)
2917          */
2918         h = NULL;
2919         if (rev == OMAP3430_REV_ES1_0) {
2920                 h = omap3430es1_hwmod_ocp_ifs;
2921         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
2922                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2923                    rev == OMAP3430_REV_ES3_1_2) {
2924                 h = omap3430es2plus_hwmod_ocp_ifs;
2925         }
2926
2927         if (h) {
2928                 r = omap_hwmod_register_links(h);
2929                 if (r < 0)
2930                         return r;
2931         }
2932
2933         h = NULL;
2934         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
2935             rev == OMAP3430_REV_ES2_1) {
2936                 h = omap3430_pre_es3_hwmod_ocp_ifs;
2937         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
2938                    rev == OMAP3430_REV_ES3_1_2) {
2939                 h = omap3430_es3plus_hwmod_ocp_ifs;
2940         }
2941
2942         if (h)
2943                 r = omap_hwmod_register_links(h);
2944         if (r < 0)
2945                 return r;
2946
2947         /*
2948          * DSS code presumes that dss_core hwmod is handled first,
2949          * _before_ any other DSS related hwmods so register common
2950          * DSS hwmod links last to ensure that dss_core is already
2951          * registered.  Otherwise some change things may happen, for
2952          * ex. if dispc is handled before dss_core and DSS is enabled
2953          * in bootloader DISPC will be reset with outputs enabled
2954          * which sometimes leads to unrecoverable L3 error.  XXX The
2955          * long-term fix to this is to ensure hwmods are set up in
2956          * dependency order in the hwmod core code.
2957          */
2958         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
2959
2960         return r;
2961
2962 put_node:
2963         of_node_put(bus);
2964         return r;
2965 }