arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   4  *
   5  * Copyright (C) 2009-2011 Nokia Corporation
   6  * Copyright (C) 2012 Texas Instruments, Inc.
   7  * Paul Walmsley
   8  *
   9  * XXX handle crossbar/shared link difference for L3?
  10  * XXX these should be marked initdata for multi-OMAP kernels
  11  */
  12
  13 #include <linux/platform_data/i2c-omap.h>
  14
  15 #include "omap_hwmod.h"
  16 #include "l3_2xxx.h"
  17 #include "l4_2xxx.h"
  18
  19 #include "omap_hwmod_common_data.h"
  20
  21 #include "cm-regbits-24xx.h"
  22 #include "prm-regbits-24xx.h"
  23 #include "i2c.h"
  24 #include "mmc.h"
  25 #include "wd_timer.h"
  26
  27 /*
  28  * OMAP2420 hardware module integration data
  29  *
  30  * All of the data in this section should be autogeneratable from the
  31  * TI hardware database or other technical documentation.  Data that
  32  * is driver-specific or driver-kernel integration-specific belongs
  33  * elsewhere.
  34  */
  35
  36 /*
  37  * IP blocks
  38  */
  39
  40 /* IVA1 (IVA1) */
  41 static struct omap_hwmod_class iva1_hwmod_class = {
  42         .name           = "iva1",
  43 };
  44
  45 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
  46         { .name = "iva", .rst_shift = 8 },
  47 };
  48
  49 static struct omap_hwmod omap2420_iva_hwmod = {
  50         .name           = "iva",
  51         .class          = &iva1_hwmod_class,
  52         .clkdm_name     = "iva1_clkdm",
  53         .rst_lines      = omap2420_iva_resets,
  54         .rst_lines_cnt  = ARRAY_SIZE(omap2420_iva_resets),
  55         .main_clk       = "iva1_ifck",
  56 };
  57
  58 /* DSP */
  59 static struct omap_hwmod_class dsp_hwmod_class = {
  60         .name           = "dsp",
  61 };
  62
  63 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
  64         { .name = "logic", .rst_shift = 0 },
  65         { .name = "mmu", .rst_shift = 1 },
  66 };
  67
  68 static struct omap_hwmod omap2420_dsp_hwmod = {
  69         .name           = "dsp",
  70         .class          = &dsp_hwmod_class,
  71         .clkdm_name     = "dsp_clkdm",
  72         .rst_lines      = omap2420_dsp_resets,
  73         .rst_lines_cnt  = ARRAY_SIZE(omap2420_dsp_resets),
  74         .main_clk       = "dsp_fck",
  75 };
  76
  77 /* I2C common */
  78 static struct omap_hwmod_class_sysconfig i2c_sysc = {
  79         .rev_offs       = 0x00,
  80         .sysc_offs      = 0x20,
  81         .syss_offs      = 0x10,
  82         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
  83         .sysc_fields    = &omap_hwmod_sysc_type1,
  84 };
  85
  86 static struct omap_hwmod_class i2c_class = {
  87         .name           = "i2c",
  88         .sysc           = &i2c_sysc,
  89         .reset          = &omap_i2c_reset,
  90 };
  91
  92 /* I2C1 */
  93 static struct omap_hwmod omap2420_i2c1_hwmod = {
  94         .name           = "i2c1",
  95         .main_clk       = "i2c1_fck",
  96         .prcm           = {
  97                 .omap2 = {
  98                         .module_offs = CORE_MOD,
  99                         .idlest_reg_id = 1,
 100                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
 101                 },
 102         },
 103         .class          = &i2c_class,
 104         /*
 105          * From mach-omap2/pm24xx.c: "Putting MPU into the WFI state
 106          * while a transfer is active seems to cause the I2C block to
 107          * timeout. Why? Good question."
 108          */
 109         .flags          = (HWMOD_16BIT_REG | HWMOD_BLOCK_WFI),
 110 };
 111
 112 /* I2C2 */
 113 static struct omap_hwmod omap2420_i2c2_hwmod = {
 114         .name           = "i2c2",
 115         .main_clk       = "i2c2_fck",
 116         .prcm           = {
 117                 .omap2 = {
 118                         .module_offs = CORE_MOD,
 119                         .idlest_reg_id = 1,
 120                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
 121                 },
 122         },
 123         .class          = &i2c_class,
 124         .flags          = HWMOD_16BIT_REG,
 125 };
 126
 127 /* mailbox */
 128 static struct omap_hwmod omap2420_mailbox_hwmod = {
 129         .name           = "mailbox",
 130         .class          = &omap2xxx_mailbox_hwmod_class,
 131         .main_clk       = "mailboxes_ick",
 132         .prcm           = {
 133                 .omap2 = {
 134                         .module_offs = CORE_MOD,
 135                         .idlest_reg_id = 1,
 136                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
 137                 },
 138         },
 139 };
 140
 141 /*
 142  * 'mcbsp' class
 143  * multi channel buffered serial port controller
 144  */
 145
 146 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
 147         .name = "mcbsp",
 148 };
 149
 150 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
 151         { .role = "pad_fck", .clk = "mcbsp_clks" },
 152         { .role = "prcm_fck", .clk = "func_96m_ck" },
 153 };
 154
 155 /* mcbsp1 */
 156 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
 157         .name           = "mcbsp1",
 158         .class          = &omap2420_mcbsp_hwmod_class,
 159         .main_clk       = "mcbsp1_fck",
 160         .prcm           = {
 161                 .omap2 = {
 162                         .module_offs = CORE_MOD,
 163                         .idlest_reg_id = 1,
 164                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
 165                 },
 166         },
 167         .opt_clks       = mcbsp_opt_clks,
 168         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 169 };
 170
 171 /* mcbsp2 */
 172 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
 173         .name           = "mcbsp2",
 174         .class          = &omap2420_mcbsp_hwmod_class,
 175         .main_clk       = "mcbsp2_fck",
 176         .prcm           = {
 177                 .omap2 = {
 178                         .module_offs = CORE_MOD,
 179                         .idlest_reg_id = 1,
 180                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
 181                 },
 182         },
 183         .opt_clks       = mcbsp_opt_clks,
 184         .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 185 };
 186
 187 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
 188         .rev_offs       = 0x3c,
 189         .sysc_offs      = 0x64,
 190         .syss_offs      = 0x68,
 191         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 192         .sysc_fields    = &omap_hwmod_sysc_type1,
 193 };
 194
 195 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
 196         .name   = "msdi",
 197         .sysc   = &omap2420_msdi_sysc,
 198         .reset  = &omap_msdi_reset,
 199 };
 200
 201 /* msdi1 */
 202 static struct omap_hwmod omap2420_msdi1_hwmod = {
 203         .name           = "msdi1",
 204         .class          = &omap2420_msdi_hwmod_class,
 205         .main_clk       = "mmc_fck",
 206         .prcm           = {
 207                 .omap2 = {
 208                         .module_offs = CORE_MOD,
 209                         .idlest_reg_id = 1,
 210                         .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
 211                 },
 212         },
 213         .flags          = HWMOD_16BIT_REG,
 214 };
 215
 216 /* HDQ1W/1-wire */
 217 static struct omap_hwmod omap2420_hdq1w_hwmod = {
 218         .name           = "hdq1w",
 219         .main_clk       = "hdq_fck",
 220         .prcm           = {
 221                 .omap2 = {
 222                         .module_offs = CORE_MOD,
 223                         .idlest_reg_id = 1,
 224                         .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
 225                 },
 226         },
 227         .class          = &omap2_hdq1w_class,
 228 };
 229
 230 /*
 231  * interfaces
 232  */
 233
 234 /* L4 CORE -> I2C1 interface */
 235 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 236         .master         = &omap2xxx_l4_core_hwmod,
 237         .slave          = &omap2420_i2c1_hwmod,
 238         .clk            = "i2c1_ick",
 239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 240 };
 241
 242 /* L4 CORE -> I2C2 interface */
 243 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 244         .master         = &omap2xxx_l4_core_hwmod,
 245         .slave          = &omap2420_i2c2_hwmod,
 246         .clk            = "i2c2_ick",
 247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 248 };
 249
 250 /* IVA <- L3 interface */
 251 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 252         .master         = &omap2xxx_l3_main_hwmod,
 253         .slave          = &omap2420_iva_hwmod,
 254         .clk            = "core_l3_ck",
 255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 256 };
 257
 258 /* DSP <- L3 interface */
 259 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
 260         .master         = &omap2xxx_l3_main_hwmod,
 261         .slave          = &omap2420_dsp_hwmod,
 262         .clk            = "dsp_ick",
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* l4_wkup -> wd_timer2 */
 267 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 268         .master         = &omap2xxx_l4_wkup_hwmod,
 269         .slave          = &omap2xxx_wd_timer2_hwmod,
 270         .clk            = "mpu_wdt_ick",
 271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 272 };
 273
 274 /* l4_wkup -> gpio1 */
 275 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
 276         .master         = &omap2xxx_l4_wkup_hwmod,
 277         .slave          = &omap2xxx_gpio1_hwmod,
 278         .clk            = "gpios_ick",
 279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 280 };
 281
 282 /* l4_wkup -> gpio2 */
 283 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
 284         .master         = &omap2xxx_l4_wkup_hwmod,
 285         .slave          = &omap2xxx_gpio2_hwmod,
 286         .clk            = "gpios_ick",
 287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 288 };
 289
 290 /* l4_wkup -> gpio3 */
 291 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
 292         .master         = &omap2xxx_l4_wkup_hwmod,
 293         .slave          = &omap2xxx_gpio3_hwmod,
 294         .clk            = "gpios_ick",
 295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 296 };
 297
 298 /* l4_wkup -> gpio4 */
 299 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
 300         .master         = &omap2xxx_l4_wkup_hwmod,
 301         .slave          = &omap2xxx_gpio4_hwmod,
 302         .clk            = "gpios_ick",
 303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 304 };
 305
 306 /* l4_core -> mailbox */
 307 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
 308         .master         = &omap2xxx_l4_core_hwmod,
 309         .slave          = &omap2420_mailbox_hwmod,
 310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 311 };
 312
 313 /* l4_core -> mcbsp1 */
 314 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
 315         .master         = &omap2xxx_l4_core_hwmod,
 316         .slave          = &omap2420_mcbsp1_hwmod,
 317         .clk            = "mcbsp1_ick",
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* l4_core -> mcbsp2 */
 322 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
 323         .master         = &omap2xxx_l4_core_hwmod,
 324         .slave          = &omap2420_mcbsp2_hwmod,
 325         .clk            = "mcbsp2_ick",
 326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 327 };
 328
 329 /* l4_core -> msdi1 */
 330 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
 331         .master         = &omap2xxx_l4_core_hwmod,
 332         .slave          = &omap2420_msdi1_hwmod,
 333         .clk            = "mmc_ick",
 334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 335 };
 336
 337 /* l4_core -> hdq1w interface */
 338 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
 339         .master         = &omap2xxx_l4_core_hwmod,
 340         .slave          = &omap2420_hdq1w_hwmod,
 341         .clk            = "hdq_ick",
 342         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 343         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
 344 };
 345
 346 static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
 347         .master         = &omap2xxx_l3_main_hwmod,
 348         .slave          = &omap2xxx_gpmc_hwmod,
 349         .clk            = "core_l3_ck",
 350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 351 };
 352
 353 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 354         &omap2xxx_l3_main__l4_core,
 355         &omap2xxx_mpu__l3_main,
 356         &omap2xxx_dss__l3,
 357         &omap2xxx_l4_core__mcspi1,
 358         &omap2xxx_l4_core__mcspi2,
 359         &omap2xxx_l4_core__l4_wkup,
 360         &omap2_l4_core__uart1,
 361         &omap2_l4_core__uart2,
 362         &omap2_l4_core__uart3,
 363         &omap2420_l4_core__i2c1,
 364         &omap2420_l4_core__i2c2,
 365         &omap2420_l3__iva,
 366         &omap2420_l3__dsp,
 367         &omap2xxx_l4_core__timer3,
 368         &omap2xxx_l4_core__timer4,
 369         &omap2xxx_l4_core__timer5,
 370         &omap2xxx_l4_core__timer6,
 371         &omap2xxx_l4_core__timer7,
 372         &omap2xxx_l4_core__timer8,
 373         &omap2xxx_l4_core__timer9,
 374         &omap2xxx_l4_core__timer10,
 375         &omap2xxx_l4_core__timer11,
 376         &omap2xxx_l4_core__timer12,
 377         &omap2420_l4_wkup__wd_timer2,
 378         &omap2xxx_l4_core__dss,
 379         &omap2xxx_l4_core__dss_dispc,
 380         &omap2xxx_l4_core__dss_rfbi,
 381         &omap2xxx_l4_core__dss_venc,
 382         &omap2420_l4_wkup__gpio1,
 383         &omap2420_l4_wkup__gpio2,
 384         &omap2420_l4_wkup__gpio3,
 385         &omap2420_l4_wkup__gpio4,
 386         &omap2420_l4_core__mailbox,
 387         &omap2420_l4_core__mcbsp1,
 388         &omap2420_l4_core__mcbsp2,
 389         &omap2420_l4_core__msdi1,
 390         &omap2xxx_l4_core__rng,
 391         &omap2xxx_l4_core__sham,
 392         &omap2xxx_l4_core__aes,
 393         &omap2420_l4_core__hdq1w,
 394         &omap2420_l3__gpmc,
 395         NULL,
 396 };
 397
 398 int __init omap2420_hwmod_init(void)
 399 {
 400         omap_hwmod_init();
 401         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 402 }