2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4 * Copyright (C) 2009-2011 Nokia Corporation
5 * Copyright (C) 2012 Texas Instruments, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * XXX handle crossbar/shared link difference for L3?
13 * XXX these should be marked initdata for multi-OMAP kernels
15 #include <linux/platform_data/spi-omap2-mcspi.h>
17 #include <plat/omap_hwmod.h>
19 #include <plat/serial.h>
21 #include <plat/dmtimer.h>
26 #include "omap_hwmod_common_data.h"
28 #include "cm-regbits-24xx.h"
29 #include "prm-regbits-24xx.h"
33 * OMAP2420 hardware module integration data
35 * All of the data in this section should be autogeneratable from the
36 * TI hardware database or other technical documentation. Data that
37 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod_class iva1_hwmod_class = {
50 static struct omap_hwmod_rst_info omap2420_iva_resets[] = {
51 { .name = "iva", .rst_shift = 8 },
54 static struct omap_hwmod omap2420_iva_hwmod = {
56 .class = &iva1_hwmod_class,
57 .clkdm_name = "iva1_clkdm",
58 .rst_lines = omap2420_iva_resets,
59 .rst_lines_cnt = ARRAY_SIZE(omap2420_iva_resets),
60 .main_clk = "iva1_ifck",
64 static struct omap_hwmod_class dsp_hwmod_class = {
68 static struct omap_hwmod_rst_info omap2420_dsp_resets[] = {
69 { .name = "logic", .rst_shift = 0 },
70 { .name = "mmu", .rst_shift = 1 },
73 static struct omap_hwmod omap2420_dsp_hwmod = {
75 .class = &dsp_hwmod_class,
76 .clkdm_name = "dsp_clkdm",
77 .rst_lines = omap2420_dsp_resets,
78 .rst_lines_cnt = ARRAY_SIZE(omap2420_dsp_resets),
79 .main_clk = "dsp_fck",
83 static struct omap_hwmod_class_sysconfig i2c_sysc = {
87 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
88 .sysc_fields = &omap_hwmod_sysc_type1,
91 static struct omap_hwmod_class i2c_class = {
94 .rev = OMAP_I2C_IP_VERSION_1,
95 .reset = &omap_i2c_reset,
98 static struct omap_i2c_dev_attr i2c_dev_attr = {
99 .flags = OMAP_I2C_FLAG_NO_FIFO |
100 OMAP_I2C_FLAG_SIMPLE_CLOCK |
101 OMAP_I2C_FLAG_16BIT_DATA_REG |
102 OMAP_I2C_FLAG_BUS_SHIFT_2,
106 static struct omap_hwmod omap2420_i2c1_hwmod = {
108 .mpu_irqs = omap2_i2c1_mpu_irqs,
109 .sdma_reqs = omap2_i2c1_sdma_reqs,
110 .main_clk = "i2c1_fck",
113 .module_offs = CORE_MOD,
115 .module_bit = OMAP2420_EN_I2C1_SHIFT,
117 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
121 .dev_attr = &i2c_dev_attr,
122 .flags = HWMOD_16BIT_REG,
126 static struct omap_hwmod omap2420_i2c2_hwmod = {
128 .mpu_irqs = omap2_i2c2_mpu_irqs,
129 .sdma_reqs = omap2_i2c2_sdma_reqs,
130 .main_clk = "i2c2_fck",
133 .module_offs = CORE_MOD,
135 .module_bit = OMAP2420_EN_I2C2_SHIFT,
137 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
141 .dev_attr = &i2c_dev_attr,
142 .flags = HWMOD_16BIT_REG,
146 static struct omap_dma_dev_attr dma_dev_attr = {
147 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
148 IS_CSSA_32 | IS_CDSA_32,
152 static struct omap_hwmod omap2420_dma_system_hwmod = {
154 .class = &omap2xxx_dma_hwmod_class,
155 .mpu_irqs = omap2_dma_system_irqs,
156 .main_clk = "core_l3_ck",
157 .dev_attr = &dma_dev_attr,
158 .flags = HWMOD_NO_IDLEST,
162 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
163 { .name = "dsp", .irq = 26 + OMAP_INTC_START, },
164 { .name = "iva", .irq = 34 + OMAP_INTC_START, },
168 static struct omap_hwmod omap2420_mailbox_hwmod = {
170 .class = &omap2xxx_mailbox_hwmod_class,
171 .mpu_irqs = omap2420_mailbox_irqs,
172 .main_clk = "mailboxes_ick",
176 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
177 .module_offs = CORE_MOD,
179 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
186 * multi channel buffered serial port controller
189 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
193 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
194 { .role = "pad_fck", .clk = "mcbsp_clks" },
195 { .role = "prcm_fck", .clk = "func_96m_ck" },
199 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
200 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
201 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
205 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
207 .class = &omap2420_mcbsp_hwmod_class,
208 .mpu_irqs = omap2420_mcbsp1_irqs,
209 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
210 .main_clk = "mcbsp1_fck",
214 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
215 .module_offs = CORE_MOD,
217 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
220 .opt_clks = mcbsp_opt_clks,
221 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
225 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
226 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
227 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
231 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
233 .class = &omap2420_mcbsp_hwmod_class,
234 .mpu_irqs = omap2420_mcbsp2_irqs,
235 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
236 .main_clk = "mcbsp2_fck",
240 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
241 .module_offs = CORE_MOD,
243 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
246 .opt_clks = mcbsp_opt_clks,
247 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
250 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
254 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
255 .sysc_fields = &omap_hwmod_sysc_type1,
258 static struct omap_hwmod_class omap2420_msdi_hwmod_class = {
260 .sysc = &omap2420_msdi_sysc,
261 .reset = &omap_msdi_reset,
265 static struct omap_hwmod_irq_info omap2420_msdi1_irqs[] = {
266 { .irq = 83 + OMAP_INTC_START, },
270 static struct omap_hwmod_dma_info omap2420_msdi1_sdma_reqs[] = {
271 { .name = "tx", .dma_req = 61 }, /* OMAP24XX_DMA_MMC1_TX */
272 { .name = "rx", .dma_req = 62 }, /* OMAP24XX_DMA_MMC1_RX */
276 static struct omap_hwmod omap2420_msdi1_hwmod = {
278 .class = &omap2420_msdi_hwmod_class,
279 .mpu_irqs = omap2420_msdi1_irqs,
280 .sdma_reqs = omap2420_msdi1_sdma_reqs,
281 .main_clk = "mmc_fck",
285 .module_bit = OMAP2420_EN_MMC_SHIFT,
286 .module_offs = CORE_MOD,
288 .idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
291 .flags = HWMOD_16BIT_REG,
295 static struct omap_hwmod omap2420_hdq1w_hwmod = {
297 .mpu_irqs = omap2_hdq1w_mpu_irqs,
298 .main_clk = "hdq_fck",
301 .module_offs = CORE_MOD,
303 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
305 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
308 .class = &omap2_hdq1w_class,
315 /* L4 CORE -> I2C1 interface */
316 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
317 .master = &omap2xxx_l4_core_hwmod,
318 .slave = &omap2420_i2c1_hwmod,
320 .addr = omap2_i2c1_addr_space,
321 .user = OCP_USER_MPU | OCP_USER_SDMA,
324 /* L4 CORE -> I2C2 interface */
325 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
326 .master = &omap2xxx_l4_core_hwmod,
327 .slave = &omap2420_i2c2_hwmod,
329 .addr = omap2_i2c2_addr_space,
330 .user = OCP_USER_MPU | OCP_USER_SDMA,
333 /* IVA <- L3 interface */
334 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
335 .master = &omap2xxx_l3_main_hwmod,
336 .slave = &omap2420_iva_hwmod,
338 .user = OCP_USER_MPU | OCP_USER_SDMA,
341 /* DSP <- L3 interface */
342 static struct omap_hwmod_ocp_if omap2420_l3__dsp = {
343 .master = &omap2xxx_l3_main_hwmod,
344 .slave = &omap2420_dsp_hwmod,
346 .user = OCP_USER_MPU | OCP_USER_SDMA,
349 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
351 .pa_start = 0x48028000,
352 .pa_end = 0x48028000 + SZ_1K - 1,
353 .flags = ADDR_TYPE_RT
358 /* l4_wkup -> timer1 */
359 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
360 .master = &omap2xxx_l4_wkup_hwmod,
361 .slave = &omap2xxx_timer1_hwmod,
363 .addr = omap2420_timer1_addrs,
364 .user = OCP_USER_MPU | OCP_USER_SDMA,
367 /* l4_wkup -> wd_timer2 */
368 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
370 .pa_start = 0x48022000,
371 .pa_end = 0x4802207f,
372 .flags = ADDR_TYPE_RT
377 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
378 .master = &omap2xxx_l4_wkup_hwmod,
379 .slave = &omap2xxx_wd_timer2_hwmod,
380 .clk = "mpu_wdt_ick",
381 .addr = omap2420_wd_timer2_addrs,
382 .user = OCP_USER_MPU | OCP_USER_SDMA,
385 /* l4_wkup -> gpio1 */
386 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
388 .pa_start = 0x48018000,
389 .pa_end = 0x480181ff,
390 .flags = ADDR_TYPE_RT
395 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
396 .master = &omap2xxx_l4_wkup_hwmod,
397 .slave = &omap2xxx_gpio1_hwmod,
399 .addr = omap2420_gpio1_addr_space,
400 .user = OCP_USER_MPU | OCP_USER_SDMA,
403 /* l4_wkup -> gpio2 */
404 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
406 .pa_start = 0x4801a000,
407 .pa_end = 0x4801a1ff,
408 .flags = ADDR_TYPE_RT
413 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
414 .master = &omap2xxx_l4_wkup_hwmod,
415 .slave = &omap2xxx_gpio2_hwmod,
417 .addr = omap2420_gpio2_addr_space,
418 .user = OCP_USER_MPU | OCP_USER_SDMA,
421 /* l4_wkup -> gpio3 */
422 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
424 .pa_start = 0x4801c000,
425 .pa_end = 0x4801c1ff,
426 .flags = ADDR_TYPE_RT
431 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
432 .master = &omap2xxx_l4_wkup_hwmod,
433 .slave = &omap2xxx_gpio3_hwmod,
435 .addr = omap2420_gpio3_addr_space,
436 .user = OCP_USER_MPU | OCP_USER_SDMA,
439 /* l4_wkup -> gpio4 */
440 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
442 .pa_start = 0x4801e000,
443 .pa_end = 0x4801e1ff,
444 .flags = ADDR_TYPE_RT
449 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
450 .master = &omap2xxx_l4_wkup_hwmod,
451 .slave = &omap2xxx_gpio4_hwmod,
453 .addr = omap2420_gpio4_addr_space,
454 .user = OCP_USER_MPU | OCP_USER_SDMA,
457 /* dma_system -> L3 */
458 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
459 .master = &omap2420_dma_system_hwmod,
460 .slave = &omap2xxx_l3_main_hwmod,
462 .user = OCP_USER_MPU | OCP_USER_SDMA,
465 /* l4_core -> dma_system */
466 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
467 .master = &omap2xxx_l4_core_hwmod,
468 .slave = &omap2420_dma_system_hwmod,
470 .addr = omap2_dma_system_addrs,
471 .user = OCP_USER_MPU | OCP_USER_SDMA,
474 /* l4_core -> mailbox */
475 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
476 .master = &omap2xxx_l4_core_hwmod,
477 .slave = &omap2420_mailbox_hwmod,
478 .addr = omap2_mailbox_addrs,
479 .user = OCP_USER_MPU | OCP_USER_SDMA,
482 /* l4_core -> mcbsp1 */
483 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
484 .master = &omap2xxx_l4_core_hwmod,
485 .slave = &omap2420_mcbsp1_hwmod,
487 .addr = omap2_mcbsp1_addrs,
488 .user = OCP_USER_MPU | OCP_USER_SDMA,
491 /* l4_core -> mcbsp2 */
492 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
493 .master = &omap2xxx_l4_core_hwmod,
494 .slave = &omap2420_mcbsp2_hwmod,
496 .addr = omap2xxx_mcbsp2_addrs,
497 .user = OCP_USER_MPU | OCP_USER_SDMA,
500 static struct omap_hwmod_addr_space omap2420_msdi1_addrs[] = {
502 .pa_start = 0x4809c000,
503 .pa_end = 0x4809c000 + SZ_128 - 1,
504 .flags = ADDR_TYPE_RT,
509 /* l4_core -> msdi1 */
510 static struct omap_hwmod_ocp_if omap2420_l4_core__msdi1 = {
511 .master = &omap2xxx_l4_core_hwmod,
512 .slave = &omap2420_msdi1_hwmod,
514 .addr = omap2420_msdi1_addrs,
515 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 /* l4_core -> hdq1w interface */
519 static struct omap_hwmod_ocp_if omap2420_l4_core__hdq1w = {
520 .master = &omap2xxx_l4_core_hwmod,
521 .slave = &omap2420_hdq1w_hwmod,
523 .addr = omap2_hdq1w_addr_space,
524 .user = OCP_USER_MPU | OCP_USER_SDMA,
525 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
529 /* l4_wkup -> 32ksync_counter */
530 static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
532 .pa_start = 0x48004000,
533 .pa_end = 0x4800401f,
534 .flags = ADDR_TYPE_RT
539 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
540 .master = &omap2xxx_l4_wkup_hwmod,
541 .slave = &omap2xxx_counter_32k_hwmod,
542 .clk = "sync_32k_ick",
543 .addr = omap2420_counter_32k_addrs,
544 .user = OCP_USER_MPU | OCP_USER_SDMA,
547 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
548 &omap2xxx_l3_main__l4_core,
549 &omap2xxx_mpu__l3_main,
551 &omap2xxx_l4_core__mcspi1,
552 &omap2xxx_l4_core__mcspi2,
553 &omap2xxx_l4_core__l4_wkup,
554 &omap2_l4_core__uart1,
555 &omap2_l4_core__uart2,
556 &omap2_l4_core__uart3,
557 &omap2420_l4_core__i2c1,
558 &omap2420_l4_core__i2c2,
561 &omap2420_l4_wkup__timer1,
562 &omap2xxx_l4_core__timer2,
563 &omap2xxx_l4_core__timer3,
564 &omap2xxx_l4_core__timer4,
565 &omap2xxx_l4_core__timer5,
566 &omap2xxx_l4_core__timer6,
567 &omap2xxx_l4_core__timer7,
568 &omap2xxx_l4_core__timer8,
569 &omap2xxx_l4_core__timer9,
570 &omap2xxx_l4_core__timer10,
571 &omap2xxx_l4_core__timer11,
572 &omap2xxx_l4_core__timer12,
573 &omap2420_l4_wkup__wd_timer2,
574 &omap2xxx_l4_core__dss,
575 &omap2xxx_l4_core__dss_dispc,
576 &omap2xxx_l4_core__dss_rfbi,
577 &omap2xxx_l4_core__dss_venc,
578 &omap2420_l4_wkup__gpio1,
579 &omap2420_l4_wkup__gpio2,
580 &omap2420_l4_wkup__gpio3,
581 &omap2420_l4_wkup__gpio4,
582 &omap2420_dma_system__l3,
583 &omap2420_l4_core__dma_system,
584 &omap2420_l4_core__mailbox,
585 &omap2420_l4_core__mcbsp1,
586 &omap2420_l4_core__mcbsp2,
587 &omap2420_l4_core__msdi1,
588 &omap2420_l4_core__hdq1w,
589 &omap2420_l4_wkup__counter_32k,
593 int __init omap2420_hwmod_init(void)
596 return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);