arch/arm/mach-omap2/devices.c

   1 /*
   2  * linux/arch/arm/mach-omap2/devices.c
   3  *
   4  * OMAP2 platform device setup/initialization
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/io.h>
  17 #include <linux/clk.h>
  18
  19 #include <mach/hardware.h>
  20 #include <asm/mach-types.h>
  21 #include <asm/mach/map.h>
  22
  23 #include <mach/control.h>
  24 #include <mach/tc.h>
  25 #include <mach/board.h>
  26 #include <mach/mux.h>
  27 #include <mach/gpio.h>
  28 #include <mach/mmc.h>
  29
  30 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  31
  32 static struct resource cam_resources[] = {
  33         {
  34                 .start          = OMAP24XX_CAMERA_BASE,
  35                 .end            = OMAP24XX_CAMERA_BASE + 0xfff,
  36                 .flags          = IORESOURCE_MEM,
  37         },
  38         {
  39                 .start          = INT_24XX_CAM_IRQ,
  40                 .flags          = IORESOURCE_IRQ,
  41         }
  42 };
  43
  44 static struct platform_device omap_cam_device = {
  45         .name           = "omap24xxcam",
  46         .id             = -1,
  47         .num_resources  = ARRAY_SIZE(cam_resources),
  48         .resource       = cam_resources,
  49 };
  50
  51 static inline void omap_init_camera(void)
  52 {
  53         platform_device_register(&omap_cam_device);
  54 }
  55
  56 #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  57
  58 static struct resource omap3isp_resources[] = {
  59         {
  60                 .start          = OMAP3430_ISP_BASE,
  61                 .end            = OMAP3430_ISP_END,
  62                 .flags          = IORESOURCE_MEM,
  63         },
  64         {
  65                 .start          = OMAP3430_ISP_CBUFF_BASE,
  66                 .end            = OMAP3430_ISP_CBUFF_END,
  67                 .flags          = IORESOURCE_MEM,
  68         },
  69         {
  70                 .start          = OMAP3430_ISP_CCP2_BASE,
  71                 .end            = OMAP3430_ISP_CCP2_END,
  72                 .flags          = IORESOURCE_MEM,
  73         },
  74         {
  75                 .start          = OMAP3430_ISP_CCDC_BASE,
  76                 .end            = OMAP3430_ISP_CCDC_END,
  77                 .flags          = IORESOURCE_MEM,
  78         },
  79         {
  80                 .start          = OMAP3430_ISP_HIST_BASE,
  81                 .end            = OMAP3430_ISP_HIST_END,
  82                 .flags          = IORESOURCE_MEM,
  83         },
  84         {
  85                 .start          = OMAP3430_ISP_H3A_BASE,
  86                 .end            = OMAP3430_ISP_H3A_END,
  87                 .flags          = IORESOURCE_MEM,
  88         },
  89         {
  90                 .start          = OMAP3430_ISP_PREV_BASE,
  91                 .end            = OMAP3430_ISP_PREV_END,
  92                 .flags          = IORESOURCE_MEM,
  93         },
  94         {
  95                 .start          = OMAP3430_ISP_RESZ_BASE,
  96                 .end            = OMAP3430_ISP_RESZ_END,
  97                 .flags          = IORESOURCE_MEM,
  98         },
  99         {
 100                 .start          = OMAP3430_ISP_SBL_BASE,
 101                 .end            = OMAP3430_ISP_SBL_END,
 102                 .flags          = IORESOURCE_MEM,
 103         },
 104         {
 105                 .start          = OMAP3430_ISP_CSI2A_BASE,
 106                 .end            = OMAP3430_ISP_CSI2A_END,
 107                 .flags          = IORESOURCE_MEM,
 108         },
 109         {
 110                 .start          = OMAP3430_ISP_CSI2PHY_BASE,
 111                 .end            = OMAP3430_ISP_CSI2PHY_END,
 112                 .flags          = IORESOURCE_MEM,
 113         },
 114         {
 115                 .start          = INT_34XX_CAM_IRQ,
 116                 .flags          = IORESOURCE_IRQ,
 117         }
 118 };
 119
 120 static struct platform_device omap3isp_device = {
 121         .name           = "omap3isp",
 122         .id             = -1,
 123         .num_resources  = ARRAY_SIZE(omap3isp_resources),
 124         .resource       = omap3isp_resources,
 125 };
 126
 127 static inline void omap_init_camera(void)
 128 {
 129         platform_device_register(&omap3isp_device);
 130 }
 131 #else
 132 static inline void omap_init_camera(void)
 133 {
 134 }
 135 #endif
 136
 137 #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 138
 139 #define MBOX_REG_SIZE   0x120
 140
 141 static struct resource omap2_mbox_resources[] = {
 142         {
 143                 .start          = OMAP24XX_MAILBOX_BASE,
 144                 .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 145                 .flags          = IORESOURCE_MEM,
 146         },
 147         {
 148                 .start          = INT_24XX_MAIL_U0_MPU,
 149                 .flags          = IORESOURCE_IRQ,
 150         },
 151         {
 152                 .start          = INT_24XX_MAIL_U3_MPU,
 153                 .flags          = IORESOURCE_IRQ,
 154         },
 155 };
 156
 157 static struct resource omap3_mbox_resources[] = {
 158         {
 159                 .start          = OMAP34XX_MAILBOX_BASE,
 160                 .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
 161                 .flags          = IORESOURCE_MEM,
 162         },
 163         {
 164                 .start          = INT_24XX_MAIL_U0_MPU,
 165                 .flags          = IORESOURCE_IRQ,
 166         },
 167 };
 168
 169 static struct platform_device mbox_device = {
 170         .name           = "omap2-mailbox",
 171         .id             = -1,
 172 };
 173
 174 static inline void omap_init_mbox(void)
 175 {
 176         if (cpu_is_omap2420()) {
 177                 mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources);
 178                 mbox_device.resource = omap2_mbox_resources;
 179         } else if (cpu_is_omap3430()) {
 180                 mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources);
 181                 mbox_device.resource = omap3_mbox_resources;
 182         } else {
 183                 pr_err("%s: platform not supported\n", __func__);
 184                 return;
 185         }
 186         platform_device_register(&mbox_device);
 187 }
 188 #else
 189 static inline void omap_init_mbox(void) { }
 190 #endif /* CONFIG_OMAP_MBOX_FWK */
 191
 192 #if defined(CONFIG_OMAP_STI)
 193
 194 #if defined(CONFIG_ARCH_OMAP2)
 195
 196 #define OMAP2_STI_BASE          0x48068000
 197 #define OMAP2_STI_CHANNEL_BASE  0x54000000
 198 #define OMAP2_STI_IRQ           4
 199
 200 static struct resource sti_resources[] = {
 201         {
 202                 .start          = OMAP2_STI_BASE,
 203                 .end            = OMAP2_STI_BASE + 0x7ff,
 204                 .flags          = IORESOURCE_MEM,
 205         },
 206         {
 207                 .start          = OMAP2_STI_CHANNEL_BASE,
 208                 .end            = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
 209                 .flags          = IORESOURCE_MEM,
 210         },
 211         {
 212                 .start          = OMAP2_STI_IRQ,
 213                 .flags          = IORESOURCE_IRQ,
 214         }
 215 };
 216 #elif defined(CONFIG_ARCH_OMAP3)
 217
 218 #define OMAP3_SDTI_BASE         0x54500000
 219 #define OMAP3_SDTI_CHANNEL_BASE 0x54600000
 220
 221 static struct resource sti_resources[] = {
 222         {
 223                 .start          = OMAP3_SDTI_BASE,
 224                 .end            = OMAP3_SDTI_BASE + 0xFFF,
 225                 .flags          = IORESOURCE_MEM,
 226         },
 227         {
 228                 .start          = OMAP3_SDTI_CHANNEL_BASE,
 229                 .end            = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
 230                 .flags          = IORESOURCE_MEM,
 231         }
 232 };
 233
 234 #endif
 235
 236 static struct platform_device sti_device = {
 237         .name           = "sti",
 238         .id             = -1,
 239         .num_resources  = ARRAY_SIZE(sti_resources),
 240         .resource       = sti_resources,
 241 };
 242
 243 static inline void omap_init_sti(void)
 244 {
 245         platform_device_register(&sti_device);
 246 }
 247 #else
 248 static inline void omap_init_sti(void) {}
 249 #endif
 250
 251 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 252
 253 #include <mach/mcspi.h>
 254
 255 #define OMAP2_MCSPI1_BASE               0x48098000
 256 #define OMAP2_MCSPI2_BASE               0x4809a000
 257 #define OMAP2_MCSPI3_BASE               0x480b8000
 258 #define OMAP2_MCSPI4_BASE               0x480ba000
 259
 260 static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
 261         .num_cs         = 4,
 262 };
 263
 264 static struct resource omap2_mcspi1_resources[] = {
 265         {
 266                 .start          = OMAP2_MCSPI1_BASE,
 267                 .end            = OMAP2_MCSPI1_BASE + 0xff,
 268                 .flags          = IORESOURCE_MEM,
 269         },
 270 };
 271
 272 static struct platform_device omap2_mcspi1 = {
 273         .name           = "omap2_mcspi",
 274         .id             = 1,
 275         .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
 276         .resource       = omap2_mcspi1_resources,
 277         .dev            = {
 278                 .platform_data = &omap2_mcspi1_config,
 279         },
 280 };
 281
 282 static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
 283         .num_cs         = 2,
 284 };
 285
 286 static struct resource omap2_mcspi2_resources[] = {
 287         {
 288                 .start          = OMAP2_MCSPI2_BASE,
 289                 .end            = OMAP2_MCSPI2_BASE + 0xff,
 290                 .flags          = IORESOURCE_MEM,
 291         },
 292 };
 293
 294 static struct platform_device omap2_mcspi2 = {
 295         .name           = "omap2_mcspi",
 296         .id             = 2,
 297         .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
 298         .resource       = omap2_mcspi2_resources,
 299         .dev            = {
 300                 .platform_data = &omap2_mcspi2_config,
 301         },
 302 };
 303
 304 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 305 static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
 306         .num_cs         = 2,
 307 };
 308
 309 static struct resource omap2_mcspi3_resources[] = {
 310         {
 311         .start          = OMAP2_MCSPI3_BASE,
 312         .end            = OMAP2_MCSPI3_BASE + 0xff,
 313         .flags          = IORESOURCE_MEM,
 314         },
 315 };
 316
 317 static struct platform_device omap2_mcspi3 = {
 318         .name           = "omap2_mcspi",
 319         .id             = 3,
 320         .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
 321         .resource       = omap2_mcspi3_resources,
 322         .dev            = {
 323                 .platform_data = &omap2_mcspi3_config,
 324         },
 325 };
 326 #endif
 327
 328 #ifdef CONFIG_ARCH_OMAP3
 329 static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
 330         .num_cs         = 1,
 331 };
 332
 333 static struct resource omap2_mcspi4_resources[] = {
 334         {
 335                 .start          = OMAP2_MCSPI4_BASE,
 336                 .end            = OMAP2_MCSPI4_BASE + 0xff,
 337                 .flags          = IORESOURCE_MEM,
 338         },
 339 };
 340
 341 static struct platform_device omap2_mcspi4 = {
 342         .name           = "omap2_mcspi",
 343         .id             = 4,
 344         .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
 345         .resource       = omap2_mcspi4_resources,
 346         .dev            = {
 347                 .platform_data = &omap2_mcspi4_config,
 348         },
 349 };
 350 #endif
 351
 352 static void omap_init_mcspi(void)
 353 {
 354         platform_device_register(&omap2_mcspi1);
 355         platform_device_register(&omap2_mcspi2);
 356 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 357         if (cpu_is_omap2430() || cpu_is_omap343x())
 358                 platform_device_register(&omap2_mcspi3);
 359 #endif
 360 #ifdef CONFIG_ARCH_OMAP3
 361         if (cpu_is_omap343x())
 362                 platform_device_register(&omap2_mcspi4);
 363 #endif
 364 }
 365
 366 #else
 367 static inline void omap_init_mcspi(void) {}
 368 #endif
 369
 370 #ifdef CONFIG_OMAP_SHA1_MD5
 371 static struct resource sha1_md5_resources[] = {
 372         {
 373                 .start  = OMAP24XX_SEC_SHA1MD5_BASE,
 374                 .end    = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
 375                 .flags  = IORESOURCE_MEM,
 376         },
 377         {
 378                 .start  = INT_24XX_SHA1MD5,
 379                 .flags  = IORESOURCE_IRQ,
 380         }
 381 };
 382
 383 static struct platform_device sha1_md5_device = {
 384         .name           = "OMAP SHA1/MD5",
 385         .id             = -1,
 386         .num_resources  = ARRAY_SIZE(sha1_md5_resources),
 387         .resource       = sha1_md5_resources,
 388 };
 389
 390 static void omap_init_sha1_md5(void)
 391 {
 392         platform_device_register(&sha1_md5_device);
 393 }
 394 #else
 395 static inline void omap_init_sha1_md5(void) { }
 396 #endif
 397
 398 /*-------------------------------------------------------------------------*/
 399
 400 #ifdef CONFIG_ARCH_OMAP3
 401
 402 #define MMCHS_SYSCONFIG                 0x0010
 403 #define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
 404 #define MMCHS_SYSSTATUS                 0x0014
 405 #define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
 406
 407 static struct platform_device dummy_pdev = {
 408         .dev = {
 409                 .bus = &platform_bus_type,
 410         },
 411 };
 412
 413 /**
 414  * omap_hsmmc_reset() - Full reset of each HS-MMC controller
 415  *
 416  * Ensure that each MMC controller is fully reset.  Controllers
 417  * left in an unknown state (by bootloader) may prevent retention
 418  * or OFF-mode.  This is especially important in cases where the
 419  * MMC driver is not enabled, _or_ built as a module.
 420  *
 421  * In order for reset to work, interface, functional and debounce
 422  * clocks must be enabled.  The debounce clock comes from func_32k_clk
 423  * and is not under SW control, so we only enable i- and f-clocks.
 424  **/
 425 static void __init omap_hsmmc_reset(void)
 426 {
 427         u32 i, nr_controllers = cpu_is_omap34xx() ? OMAP34XX_NR_MMC :
 428                 OMAP24XX_NR_MMC;
 429
 430         for (i = 0; i < nr_controllers; i++) {
 431                 u32 v, base = 0;
 432                 struct clk *iclk, *fclk;
 433                 struct device *dev = &dummy_pdev.dev;
 434
 435                 switch (i) {
 436                 case 0:
 437                         base = OMAP2_MMC1_BASE;
 438                         break;
 439                 case 1:
 440                         base = OMAP2_MMC2_BASE;
 441                         break;
 442                 case 2:
 443                         base = OMAP3_MMC3_BASE;
 444                         break;
 445                 }
 446
 447                 dummy_pdev.id = i;
 448                 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
 449                 iclk = clk_get(dev, "ick");
 450                 if (iclk && clk_enable(iclk))
 451                         iclk = NULL;
 452
 453                 fclk = clk_get(dev, "fck");
 454                 if (fclk && clk_enable(fclk))
 455                         fclk = NULL;
 456
 457                 if (!iclk || !fclk) {
 458                         printk(KERN_WARNING
 459                                "%s: Unable to enable clocks for MMC%d, "
 460                                "cannot reset.\n",  __func__, i);
 461                         break;
 462                 }
 463
 464                 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
 465                 v = omap_readl(base + MMCHS_SYSSTATUS);
 466                 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
 467                          MMCHS_SYSSTATUS_RESETDONE))
 468                         cpu_relax();
 469
 470                 if (fclk) {
 471                         clk_disable(fclk);
 472                         clk_put(fclk);
 473                 }
 474                 if (iclk) {
 475                         clk_disable(iclk);
 476                         clk_put(iclk);
 477                 }
 478         }
 479 }
 480 #else
 481 static inline void omap_hsmmc_reset(void) {}
 482 #endif
 483
 484 #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
 485         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 486
 487 static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 488                         int controller_nr)
 489 {
 490         if (cpu_is_omap2420() && controller_nr == 0) {
 491                 omap_cfg_reg(H18_24XX_MMC_CMD);
 492                 omap_cfg_reg(H15_24XX_MMC_CLKI);
 493                 omap_cfg_reg(G19_24XX_MMC_CLKO);
 494                 omap_cfg_reg(F20_24XX_MMC_DAT0);
 495                 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
 496                 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
 497                 if (mmc_controller->slots[0].wires == 4) {
 498                         omap_cfg_reg(H14_24XX_MMC_DAT1);
 499                         omap_cfg_reg(E19_24XX_MMC_DAT2);
 500                         omap_cfg_reg(D19_24XX_MMC_DAT3);
 501                         omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
 502                         omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
 503                         omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
 504                 }
 505
 506                 /*
 507                  * Use internal loop-back in MMC/SDIO Module Input Clock
 508                  * selection
 509                  */
 510                 if (mmc_controller->slots[0].internal_clock) {
 511                         u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 512                         v |= (1 << 24);
 513                         omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
 514                 }
 515         }
 516
 517         if (cpu_is_omap3430()) {
 518                 if (controller_nr == 0) {
 519                         omap_cfg_reg(N28_3430_MMC1_CLK);
 520                         omap_cfg_reg(M27_3430_MMC1_CMD);
 521                         omap_cfg_reg(N27_3430_MMC1_DAT0);
 522                         if (mmc_controller->slots[0].wires == 4 ||
 523                                 mmc_controller->slots[0].wires == 8) {
 524                                 omap_cfg_reg(N26_3430_MMC1_DAT1);
 525                                 omap_cfg_reg(N25_3430_MMC1_DAT2);
 526                                 omap_cfg_reg(P28_3430_MMC1_DAT3);
 527                         }
 528                         if (mmc_controller->slots[0].wires == 8) {
 529                                 omap_cfg_reg(P27_3430_MMC1_DAT4);
 530                                 omap_cfg_reg(P26_3430_MMC1_DAT5);
 531                                 omap_cfg_reg(R27_3430_MMC1_DAT6);
 532                                 omap_cfg_reg(R25_3430_MMC1_DAT7);
 533                         }
 534                 }
 535                 if (controller_nr == 1) {
 536                         /* MMC2 */
 537                         omap_cfg_reg(AE2_3430_MMC2_CLK);
 538                         omap_cfg_reg(AG5_3430_MMC2_CMD);
 539                         omap_cfg_reg(AH5_3430_MMC2_DAT0);
 540
 541                         /*
 542                          * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
 543                          * in the board-*.c files
 544                          */
 545                         if (mmc_controller->slots[0].wires == 4 ||
 546                                 mmc_controller->slots[0].wires == 8) {
 547                                 omap_cfg_reg(AH4_3430_MMC2_DAT1);
 548                                 omap_cfg_reg(AG4_3430_MMC2_DAT2);
 549                                 omap_cfg_reg(AF4_3430_MMC2_DAT3);
 550                         }
 551                 }
 552
 553                 /*
 554                  * For MMC3 the pins need to be muxed in the board-*.c files
 555                  */
 556         }
 557 }
 558
 559 void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
 560                         int nr_controllers)
 561 {
 562         int i;
 563         char *name;
 564
 565         for (i = 0; i < nr_controllers; i++) {
 566                 unsigned long base, size;
 567                 unsigned int irq = 0;
 568
 569                 if (!mmc_data[i])
 570                         continue;
 571
 572                 omap2_mmc_mux(mmc_data[i], i);
 573
 574                 switch (i) {
 575                 case 0:
 576                         base = OMAP2_MMC1_BASE;
 577                         irq = INT_24XX_MMC_IRQ;
 578                         break;
 579                 case 1:
 580                         base = OMAP2_MMC2_BASE;
 581                         irq = INT_24XX_MMC2_IRQ;
 582                         break;
 583                 case 2:
 584                         if (!cpu_is_omap34xx())
 585                                 return;
 586                         base = OMAP3_MMC3_BASE;
 587                         irq = INT_34XX_MMC3_IRQ;
 588                         break;
 589                 default:
 590                         continue;
 591                 }
 592
 593                 if (cpu_is_omap2420()) {
 594                         size = OMAP2420_MMC_SIZE;
 595                         name = "mmci-omap";
 596                 } else {
 597                         size = HSMMC_SIZE;
 598                         name = "mmci-omap-hs";
 599                 }
 600                 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
 601         };
 602 }
 603
 604 #endif
 605
 606 /*-------------------------------------------------------------------------*/
 607
 608 #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
 609 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
 610 #define OMAP_HDQ_BASE   0x480B2000
 611 #endif
 612 static struct resource omap_hdq_resources[] = {
 613         {
 614                 .start          = OMAP_HDQ_BASE,
 615                 .end            = OMAP_HDQ_BASE + 0x1C,
 616                 .flags          = IORESOURCE_MEM,
 617         },
 618         {
 619                 .start          = INT_24XX_HDQ_IRQ,
 620                 .flags          = IORESOURCE_IRQ,
 621         },
 622 };
 623 static struct platform_device omap_hdq_dev = {
 624         .name = "omap_hdq",
 625         .id = 0,
 626         .dev = {
 627                 .platform_data = NULL,
 628         },
 629         .num_resources  = ARRAY_SIZE(omap_hdq_resources),
 630         .resource       = omap_hdq_resources,
 631 };
 632 static inline void omap_hdq_init(void)
 633 {
 634         (void) platform_device_register(&omap_hdq_dev);
 635 }
 636 #else
 637 static inline void omap_hdq_init(void) {}
 638 #endif
 639
 640 /*-------------------------------------------------------------------------*/
 641
 642 static int __init omap2_init_devices(void)
 643 {
 644         /* please keep these calls, and their implementations above,
 645          * in alphabetical order so they're easier to sort through.
 646          */
 647         omap_hsmmc_reset();
 648         omap_init_camera();
 649         omap_init_mbox();
 650         omap_init_mcspi();
 651         omap_hdq_init();
 652         omap_init_sti();
 653         omap_init_sha1_md5();
 654
 655         return 0;
 656 }
 657 arch_initcall(omap2_init_devices);