arch/arm/mach-omap2/cm-regbits-33xx.h

   1 /*
   2  * AM33XX Power Management register bits
   3  *
   4  * This file is automatically generated from the AM33XX hardware databases.
   5  * Vaibhav Hiremath <hvaibhav@ti.com>
   6  *
   7  * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19
  20 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
  21 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
  22
  23 /*
  24  * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
  25  * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
  26  */
  27 #define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
  28 #define AM33XX_AUTO_DPLL_MODE_WIDTH                     3
  29 #define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
  30
  31 /* Used by CM_WKUP_CLKSTCTRL */
  32 #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
  33 #define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH               1
  34 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
  35
  36 /* Used by CM_PER_L4LS_CLKSTCTRL */
  37 #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
  38 #define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH                1
  39 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
  40
  41 /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
  42 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
  43 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH         1
  44 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
  45
  46 /* Used by CM_PER_CPSW_CLKSTCTRL */
  47 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
  48 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH       1
  49 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
  50
  51 /* Used by CM_PER_L4HS_CLKSTCTRL */
  52 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
  53 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH       1
  54 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
  55
  56 /* Used by CM_PER_L4HS_CLKSTCTRL */
  57 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
  58 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH        1
  59 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
  60
  61 /* Used by CM_PER_L4HS_CLKSTCTRL */
  62 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
  63 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH         1
  64 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
  65
  66 /* Used by CM_PER_L3_CLKSTCTRL */
  67 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
  68 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH          1
  69 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
  70
  71 /* Used by CM_CEFUSE_CLKSTCTRL */
  72 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
  73 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH     1
  74 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
  75
  76 /* Used by CM_L3_AON_CLKSTCTRL */
  77 #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
  78 #define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH              1
  79 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
  80
  81 /* Used by CM_L3_AON_CLKSTCTRL */
  82 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
  83 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH             1
  84 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
  85
  86 /* Used by CM_PER_L3_CLKSTCTRL */
  87 #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
  88 #define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH              1
  89 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
  90
  91 /* Used by CM_GFX_L3_CLKSTCTRL */
  92 #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
  93 #define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH               1
  94 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
  95
  96 /* Used by CM_GFX_L3_CLKSTCTRL */
  97 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
  98 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH            1
  99 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
 100
 101 /* Used by CM_WKUP_CLKSTCTRL */
 102 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
 103 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH           1
 104 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
 105
 106 /* Used by CM_PER_L4LS_CLKSTCTRL */
 107 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
 108 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH          1
 109 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
 110
 111 /* Used by CM_PER_L4LS_CLKSTCTRL */
 112 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
 113 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH          1
 114 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
 115
 116 /* Used by CM_PER_L4LS_CLKSTCTRL */
 117 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
 118 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH          1
 119 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
 120
 121 /* Used by CM_PER_L4LS_CLKSTCTRL */
 122 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
 123 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH          1
 124 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
 125
 126 /* Used by CM_PER_L4LS_CLKSTCTRL */
 127 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
 128 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH          1
 129 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
 130
 131 /* Used by CM_PER_L4LS_CLKSTCTRL */
 132 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
 133 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH          1
 134 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
 135
 136 /* Used by CM_WKUP_CLKSTCTRL */
 137 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
 138 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH             1
 139 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
 140
 141 /* Used by CM_PER_L4LS_CLKSTCTRL */
 142 #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
 143 #define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH               1
 144 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
 145
 146 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 147 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
 148 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH         1
 149 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
 150
 151 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 152 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
 153 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH         1
 154 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
 155
 156 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 157 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
 158 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH        1
 159 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
 160
 161 /* Used by CM_PER_L3S_CLKSTCTRL */
 162 #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
 163 #define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH               1
 164 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
 165
 166 /* Used by CM_L3_AON_CLKSTCTRL */
 167 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
 168 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH            1
 169 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
 170
 171 /* Used by CM_PER_L3_CLKSTCTRL */
 172 #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
 173 #define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH                1
 174 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
 175
 176 /* Used by CM_PER_L4FW_CLKSTCTRL */
 177 #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
 178 #define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH              1
 179 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
 180
 181 /* Used by CM_PER_L4HS_CLKSTCTRL */
 182 #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
 183 #define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH              1
 184 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
 185
 186 /* Used by CM_PER_L4LS_CLKSTCTRL */
 187 #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
 188 #define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH              1
 189 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
 190
 191 /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
 192 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
 193 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH          1
 194 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
 195
 196 /* Used by CM_CEFUSE_CLKSTCTRL */
 197 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
 198 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH        1
 199 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
 200
 201 /* Used by CM_RTC_CLKSTCTRL */
 202 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
 203 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH            1
 204 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
 205
 206 /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
 207 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
 208 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH       1
 209 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
 210
 211 /* Used by CM_WKUP_CLKSTCTRL */
 212 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
 213 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH           1
 214 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
 215
 216 /* Used by CM_PER_L4LS_CLKSTCTRL */
 217 #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
 218 #define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH              1
 219 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
 220
 221 /* Used by CM_PER_LCDC_CLKSTCTRL */
 222 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
 223 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH       1
 224 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
 225
 226 /* Used by CM_PER_LCDC_CLKSTCTRL */
 227 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
 228 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH       1
 229 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
 230
 231 /* Used by CM_PER_L3_CLKSTCTRL */
 232 #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
 233 #define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH             1
 234 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
 235
 236 /* Used by CM_PER_L3_CLKSTCTRL */
 237 #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
 238 #define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH               1
 239 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
 240
 241 /* Used by CM_MPU_CLKSTCTRL */
 242 #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
 243 #define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH                1
 244 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
 245
 246 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 247 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
 248 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH          1
 249 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
 250
 251 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 252 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
 253 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH          1
 254 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
 255
 256 /* Used by CM_RTC_CLKSTCTRL */
 257 #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
 258 #define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH             1
 259 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
 260
 261 /* Used by CM_PER_L4LS_CLKSTCTRL */
 262 #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
 263 #define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH               1
 264 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
 265
 266 /* Used by CM_WKUP_CLKSTCTRL */
 267 #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
 268 #define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH              1
 269 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
 270
 271 /* Used by CM_WKUP_CLKSTCTRL */
 272 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
 273 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH            1
 274 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
 275
 276 /* Used by CM_WKUP_CLKSTCTRL */
 277 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
 278 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH            1
 279 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
 280
 281 /* Used by CM_PER_L4LS_CLKSTCTRL */
 282 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
 283 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH            1
 284 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
 285
 286 /* Used by CM_PER_L4LS_CLKSTCTRL */
 287 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
 288 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH            1
 289 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
 290
 291 /* Used by CM_PER_L4LS_CLKSTCTRL */
 292 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
 293 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH            1
 294 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
 295
 296 /* Used by CM_PER_L4LS_CLKSTCTRL */
 297 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
 298 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH            1
 299 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
 300
 301 /* Used by CM_PER_L4LS_CLKSTCTRL */
 302 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
 303 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH            1
 304 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
 305
 306 /* Used by CM_PER_L4LS_CLKSTCTRL */
 307 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
 308 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH            1
 309 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
 310
 311 /* Used by CM_WKUP_CLKSTCTRL */
 312 #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
 313 #define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH            1
 314 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
 315
 316 /* Used by CM_PER_L4LS_CLKSTCTRL */
 317 #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
 318 #define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH             1
 319 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
 320
 321 /* Used by CM_WKUP_CLKSTCTRL */
 322 #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
 323 #define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH              1
 324 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
 325
 326 /* Used by CM_WKUP_CLKSTCTRL */
 327 #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
 328 #define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH              1
 329 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
 330
 331 /* Used by CLKSEL_GFX_FCLK */
 332 #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
 333 #define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH                1
 334 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
 335
 336 /* Used by CM_CLKOUT_CTRL */
 337 #define AM33XX_CLKOUT2DIV_SHIFT                         3
 338 #define AM33XX_CLKOUT2DIV_WIDTH                         3
 339 #define AM33XX_CLKOUT2DIV_MASK                          (0x7 << 3)
 340
 341 /* Used by CM_CLKOUT_CTRL */
 342 #define AM33XX_CLKOUT2EN_SHIFT                          7
 343 #define AM33XX_CLKOUT2EN_WIDTH                          1
 344 #define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
 345
 346 /* Used by CM_CLKOUT_CTRL */
 347 #define AM33XX_CLKOUT2SOURCE_SHIFT                      0
 348 #define AM33XX_CLKOUT2SOURCE_WIDTH                      3
 349 #define AM33XX_CLKOUT2SOURCE_MASK                       (0x7 << 0)
 350
 351 /*
 352  * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
 353  * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
 354  * CLKSEL_TIMER7_CLK
 355  */
 356 #define AM33XX_CLKSEL_SHIFT                             0
 357 #define AM33XX_CLKSEL_WIDTH                             1
 358 #define AM33XX_CLKSEL_MASK                              (0x01 << 0)
 359
 360 /*
 361  * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
 362  * CM_CPTS_RFT_CLKSEL
 363  */
 364 #define AM33XX_CLKSEL_0_0_SHIFT                         0
 365 #define AM33XX_CLKSEL_0_0_WIDTH                         1
 366 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
 367
 368 #define AM33XX_CLKSEL_0_1_SHIFT                         0
 369 #define AM33XX_CLKSEL_0_1_WIDTH                         2
 370 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
 371
 372 /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
 373 #define AM33XX_CLKSEL_0_2_SHIFT                         0
 374 #define AM33XX_CLKSEL_0_2_WIDTH                         3
 375 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
 376
 377 /* Used by CLKSEL_GFX_FCLK */
 378 #define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
 379 #define AM33XX_CLKSEL_GFX_FCLK_WIDTH                    1
 380 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
 381
 382 /*
 383  * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
 384  * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
 385  * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
 386  * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
 387  * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
 388  * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
 389  */
 390 #define AM33XX_CLKTRCTRL_SHIFT                          0
 391 #define AM33XX_CLKTRCTRL_WIDTH                          2
 392 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
 393
 394 /*
 395  * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
 396  * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
 397  * CM_SSC_DELTAMSTEP_DPLL_PER
 398  */
 399 #define AM33XX_DELTAMSTEP_SHIFT                         0
 400 #define AM33XX_DELTAMSTEP_WIDTH                         20
 401 #define AM33XX_DELTAMSTEP_MASK                          (0xfffff << 0)
 402
 403 /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
 404 #define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
 405 #define AM33XX_DPLL_BYP_CLKSEL_WIDTH                    1
 406 #define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
 407
 408 /* Used by CM_CLKDCOLDO_DPLL_PER */
 409 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
 410 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH           1
 411 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
 412
 413 /* Used by CM_CLKDCOLDO_DPLL_PER */
 414 #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
 415 #define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH                1
 416 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
 417
 418 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 419 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
 420 #define AM33XX_DPLL_CLKOUT_DIV_WIDTH                    5
 421 #define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
 422
 423 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
 424 #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
 425 #define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH                7
 426 #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x7f << 0)
 427
 428 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 429 #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
 430 #define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH               1
 431 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
 432
 433 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
 434 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
 435 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH        1
 436 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
 437
 438 /*
 439  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
 440  * CM_DIV_M2_DPLL_PER
 441  */
 442 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
 443 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH              1
 444 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
 445
 446 /*
 447  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
 448  * CM_CLKSEL_DPLL_MPU
 449  */
 450 #define AM33XX_DPLL_DIV_SHIFT                           0
 451 #define AM33XX_DPLL_DIV_WIDTH                           7
 452 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
 453
 454 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
 455
 456 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
 457 #define AM33XX_DPLL_DIV_0_7_SHIFT                       0
 458 #define AM33XX_DPLL_DIV_0_7_WIDTH                       8
 459 #define AM33XX_DPLL_DIV_0_7_MASK                        (0xff << 0)
 460
 461 /*
 462  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 463  * CM_CLKMODE_DPLL_MPU
 464  */
 465 #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
 466 #define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH                 1
 467 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
 468
 469 /*
 470  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 471  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 472  */
 473 #define AM33XX_DPLL_EN_SHIFT                            0
 474 #define AM33XX_DPLL_EN_WIDTH                            3
 475 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
 476
 477 /*
 478  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 479  * CM_CLKMODE_DPLL_MPU
 480  */
 481 #define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
 482 #define AM33XX_DPLL_LPMODE_EN_WIDTH                     1
 483 #define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
 484
 485 /*
 486  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
 487  * CM_CLKSEL_DPLL_MPU
 488  */
 489 #define AM33XX_DPLL_MULT_SHIFT                          8
 490 #define AM33XX_DPLL_MULT_WIDTH                          11
 491 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
 492
 493 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
 494 #define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
 495 #define AM33XX_DPLL_MULT_PERIPH_WIDTH                   12
 496 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
 497
 498 /*
 499  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 500  * CM_CLKMODE_DPLL_MPU
 501  */
 502 #define AM33XX_DPLL_REGM4XEN_SHIFT                      11
 503 #define AM33XX_DPLL_REGM4XEN_WIDTH                      1
 504 #define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
 505
 506 /* Used by CM_CLKSEL_DPLL_PERIPH */
 507 #define AM33XX_DPLL_SD_DIV_SHIFT                        24
 508 #define AM33XX_DPLL_SD_DIV_WIDTH                        8
 509 #define AM33XX_DPLL_SD_DIV_MASK                         (0xff << 24)
 510
 511 /*
 512  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 513  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 514  */
 515 #define AM33XX_DPLL_SSC_ACK_SHIFT                       13
 516 #define AM33XX_DPLL_SSC_ACK_WIDTH                       1
 517 #define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
 518
 519 /*
 520  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 521  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 522  */
 523 #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
 524 #define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH                1
 525 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
 526
 527 /*
 528  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 529  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 530  */
 531 #define AM33XX_DPLL_SSC_EN_SHIFT                        12
 532 #define AM33XX_DPLL_SSC_EN_WIDTH                        1
 533 #define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
 534
 535 /* Used by CM_DIV_M4_DPLL_CORE */
 536 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
 537 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH              5
 538 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
 539
 540 /* Used by CM_DIV_M4_DPLL_CORE */
 541 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
 542 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH         1
 543 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
 544
 545 /* Used by CM_DIV_M4_DPLL_CORE */
 546 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
 547 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH        1
 548 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
 549
 550 /* Used by CM_DIV_M4_DPLL_CORE */
 551 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
 552 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH             1
 553 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
 554
 555 /* Used by CM_DIV_M5_DPLL_CORE */
 556 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
 557 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH              5
 558 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
 559
 560 /* Used by CM_DIV_M5_DPLL_CORE */
 561 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
 562 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH         1
 563 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
 564
 565 /* Used by CM_DIV_M5_DPLL_CORE */
 566 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
 567 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH        1
 568 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
 569
 570 /* Used by CM_DIV_M5_DPLL_CORE */
 571 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
 572 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH             1
 573 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
 574
 575 /* Used by CM_DIV_M6_DPLL_CORE */
 576 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
 577 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH              5
 578 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x1f << 0)
 579
 580 /* Used by CM_DIV_M6_DPLL_CORE */
 581 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
 582 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH         1
 583 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
 584
 585 /* Used by CM_DIV_M6_DPLL_CORE */
 586 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
 587 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH        1
 588 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
 589
 590 /* Used by CM_DIV_M6_DPLL_CORE */
 591 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
 592 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH             1
 593 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
 594
 595 /*
 596  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
 597  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
 598  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
 599  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
 600  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
 601  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
 602  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
 603  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
 604  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
 605  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
 606  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
 607  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
 608  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
 609  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
 610  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
 611  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
 612  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
 613  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
 614  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
 615  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
 616  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
 617  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
 618  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
 619  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
 620  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
 621  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
 622  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
 623  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
 624  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
 625  * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
 626  * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
 627  */
 628 #define AM33XX_IDLEST_SHIFT                             16
 629 #define AM33XX_IDLEST_WIDTH                             2
 630 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
 631
 632 /* Used by CM_MAC_CLKSEL */
 633 #define AM33XX_MII_CLK_SEL_SHIFT                        2
 634 #define AM33XX_MII_CLK_SEL_WIDTH                        1
 635 #define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
 636
 637 /*
 638  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
 639  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
 640  * CM_SSC_MODFREQDIV_DPLL_PER
 641  */
 642 #define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
 643 #define AM33XX_MODFREQDIV_EXPONENT_WIDTH                3
 644 #define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x7 << 8)
 645
 646 /*
 647  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
 648  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
 649  * CM_SSC_MODFREQDIV_DPLL_PER
 650  */
 651 #define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
 652 #define AM33XX_MODFREQDIV_MANTISSA_WIDTH                7
 653 #define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x7f << 0)
 654
 655 /*
 656  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
 657  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
 658  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
 659  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
 660  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
 661  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
 662  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
 663  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
 664  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
 665  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
 666  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
 667  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
 668  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
 669  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
 670  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
 671  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
 672  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
 673  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
 674  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
 675  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
 676  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
 677  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
 678  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
 679  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
 680  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
 681  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
 682  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
 683  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
 684  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
 685  * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
 686  * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
 687  * CM_CEFUSE_CEFUSE_CLKCTRL
 688  */
 689 #define AM33XX_MODULEMODE_SHIFT                         0
 690 #define AM33XX_MODULEMODE_WIDTH                         2
 691 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
 692
 693 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 694 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
 695 #define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH                  1
 696 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
 697
 698 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 699 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
 700 #define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH                1
 701 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
 702
 703 /* Used by CM_WKUP_GPIO0_CLKCTRL */
 704 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
 705 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH             1
 706 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
 707
 708 /* Used by CM_PER_GPIO1_CLKCTRL */
 709 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
 710 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH            1
 711 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
 712
 713 /* Used by CM_PER_GPIO2_CLKCTRL */
 714 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
 715 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH            1
 716 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
 717
 718 /* Used by CM_PER_GPIO3_CLKCTRL */
 719 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
 720 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH            1
 721 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
 722
 723 /* Used by CM_PER_GPIO4_CLKCTRL */
 724 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
 725 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH            1
 726 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
 727
 728 /* Used by CM_PER_GPIO5_CLKCTRL */
 729 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
 730 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH            1
 731 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
 732
 733 /* Used by CM_PER_GPIO6_CLKCTRL */
 734 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
 735 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH            1
 736 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
 737
 738 /*
 739  * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
 740  * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
 741  * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
 742  * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
 743  * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
 744  * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
 745  */
 746 #define AM33XX_STBYST_SHIFT                             18
 747 #define AM33XX_STBYST_WIDTH                             1
 748 #define AM33XX_STBYST_MASK                              (1 << 18)
 749
 750 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 751 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
 752 #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH                  3
 753 #define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x7 << 27)
 754
 755 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 756 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
 757 #define AM33XX_STM_PMD_CLKSEL_WIDTH                     2
 758 #define AM33XX_STM_PMD_CLKSEL_MASK                      (0x3 << 22)
 759
 760 /*
 761  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
 762  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
 763  */
 764 #define AM33XX_ST_DPLL_CLK_SHIFT                        0
 765 #define AM33XX_ST_DPLL_CLK_WIDTH                        1
 766 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
 767
 768 /* Used by CM_CLKDCOLDO_DPLL_PER */
 769 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
 770 #define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH                  1
 771 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
 772
 773 /*
 774  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
 775  * CM_DIV_M2_DPLL_PER
 776  */
 777 #define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
 778 #define AM33XX_ST_DPLL_CLKOUT_WIDTH                     1
 779 #define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
 780
 781 /* Used by CM_DIV_M4_DPLL_CORE */
 782 #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
 783 #define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH               1
 784 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
 785
 786 /* Used by CM_DIV_M5_DPLL_CORE */
 787 #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
 788 #define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH               1
 789 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
 790
 791 /* Used by CM_DIV_M6_DPLL_CORE */
 792 #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
 793 #define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH               1
 794 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
 795
 796 /*
 797  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
 798  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
 799  */
 800 #define AM33XX_ST_MN_BYPASS_SHIFT                       8
 801 #define AM33XX_ST_MN_BYPASS_WIDTH                       1
 802 #define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
 803
 804 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 805 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
 806 #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH                  3
 807 #define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x7 << 24)
 808
 809 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 810 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
 811 #define AM33XX_TRC_PMD_CLKSEL_WIDTH                     2
 812 #define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x3 << 20)
 813
 814 /* Used by CONTROL_SEC_CLK_CTRL */
 815 #define AM33XX_TIMER0_CLKSEL_WIDTH                      2
 816 #define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
 817 #endif