arch/arm/mach-omap2/cm-regbits-33xx.h

   1 /*
   2  * AM33XX Power Management register bits
   3  *
   4  * This file is automatically generated from the AM33XX hardware databases.
   5  * Vaibhav Hiremath <hvaibhav@ti.com>
   6  *
   7  * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation version 2.
  12  *
  13  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14  * kind, whether express or implied; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  */
  18
  19
  20 #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
  21 #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
  22
  23 /*
  24  * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
  25  * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
  26  */
  27 #define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
  28 #define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
  29
  30 /* Used by CM_WKUP_CLKSTCTRL */
  31 #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
  32 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
  33
  34 /* Used by CM_PER_L4LS_CLKSTCTRL */
  35 #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
  36 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
  37
  38 /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
  39 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
  40 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
  41
  42 /* Used by CM_PER_CPSW_CLKSTCTRL */
  43 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
  44 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
  45
  46 /* Used by CM_PER_L4HS_CLKSTCTRL */
  47 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
  48 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
  49
  50 /* Used by CM_PER_L4HS_CLKSTCTRL */
  51 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
  52 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
  53
  54 /* Used by CM_PER_L4HS_CLKSTCTRL */
  55 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
  56 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
  57
  58 /* Used by CM_PER_L3_CLKSTCTRL */
  59 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
  60 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
  61
  62 /* Used by CM_CEFUSE_CLKSTCTRL */
  63 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
  64 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
  65
  66 /* Used by CM_L3_AON_CLKSTCTRL */
  67 #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
  68 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
  69
  70 /* Used by CM_L3_AON_CLKSTCTRL */
  71 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
  72 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
  73
  74 /* Used by CM_PER_L3_CLKSTCTRL */
  75 #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
  76 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
  77
  78 /* Used by CM_GFX_L3_CLKSTCTRL */
  79 #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
  80 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
  81
  82 /* Used by CM_GFX_L3_CLKSTCTRL */
  83 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
  84 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
  85
  86 /* Used by CM_WKUP_CLKSTCTRL */
  87 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
  88 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
  89
  90 /* Used by CM_PER_L4LS_CLKSTCTRL */
  91 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
  92 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
  93
  94 /* Used by CM_PER_L4LS_CLKSTCTRL */
  95 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
  96 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
  97
  98 /* Used by CM_PER_L4LS_CLKSTCTRL */
  99 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
 100 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
 101
 102 /* Used by CM_PER_L4LS_CLKSTCTRL */
 103 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
 104 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
 105
 106 /* Used by CM_PER_L4LS_CLKSTCTRL */
 107 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
 108 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
 109
 110 /* Used by CM_PER_L4LS_CLKSTCTRL */
 111 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
 112 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
 113
 114 /* Used by CM_WKUP_CLKSTCTRL */
 115 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
 116 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
 117
 118 /* Used by CM_PER_L4LS_CLKSTCTRL */
 119 #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
 120 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
 121
 122 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 123 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
 124 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
 125
 126 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 127 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
 128 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
 129
 130 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 131 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
 132 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
 133
 134 /* Used by CM_PER_L3S_CLKSTCTRL */
 135 #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
 136 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
 137
 138 /* Used by CM_L3_AON_CLKSTCTRL */
 139 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
 140 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
 141
 142 /* Used by CM_PER_L3_CLKSTCTRL */
 143 #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
 144 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
 145
 146 /* Used by CM_PER_L4FW_CLKSTCTRL */
 147 #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
 148 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
 149
 150 /* Used by CM_PER_L4HS_CLKSTCTRL */
 151 #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
 152 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
 153
 154 /* Used by CM_PER_L4LS_CLKSTCTRL */
 155 #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
 156 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
 157
 158 /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
 159 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
 160 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
 161
 162 /* Used by CM_CEFUSE_CLKSTCTRL */
 163 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
 164 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
 165
 166 /* Used by CM_RTC_CLKSTCTRL */
 167 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
 168 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
 169
 170 /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
 171 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
 172 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
 173
 174 /* Used by CM_WKUP_CLKSTCTRL */
 175 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
 176 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
 177
 178 /* Used by CM_PER_L4LS_CLKSTCTRL */
 179 #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
 180 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
 181
 182 /* Used by CM_PER_LCDC_CLKSTCTRL */
 183 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
 184 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
 185
 186 /* Used by CM_PER_LCDC_CLKSTCTRL */
 187 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
 188 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
 189
 190 /* Used by CM_PER_L3_CLKSTCTRL */
 191 #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
 192 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
 193
 194 /* Used by CM_PER_L3_CLKSTCTRL */
 195 #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
 196 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
 197
 198 /* Used by CM_MPU_CLKSTCTRL */
 199 #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
 200 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
 201
 202 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 203 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
 204 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
 205
 206 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 207 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
 208 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
 209
 210 /* Used by CM_RTC_CLKSTCTRL */
 211 #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
 212 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
 213
 214 /* Used by CM_PER_L4LS_CLKSTCTRL */
 215 #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
 216 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
 217
 218 /* Used by CM_WKUP_CLKSTCTRL */
 219 #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
 220 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
 221
 222 /* Used by CM_WKUP_CLKSTCTRL */
 223 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
 224 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
 225
 226 /* Used by CM_WKUP_CLKSTCTRL */
 227 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
 228 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
 229
 230 /* Used by CM_PER_L4LS_CLKSTCTRL */
 231 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
 232 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
 233
 234 /* Used by CM_PER_L4LS_CLKSTCTRL */
 235 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
 236 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
 237
 238 /* Used by CM_PER_L4LS_CLKSTCTRL */
 239 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
 240 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
 241
 242 /* Used by CM_PER_L4LS_CLKSTCTRL */
 243 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
 244 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
 245
 246 /* Used by CM_PER_L4LS_CLKSTCTRL */
 247 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
 248 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
 249
 250 /* Used by CM_PER_L4LS_CLKSTCTRL */
 251 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
 252 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
 253
 254 /* Used by CM_WKUP_CLKSTCTRL */
 255 #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
 256 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
 257
 258 /* Used by CM_PER_L4LS_CLKSTCTRL */
 259 #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
 260 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
 261
 262 /* Used by CM_WKUP_CLKSTCTRL */
 263 #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
 264 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
 265
 266 /* Used by CM_WKUP_CLKSTCTRL */
 267 #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
 268 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
 269
 270 /* Used by CLKSEL_GFX_FCLK */
 271 #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
 272 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
 273
 274 /* Used by CM_CLKOUT_CTRL */
 275 #define AM33XX_CLKOUT2DIV_SHIFT                         3
 276 #define AM33XX_CLKOUT2DIV_MASK                          (0x05 << 3)
 277
 278 /* Used by CM_CLKOUT_CTRL */
 279 #define AM33XX_CLKOUT2EN_SHIFT                          7
 280 #define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
 281
 282 /* Used by CM_CLKOUT_CTRL */
 283 #define AM33XX_CLKOUT2SOURCE_SHIFT                      0
 284 #define AM33XX_CLKOUT2SOURCE_MASK                       (0x02 << 0)
 285
 286 /*
 287  * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
 288  * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
 289  * CLKSEL_TIMER7_CLK
 290  */
 291 #define AM33XX_CLKSEL_SHIFT                             0
 292 #define AM33XX_CLKSEL_MASK                              (0x01 << 0)
 293
 294 /*
 295  * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
 296  * CM_CPTS_RFT_CLKSEL
 297  */
 298 #define AM33XX_CLKSEL_0_0_SHIFT                         0
 299 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
 300
 301 #define AM33XX_CLKSEL_0_1_SHIFT                         0
 302 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
 303
 304 /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
 305 #define AM33XX_CLKSEL_0_2_SHIFT                         0
 306 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
 307
 308 /* Used by CLKSEL_GFX_FCLK */
 309 #define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
 310 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
 311
 312 /*
 313  * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
 314  * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
 315  * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
 316  * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
 317  * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
 318  * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
 319  */
 320 #define AM33XX_CLKTRCTRL_SHIFT                          0
 321 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
 322
 323 /*
 324  * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
 325  * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
 326  * CM_SSC_DELTAMSTEP_DPLL_PER
 327  */
 328 #define AM33XX_DELTAMSTEP_SHIFT                         0
 329 #define AM33XX_DELTAMSTEP_MASK                          (0x19 << 0)
 330
 331 /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
 332 #define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
 333 #define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
 334
 335 /* Used by CM_CLKDCOLDO_DPLL_PER */
 336 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
 337 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
 338
 339 /* Used by CM_CLKDCOLDO_DPLL_PER */
 340 #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
 341 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
 342
 343 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 344 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
 345 #define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
 346
 347 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
 348 #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
 349 #define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x06 << 0)
 350
 351 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 352 #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
 353 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
 354
 355 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
 356 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
 357 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
 358
 359 /*
 360  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
 361  * CM_DIV_M2_DPLL_PER
 362  */
 363 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
 364 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
 365
 366 /*
 367  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
 368  * CM_CLKSEL_DPLL_MPU
 369  */
 370 #define AM33XX_DPLL_DIV_SHIFT                           0
 371 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
 372
 373 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
 374
 375 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
 376 #define AM33XX_DPLL_DIV_0_7_SHIFT                       0
 377 #define AM33XX_DPLL_DIV_0_7_MASK                        (0x07 << 0)
 378
 379 /*
 380  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 381  * CM_CLKMODE_DPLL_MPU
 382  */
 383 #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
 384 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
 385
 386 /*
 387  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 388  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 389  */
 390 #define AM33XX_DPLL_EN_SHIFT                            0
 391 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
 392
 393 /*
 394  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 395  * CM_CLKMODE_DPLL_MPU
 396  */
 397 #define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
 398 #define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
 399
 400 /*
 401  * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
 402  * CM_CLKSEL_DPLL_MPU
 403  */
 404 #define AM33XX_DPLL_MULT_SHIFT                          8
 405 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
 406
 407 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
 408 #define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
 409 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
 410
 411 /*
 412  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 413  * CM_CLKMODE_DPLL_MPU
 414  */
 415 #define AM33XX_DPLL_REGM4XEN_SHIFT                      11
 416 #define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
 417
 418 /* Used by CM_CLKSEL_DPLL_PERIPH */
 419 #define AM33XX_DPLL_SD_DIV_SHIFT                        24
 420 #define AM33XX_DPLL_SD_DIV_MASK                         (24, 31)
 421
 422 /*
 423  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 424  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 425  */
 426 #define AM33XX_DPLL_SSC_ACK_SHIFT                       13
 427 #define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
 428
 429 /*
 430  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 431  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 432  */
 433 #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
 434 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
 435
 436 /*
 437  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
 438  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
 439  */
 440 #define AM33XX_DPLL_SSC_EN_SHIFT                        12
 441 #define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
 442
 443 /* Used by CM_DIV_M4_DPLL_CORE */
 444 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
 445 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
 446
 447 /* Used by CM_DIV_M4_DPLL_CORE */
 448 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
 449 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
 450
 451 /* Used by CM_DIV_M4_DPLL_CORE */
 452 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
 453 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
 454
 455 /* Used by CM_DIV_M4_DPLL_CORE */
 456 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
 457 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
 458
 459 /* Used by CM_DIV_M5_DPLL_CORE */
 460 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
 461 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
 462
 463 /* Used by CM_DIV_M5_DPLL_CORE */
 464 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
 465 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
 466
 467 /* Used by CM_DIV_M5_DPLL_CORE */
 468 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
 469 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
 470
 471 /* Used by CM_DIV_M5_DPLL_CORE */
 472 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
 473 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
 474
 475 /* Used by CM_DIV_M6_DPLL_CORE */
 476 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
 477 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x04 << 0)
 478
 479 /* Used by CM_DIV_M6_DPLL_CORE */
 480 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
 481 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
 482
 483 /* Used by CM_DIV_M6_DPLL_CORE */
 484 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
 485 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
 486
 487 /* Used by CM_DIV_M6_DPLL_CORE */
 488 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
 489 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
 490
 491 /*
 492  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
 493  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
 494  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
 495  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
 496  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
 497  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
 498  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
 499  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
 500  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
 501  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
 502  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
 503  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
 504  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
 505  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
 506  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
 507  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
 508  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
 509  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
 510  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
 511  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
 512  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
 513  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
 514  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
 515  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
 516  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
 517  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
 518  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
 519  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
 520  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
 521  * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
 522  * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
 523  */
 524 #define AM33XX_IDLEST_SHIFT                             16
 525 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
 526 #define AM33XX_IDLEST_VAL                               0x3
 527
 528 /* Used by CM_MAC_CLKSEL */
 529 #define AM33XX_MII_CLK_SEL_SHIFT                        2
 530 #define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
 531
 532 /*
 533  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
 534  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
 535  * CM_SSC_MODFREQDIV_DPLL_PER
 536  */
 537 #define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
 538 #define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x10 << 8)
 539
 540 /*
 541  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
 542  * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
 543  * CM_SSC_MODFREQDIV_DPLL_PER
 544  */
 545 #define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
 546 #define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x06 << 0)
 547
 548 /*
 549  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
 550  * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
 551  * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
 552  * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
 553  * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
 554  * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
 555  * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
 556  * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
 557  * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
 558  * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
 559  * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
 560  * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
 561  * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
 562  * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
 563  * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
 564  * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
 565  * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
 566  * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
 567  * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
 568  * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
 569  * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
 570  * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
 571  * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
 572  * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
 573  * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
 574  * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
 575  * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
 576  * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
 577  * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
 578  * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
 579  * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
 580  * CM_CEFUSE_CEFUSE_CLKCTRL
 581  */
 582 #define AM33XX_MODULEMODE_SHIFT                         0
 583 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
 584
 585 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 586 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
 587 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
 588
 589 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 590 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
 591 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
 592
 593 /* Used by CM_WKUP_GPIO0_CLKCTRL */
 594 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
 595 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
 596
 597 /* Used by CM_PER_GPIO1_CLKCTRL */
 598 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
 599 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
 600
 601 /* Used by CM_PER_GPIO2_CLKCTRL */
 602 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
 603 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
 604
 605 /* Used by CM_PER_GPIO3_CLKCTRL */
 606 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
 607 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
 608
 609 /* Used by CM_PER_GPIO4_CLKCTRL */
 610 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
 611 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
 612
 613 /* Used by CM_PER_GPIO5_CLKCTRL */
 614 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
 615 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
 616
 617 /* Used by CM_PER_GPIO6_CLKCTRL */
 618 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
 619 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
 620
 621 /*
 622  * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
 623  * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
 624  * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
 625  * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
 626  * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
 627  * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
 628  */
 629 #define AM33XX_STBYST_SHIFT                             18
 630 #define AM33XX_STBYST_MASK                              (1 << 18)
 631
 632 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 633 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
 634 #define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x29 << 27)
 635
 636 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 637 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
 638 #define AM33XX_STM_PMD_CLKSEL_MASK                      (0x23 << 22)
 639
 640 /*
 641  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
 642  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
 643  */
 644 #define AM33XX_ST_DPLL_CLK_SHIFT                        0
 645 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
 646
 647 /* Used by CM_CLKDCOLDO_DPLL_PER */
 648 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
 649 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
 650
 651 /*
 652  * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
 653  * CM_DIV_M2_DPLL_PER
 654  */
 655 #define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
 656 #define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
 657
 658 /* Used by CM_DIV_M4_DPLL_CORE */
 659 #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
 660 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
 661
 662 /* Used by CM_DIV_M5_DPLL_CORE */
 663 #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
 664 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
 665
 666 /* Used by CM_DIV_M6_DPLL_CORE */
 667 #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
 668 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
 669
 670 /*
 671  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
 672  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
 673  */
 674 #define AM33XX_ST_MN_BYPASS_SHIFT                       8
 675 #define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
 676
 677 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 678 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
 679 #define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x26 << 24)
 680
 681 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 682 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
 683 #define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x21 << 20)
 684
 685 /* Used by CONTROL_SEC_CLK_CTRL */
 686 #define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
 687 #endif