2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/delay.h>
16 #include <linux/types.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
19 #include <linux/irq.h>
20 #include <linux/gpio.h>
21 #include <linux/smsc911x.h>
22 #include <linux/platform_device.h>
23 #include <linux/mfd/mc13783.h>
24 #include <linux/spi/spi.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/fsl_devices.h>
27 #include <linux/input/matrix_keypad.h>
29 #include <mach/hardware.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <asm/mach/time.h>
33 #include <asm/memory.h>
34 #include <asm/mach/map.h>
35 #include <mach/common.h>
36 #include <mach/imx-uart.h>
37 #include <mach/iomux-mx3.h>
39 #include "devices-imx31.h"
42 /* Definitions for components on the Debug board */
44 /* Base address of CPLD controller on the Debug board */
45 #define DEBUG_BASE_ADDRESS CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
47 /* LAN9217 ethernet base address */
48 #define LAN9217_BASE_ADDR MX3x_CS5_BASE_ADDR
50 /* CPLD config and interrupt base address */
51 #define CPLD_ADDR (DEBUG_BASE_ADDRESS + 0x20000)
53 /* status, interrupt */
54 #define CPLD_INT_STATUS_REG (CPLD_ADDR + 0x10)
55 #define CPLD_INT_MASK_REG (CPLD_ADDR + 0x38)
56 #define CPLD_INT_RESET_REG (CPLD_ADDR + 0x20)
57 /* magic word for debug CPLD */
58 #define CPLD_MAGIC_NUMBER1_REG (CPLD_ADDR + 0x40)
59 #define CPLD_MAGIC_NUMBER2_REG (CPLD_ADDR + 0x48)
60 /* CPLD code version */
61 #define CPLD_CODE_VER_REG (CPLD_ADDR + 0x50)
62 /* magic word for debug CPLD */
63 #define CPLD_MAGIC_NUMBER3_REG (CPLD_ADDR + 0x58)
65 /* CPLD IRQ line for external uart, external ethernet etc */
66 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
68 #define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
69 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
71 #define EXPIO_INT_ENET (MXC_EXP_IO_BASE + 0)
73 #define MXC_MAX_EXP_IO_LINES 16
76 * This file contains the board-specific initialization routines.
79 static int mx31_3ds_pins[] = {
85 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
87 MX31_PIN_CSPI2_SCLK__SCLK,
88 MX31_PIN_CSPI2_MOSI__MOSI,
89 MX31_PIN_CSPI2_MISO__MISO,
90 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
91 MX31_PIN_CSPI2_SS0__SS0,
92 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
94 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
96 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
98 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
99 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
100 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
101 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
102 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
103 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
104 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
105 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
106 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
107 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
108 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
109 MX31_PIN_USBOTG_STP__USBOTG_STP,
111 MX31_PIN_KEY_ROW0_KEY_ROW0,
112 MX31_PIN_KEY_ROW1_KEY_ROW1,
113 MX31_PIN_KEY_ROW2_KEY_ROW2,
114 MX31_PIN_KEY_COL0_KEY_COL0,
115 MX31_PIN_KEY_COL1_KEY_COL1,
116 MX31_PIN_KEY_COL2_KEY_COL2,
117 MX31_PIN_KEY_COL3_KEY_COL3,
124 static const uint32_t mx31_3ds_keymap[] = {
127 KEY(1, 0, KEY_RIGHT),
129 KEY(1, 2, KEY_ENTER),
136 static struct matrix_keymap_data mx31_3ds_keymap_data = {
137 .keymap = mx31_3ds_keymap,
138 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
142 static struct regulator_init_data pwgtx_init = {
149 static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
151 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
152 .init_data = &pwgtx_init,
154 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
155 .init_data = &pwgtx_init,
160 static struct mc13783_platform_data mc13783_pdata __initdata = {
161 .regulators = mx31_3ds_regulators,
162 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
163 .flags = MC13783_USE_REGULATOR,
167 static int spi1_internal_chipselect[] = {
172 static const struct spi_imx_master spi1_pdata __initconst = {
173 .chipselect = spi1_internal_chipselect,
174 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
177 static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
179 .modalias = "mc13783",
180 .max_speed_hz = 1000000,
182 .chip_select = 1, /* SS2 */
183 .platform_data = &mc13783_pdata,
184 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
192 static const struct mxc_nand_platform_data
193 mx31_3ds_nand_board_info __initconst = {
196 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
205 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
206 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
208 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
210 static void mx31_3ds_usbotg_init(void)
212 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
216 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
217 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
218 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
219 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
220 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
221 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
222 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
223 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
225 gpio_request(USBOTG_RST_B, "otgusb-reset");
226 gpio_direction_output(USBOTG_RST_B, 0);
228 gpio_set_value(USBOTG_RST_B, 1);
231 static struct fsl_usb2_platform_data usbotg_pdata = {
232 .operating_mode = FSL_USB2_DR_DEVICE,
233 .phy_mode = FSL_USB2_PHY_ULPI,
236 static struct imxuart_platform_data uart_pdata = {
237 .flags = IMXUART_HAVE_RTSCTS,
241 * Support for the SMSC9217 on the Debug board.
244 static struct smsc911x_platform_config smsc911x_config = {
245 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
246 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
247 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
248 .phy_interface = PHY_INTERFACE_MODE_MII,
251 static struct resource smsc911x_resources[] = {
253 .start = LAN9217_BASE_ADDR,
254 .end = LAN9217_BASE_ADDR + 0xff,
255 .flags = IORESOURCE_MEM,
257 .start = EXPIO_INT_ENET,
258 .end = EXPIO_INT_ENET,
259 .flags = IORESOURCE_IRQ,
263 static struct platform_device smsc911x_device = {
266 .num_resources = ARRAY_SIZE(smsc911x_resources),
267 .resource = smsc911x_resources,
269 .platform_data = &smsc911x_config,
274 * Routines for the CPLD on the debug board. It contains a CPLD handling
275 * LEDs, switches, interrupts for Ethernet.
278 static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
284 imr_val = __raw_readw(CPLD_INT_MASK_REG);
285 int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
287 expio_irq = MXC_EXP_IO_BASE;
288 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
289 if ((int_valid & 1) == 0)
291 generic_handle_irq(expio_irq);
296 * Disable an expio pin's interrupt by setting the bit in the imr.
297 * @param irq an expio virtual irq number
299 static void expio_mask_irq(uint32_t irq)
302 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
304 /* mask the interrupt */
305 reg = __raw_readw(CPLD_INT_MASK_REG);
307 __raw_writew(reg, CPLD_INT_MASK_REG);
311 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
312 * @param irq an expanded io virtual irq number
314 static void expio_ack_irq(uint32_t irq)
316 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
318 /* clear the interrupt status */
319 __raw_writew(1 << expio, CPLD_INT_RESET_REG);
320 __raw_writew(0, CPLD_INT_RESET_REG);
321 /* mask the interrupt */
326 * Enable a expio pin's interrupt by clearing the bit in the imr.
327 * @param irq a expio virtual irq number
329 static void expio_unmask_irq(uint32_t irq)
332 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
334 /* unmask the interrupt */
335 reg = __raw_readw(CPLD_INT_MASK_REG);
336 reg &= ~(1 << expio);
337 __raw_writew(reg, CPLD_INT_MASK_REG);
340 static struct irq_chip expio_irq_chip = {
341 .ack = expio_ack_irq,
342 .mask = expio_mask_irq,
343 .unmask = expio_unmask_irq,
346 static int __init mx31_3ds_init_expio(void)
351 /* Check if there's a debug board connected */
352 if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
353 (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
354 (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
355 /* No Debug board found */
359 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
360 __raw_readw(CPLD_CODE_VER_REG));
363 * Configure INT line as GPIO input
365 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
367 pr_warning("could not get LAN irq gpio\n");
369 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
371 /* Disable the interrupts and clear the status */
372 __raw_writew(0, CPLD_INT_MASK_REG);
373 __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
374 __raw_writew(0, CPLD_INT_RESET_REG);
375 __raw_writew(0x1F, CPLD_INT_MASK_REG);
376 for (i = MXC_EXP_IO_BASE;
377 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
379 set_irq_chip(i, &expio_irq_chip);
380 set_irq_handler(i, handle_level_irq);
381 set_irq_flags(i, IRQF_VALID);
383 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
384 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
390 * This structure defines the MX31 memory map.
392 static struct map_desc mx31_3ds_io_desc[] __initdata = {
394 .virtual = MX31_CS5_BASE_ADDR_VIRT,
395 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
396 .length = MX31_CS5_SIZE,
402 * Set up static virtual mappings.
404 static void __init mx31_3ds_map_io(void)
407 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
411 * Board specific initialization.
413 static void __init mxc_board_init(void)
415 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
418 mxc_register_device(&mxc_uart_device0, &uart_pdata);
419 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
421 imx31_add_spi_imx0(&spi1_pdata);
422 spi_register_board_info(mx31_3ds_spi_devs,
423 ARRAY_SIZE(mx31_3ds_spi_devs));
425 mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
427 mx31_3ds_usbotg_init();
428 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
430 if (!mx31_3ds_init_expio())
431 platform_device_register(&smsc911x_device);
434 static void __init mx31_3ds_timer_init(void)
436 mx31_clocks_init(26000000);
439 static struct sys_timer mx31_3ds_timer = {
440 .init = mx31_3ds_timer_init,
444 * The following uses standard kernel macros defined in arch.h in order to
445 * initialize __mach_desc_MX31_3DS data structure.
447 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
448 /* Maintainer: Freescale Semiconductor, Inc. */
449 .phys_io = MX31_AIPS1_BASE_ADDR,
450 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
451 .boot_params = MX3x_PHYS_OFFSET + 0x100,
452 .map_io = mx31_3ds_map_io,
453 .init_irq = mx31_init_irq,
454 .init_machine = mxc_board_init,
455 .timer = &mx31_3ds_timer,