arch/arm/mach-exynos/exynos.c

   1 /*
   2  * SAMSUNG EXYNOS Flattened Device Tree enabled machine
   3  *
   4  * Copyright (c) 2010-2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/serial_s3c.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_domain.h>
  22 #include <linux/irqchip.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/hardware/cache-l2x0.h>
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/memory.h>
  29
  30 #include "common.h"
  31 #include "mfc.h"
  32 #include "regs-pmu.h"
  33 #include "regs-sys.h"
  34
  35 void __iomem *pmu_base_addr;
  36
  37 static struct map_desc exynos4_iodesc[] __initdata = {
  38         {
  39                 .virtual        = (unsigned long)S3C_VA_SYS,
  40                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSCON),
  41                 .length         = SZ_64K,
  42                 .type           = MT_DEVICE,
  43         }, {
  44                 .virtual        = (unsigned long)S5P_VA_SROMC,
  45                 .pfn            = __phys_to_pfn(EXYNOS4_PA_SROMC),
  46                 .length         = SZ_4K,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = (unsigned long)S5P_VA_CMU,
  50                 .pfn            = __phys_to_pfn(EXYNOS4_PA_CMU),
  51                 .length         = SZ_128K,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = (unsigned long)S5P_VA_COREPERI_BASE,
  55                 .pfn            = __phys_to_pfn(EXYNOS4_PA_COREPERI),
  56                 .length         = SZ_8K,
  57                 .type           = MT_DEVICE,
  58         }, {
  59                 .virtual        = (unsigned long)S5P_VA_DMC0,
  60                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC0),
  61                 .length         = SZ_64K,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = (unsigned long)S5P_VA_DMC1,
  65                 .pfn            = __phys_to_pfn(EXYNOS4_PA_DMC1),
  66                 .length         = SZ_64K,
  67                 .type           = MT_DEVICE,
  68         },
  69 };
  70
  71 static struct map_desc exynos5_iodesc[] __initdata = {
  72         {
  73                 .virtual        = (unsigned long)S3C_VA_SYS,
  74                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSCON),
  75                 .length         = SZ_64K,
  76                 .type           = MT_DEVICE,
  77         }, {
  78                 .virtual        = (unsigned long)S5P_VA_SROMC,
  79                 .pfn            = __phys_to_pfn(EXYNOS5_PA_SROMC),
  80                 .length         = SZ_4K,
  81                 .type           = MT_DEVICE,
  82         }, {
  83                 .virtual        = (unsigned long)S5P_VA_CMU,
  84                 .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
  85                 .length         = 144 * SZ_1K,
  86                 .type           = MT_DEVICE,
  87         },
  88 };
  89
  90 static struct platform_device exynos_cpuidle = {
  91         .name              = "exynos_cpuidle",
  92 #ifdef CONFIG_ARM_EXYNOS_CPUIDLE
  93         .dev.platform_data = exynos_enter_aftr,
  94 #endif
  95         .id                = -1,
  96 };
  97
  98 void __iomem *sysram_base_addr;
  99 void __iomem *sysram_ns_base_addr;
 100
 101 void __init exynos_sysram_init(void)
 102 {
 103         struct device_node *node;
 104
 105         for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
 106                 if (!of_device_is_available(node))
 107                         continue;
 108                 sysram_base_addr = of_iomap(node, 0);
 109                 break;
 110         }
 111
 112         for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
 113                 if (!of_device_is_available(node))
 114                         continue;
 115                 sysram_ns_base_addr = of_iomap(node, 0);
 116                 break;
 117         }
 118 }
 119
 120 static void __init exynos_init_late(void)
 121 {
 122         if (of_machine_is_compatible("samsung,exynos5440"))
 123                 /* to be supported later */
 124                 return;
 125
 126         exynos_pm_init();
 127 }
 128
 129 static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 130                                         int depth, void *data)
 131 {
 132         struct map_desc iodesc;
 133         const __be32 *reg;
 134         int len;
 135
 136         if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
 137                 !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
 138                 return 0;
 139
 140         reg = of_get_flat_dt_prop(node, "reg", &len);
 141         if (reg == NULL || len != (sizeof(unsigned long) * 2))
 142                 return 0;
 143
 144         iodesc.pfn = __phys_to_pfn(be32_to_cpu(reg[0]));
 145         iodesc.length = be32_to_cpu(reg[1]) - 1;
 146         iodesc.virtual = (unsigned long)S5P_VA_CHIPID;
 147         iodesc.type = MT_DEVICE;
 148         iotable_init(&iodesc, 1);
 149         return 1;
 150 }
 151
 152 /*
 153  * exynos_map_io
 154  *
 155  * register the standard cpu IO areas
 156  */
 157 static void __init exynos_map_io(void)
 158 {
 159         if (soc_is_exynos4())
 160                 iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
 161
 162         if (soc_is_exynos5())
 163                 iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
 164 }
 165
 166 static void __init exynos_init_io(void)
 167 {
 168         debug_ll_io_init();
 169
 170         of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
 171
 172         /* detect cpu id and rev. */
 173         s5p_init_cpu(S5P_VA_CHIPID);
 174
 175         exynos_map_io();
 176 }
 177
 178 static const struct of_device_id exynos_dt_pmu_match[] = {
 179         { .compatible = "samsung,exynos3250-pmu" },
 180         { .compatible = "samsung,exynos4210-pmu" },
 181         { .compatible = "samsung,exynos4212-pmu" },
 182         { .compatible = "samsung,exynos4412-pmu" },
 183         { .compatible = "samsung,exynos4415-pmu" },
 184         { .compatible = "samsung,exynos5250-pmu" },
 185         { .compatible = "samsung,exynos5260-pmu" },
 186         { .compatible = "samsung,exynos5410-pmu" },
 187         { .compatible = "samsung,exynos5420-pmu" },
 188         { /*sentinel*/ },
 189 };
 190
 191 static void exynos_map_pmu(void)
 192 {
 193         struct device_node *np;
 194
 195         np = of_find_matching_node(NULL, exynos_dt_pmu_match);
 196         if (np)
 197                 pmu_base_addr = of_iomap(np, 0);
 198
 199         if (!pmu_base_addr)
 200                 panic("failed to find exynos pmu register\n");
 201 }
 202
 203 static void __init exynos_init_irq(void)
 204 {
 205         irqchip_init();
 206         /*
 207          * Since platsmp.c needs pmu base address by the time
 208          * DT is not unflatten so we can't use DT APIs before
 209          * init_irq
 210          */
 211         exynos_map_pmu();
 212 }
 213
 214 static void __init exynos_dt_machine_init(void)
 215 {
 216         struct device_node *i2c_np;
 217         const char *i2c_compat = "samsung,s3c2440-i2c";
 218         unsigned int tmp;
 219         int id;
 220
 221         /*
 222          * Exynos5's legacy i2c controller and new high speed i2c
 223          * controller have muxed interrupt sources. By default the
 224          * interrupts for 4-channel HS-I2C controller are enabled.
 225          * If node for first four channels of legacy i2c controller
 226          * are available then re-configure the interrupts via the
 227          * system register.
 228          */
 229         if (soc_is_exynos5()) {
 230                 for_each_compatible_node(i2c_np, NULL, i2c_compat) {
 231                         if (of_device_is_available(i2c_np)) {
 232                                 id = of_alias_get_id(i2c_np, "i2c");
 233                                 if (id < 4) {
 234                                         tmp = readl(EXYNOS5_SYS_I2C_CFG);
 235                                         writel(tmp & ~(0x1 << id),
 236                                                         EXYNOS5_SYS_I2C_CFG);
 237                                 }
 238                         }
 239                 }
 240         }
 241
 242         /*
 243          * This is called from smp_prepare_cpus if we've built for SMP, but
 244          * we still need to set it up for PM and firmware ops if not.
 245          */
 246         if (!IS_ENABLED(CONFIG_SMP))
 247                 exynos_sysram_init();
 248
 249         if (of_machine_is_compatible("samsung,exynos4210") ||
 250             of_machine_is_compatible("samsung,exynos4212") ||
 251             (of_machine_is_compatible("samsung,exynos4412") &&
 252              of_machine_is_compatible("samsung,trats2")) ||
 253             of_machine_is_compatible("samsung,exynos5250"))
 254                 platform_device_register(&exynos_cpuidle);
 255
 256         platform_device_register_simple("exynos-cpufreq", -1, NULL, 0);
 257
 258         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 259 }
 260
 261 static char const *exynos_dt_compat[] __initconst = {
 262         "samsung,exynos3",
 263         "samsung,exynos3250",
 264         "samsung,exynos4",
 265         "samsung,exynos4210",
 266         "samsung,exynos4212",
 267         "samsung,exynos4412",
 268         "samsung,exynos4415",
 269         "samsung,exynos5",
 270         "samsung,exynos5250",
 271         "samsung,exynos5260",
 272         "samsung,exynos5420",
 273         "samsung,exynos5440",
 274         NULL
 275 };
 276
 277 static void __init exynos_reserve(void)
 278 {
 279 #ifdef CONFIG_S5P_DEV_MFC
 280         int i;
 281         char *mfc_mem[] = {
 282                 "samsung,mfc-v5",
 283                 "samsung,mfc-v6",
 284                 "samsung,mfc-v7",
 285         };
 286
 287         for (i = 0; i < ARRAY_SIZE(mfc_mem); i++)
 288                 if (of_scan_flat_dt(s5p_fdt_alloc_mfc_mem, mfc_mem[i]))
 289                         break;
 290 #endif
 291 }
 292
 293 static void __init exynos_dt_fixup(void)
 294 {
 295         /*
 296          * Some versions of uboot pass garbage entries in the memory node,
 297          * use the old CONFIG_ARM_NR_BANKS
 298          */
 299         of_fdt_limit_memory(8);
 300 }
 301
 302 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
 303         /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
 304         /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
 305         .l2c_aux_val    = 0x3c400001,
 306         .l2c_aux_mask   = 0xc20fffff,
 307         .smp            = smp_ops(exynos_smp_ops),
 308         .map_io         = exynos_init_io,
 309         .init_early     = exynos_firmware_init,
 310         .init_irq       = exynos_init_irq,
 311         .init_machine   = exynos_dt_machine_init,
 312         .init_late      = exynos_init_late,
 313         .dt_compat      = exynos_dt_compat,
 314         .reserve        = exynos_reserve,
 315         .dt_fixup       = exynos_dt_fixup,
 316 MACHINE_END