arch/arm/mach-exynos/dma.c

   1 /* linux/arch/arm/mach-exynos4/dma.c
   2  *
   3  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   7  *      Jaswinder Singh <jassi.brar@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/amba/pl330.h>
  27 #include <linux/of.h>
  28
  29 #include <asm/irq.h>
  30 #include <plat/devs.h>
  31 #include <plat/irqs.h>
  32 #include <plat/cpu.h>
  33
  34 #include <mach/map.h>
  35 #include <mach/irqs.h>
  36 #include <mach/dma.h>
  37
  38 static u64 dma_dmamask = DMA_BIT_MASK(32);
  39
  40 static u8 exynos4210_pdma0_peri[] = {
  41         DMACH_PCM0_RX,
  42         DMACH_PCM0_TX,
  43         DMACH_PCM2_RX,
  44         DMACH_PCM2_TX,
  45         DMACH_MSM_REQ0,
  46         DMACH_MSM_REQ2,
  47         DMACH_SPI0_RX,
  48         DMACH_SPI0_TX,
  49         DMACH_SPI2_RX,
  50         DMACH_SPI2_TX,
  51         DMACH_I2S0S_TX,
  52         DMACH_I2S0_RX,
  53         DMACH_I2S0_TX,
  54         DMACH_I2S2_RX,
  55         DMACH_I2S2_TX,
  56         DMACH_UART0_RX,
  57         DMACH_UART0_TX,
  58         DMACH_UART2_RX,
  59         DMACH_UART2_TX,
  60         DMACH_UART4_RX,
  61         DMACH_UART4_TX,
  62         DMACH_SLIMBUS0_RX,
  63         DMACH_SLIMBUS0_TX,
  64         DMACH_SLIMBUS2_RX,
  65         DMACH_SLIMBUS2_TX,
  66         DMACH_SLIMBUS4_RX,
  67         DMACH_SLIMBUS4_TX,
  68         DMACH_AC97_MICIN,
  69         DMACH_AC97_PCMIN,
  70         DMACH_AC97_PCMOUT,
  71 };
  72
  73 static u8 exynos4212_pdma0_peri[] = {
  74         DMACH_PCM0_RX,
  75         DMACH_PCM0_TX,
  76         DMACH_PCM2_RX,
  77         DMACH_PCM2_TX,
  78         DMACH_MIPI_HSI0,
  79         DMACH_MIPI_HSI1,
  80         DMACH_SPI0_RX,
  81         DMACH_SPI0_TX,
  82         DMACH_SPI2_RX,
  83         DMACH_SPI2_TX,
  84         DMACH_I2S0S_TX,
  85         DMACH_I2S0_RX,
  86         DMACH_I2S0_TX,
  87         DMACH_I2S2_RX,
  88         DMACH_I2S2_TX,
  89         DMACH_UART0_RX,
  90         DMACH_UART0_TX,
  91         DMACH_UART2_RX,
  92         DMACH_UART2_TX,
  93         DMACH_UART4_RX,
  94         DMACH_UART4_TX,
  95         DMACH_SLIMBUS0_RX,
  96         DMACH_SLIMBUS0_TX,
  97         DMACH_SLIMBUS2_RX,
  98         DMACH_SLIMBUS2_TX,
  99         DMACH_SLIMBUS4_RX,
 100         DMACH_SLIMBUS4_TX,
 101         DMACH_AC97_MICIN,
 102         DMACH_AC97_PCMIN,
 103         DMACH_AC97_PCMOUT,
 104         DMACH_MIPI_HSI4,
 105         DMACH_MIPI_HSI5,
 106 };
 107
 108 struct dma_pl330_platdata exynos4_pdma0_pdata;
 109
 110 static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
 111         EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata);
 112
 113 static u8 exynos4210_pdma1_peri[] = {
 114         DMACH_PCM0_RX,
 115         DMACH_PCM0_TX,
 116         DMACH_PCM1_RX,
 117         DMACH_PCM1_TX,
 118         DMACH_MSM_REQ1,
 119         DMACH_MSM_REQ3,
 120         DMACH_SPI1_RX,
 121         DMACH_SPI1_TX,
 122         DMACH_I2S0S_TX,
 123         DMACH_I2S0_RX,
 124         DMACH_I2S0_TX,
 125         DMACH_I2S1_RX,
 126         DMACH_I2S1_TX,
 127         DMACH_UART0_RX,
 128         DMACH_UART0_TX,
 129         DMACH_UART1_RX,
 130         DMACH_UART1_TX,
 131         DMACH_UART3_RX,
 132         DMACH_UART3_TX,
 133         DMACH_SLIMBUS1_RX,
 134         DMACH_SLIMBUS1_TX,
 135         DMACH_SLIMBUS3_RX,
 136         DMACH_SLIMBUS3_TX,
 137         DMACH_SLIMBUS5_RX,
 138         DMACH_SLIMBUS5_TX,
 139 };
 140
 141 static u8 exynos4212_pdma1_peri[] = {
 142         DMACH_PCM0_RX,
 143         DMACH_PCM0_TX,
 144         DMACH_PCM1_RX,
 145         DMACH_PCM1_TX,
 146         DMACH_MIPI_HSI2,
 147         DMACH_MIPI_HSI3,
 148         DMACH_SPI1_RX,
 149         DMACH_SPI1_TX,
 150         DMACH_I2S0S_TX,
 151         DMACH_I2S0_RX,
 152         DMACH_I2S0_TX,
 153         DMACH_I2S1_RX,
 154         DMACH_I2S1_TX,
 155         DMACH_UART0_RX,
 156         DMACH_UART0_TX,
 157         DMACH_UART1_RX,
 158         DMACH_UART1_TX,
 159         DMACH_UART3_RX,
 160         DMACH_UART3_TX,
 161         DMACH_SLIMBUS1_RX,
 162         DMACH_SLIMBUS1_TX,
 163         DMACH_SLIMBUS3_RX,
 164         DMACH_SLIMBUS3_TX,
 165         DMACH_SLIMBUS5_RX,
 166         DMACH_SLIMBUS5_TX,
 167         DMACH_SLIMBUS0AUX_RX,
 168         DMACH_SLIMBUS0AUX_TX,
 169         DMACH_SPDIF,
 170         DMACH_MIPI_HSI6,
 171         DMACH_MIPI_HSI7,
 172 };
 173
 174 static struct dma_pl330_platdata exynos4_pdma1_pdata;
 175
 176 static AMBA_AHB_DEVICE(exynos4_pdma1,  "dma-pl330.1", 0x00041330,
 177         EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata);
 178
 179 static u8 mdma_peri[] = {
 180         DMACH_MTOM_0,
 181         DMACH_MTOM_1,
 182         DMACH_MTOM_2,
 183         DMACH_MTOM_3,
 184         DMACH_MTOM_4,
 185         DMACH_MTOM_5,
 186         DMACH_MTOM_6,
 187         DMACH_MTOM_7,
 188 };
 189
 190 static struct dma_pl330_platdata exynos4_mdma1_pdata = {
 191         .nr_valid_peri = ARRAY_SIZE(mdma_peri),
 192         .peri_id = mdma_peri,
 193 };
 194
 195 static AMBA_AHB_DEVICE(exynos4_mdma1,  "dma-pl330.2", 0x00041330,
 196         EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata);
 197
 198 static int __init exynos4_dma_init(void)
 199 {
 200         if (of_have_populated_dt())
 201                 return 0;
 202
 203         if (soc_is_exynos4210()) {
 204                 exynos4_pdma0_pdata.nr_valid_peri =
 205                         ARRAY_SIZE(exynos4210_pdma0_peri);
 206                 exynos4_pdma0_pdata.peri_id = exynos4210_pdma0_peri;
 207                 exynos4_pdma1_pdata.nr_valid_peri =
 208                         ARRAY_SIZE(exynos4210_pdma1_peri);
 209                 exynos4_pdma1_pdata.peri_id = exynos4210_pdma1_peri;
 210         } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
 211                 exynos4_pdma0_pdata.nr_valid_peri =
 212                         ARRAY_SIZE(exynos4212_pdma0_peri);
 213                 exynos4_pdma0_pdata.peri_id = exynos4212_pdma0_peri;
 214                 exynos4_pdma1_pdata.nr_valid_peri =
 215                         ARRAY_SIZE(exynos4212_pdma1_peri);
 216                 exynos4_pdma1_pdata.peri_id = exynos4212_pdma1_peri;
 217         }
 218
 219         dma_cap_set(DMA_SLAVE, exynos4_pdma0_pdata.cap_mask);
 220         dma_cap_set(DMA_CYCLIC, exynos4_pdma0_pdata.cap_mask);
 221         amba_device_register(&exynos4_pdma0_device, &iomem_resource);
 222
 223         dma_cap_set(DMA_SLAVE, exynos4_pdma1_pdata.cap_mask);
 224         dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
 225         amba_device_register(&exynos4_pdma1_device, &iomem_resource);
 226
 227         dma_cap_set(DMA_MEMCPY, exynos4_mdma1_pdata.cap_mask);
 228         amba_device_register(&exynos4_mdma1_device, &iomem_resource);
 229
 230         return 0;
 231 }
 232 arch_initcall(exynos4_dma_init);