arch/arm/mach-davinci/dm644x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/clk/davinci.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/dmaengine.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/irqchip/irq-davinci-aintc.h>
  19 #include <linux/platform_data/edma.h>
  20 #include <linux/platform_data/gpio-davinci.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/serial_8250.h>
  23
  24 #include <asm/mach/map.h>
  25
  26 #include <mach/common.h>
  27 #include <mach/cputype.h>
  28 #include <mach/mux.h>
  29 #include <mach/serial.h>
  30 #include <mach/time.h>
  31
  32 #include "asp.h"
  33 #include "davinci.h"
  34 #include "irqs.h"
  35 #include "mux.h"
  36
  37 /*
  38  * Device specific clocks
  39  */
  40 #define DM644X_REF_FREQ         27000000
  41
  42 #define DM644X_EMAC_BASE                0x01c80000
  43 #define DM644X_EMAC_MDIO_BASE           (DM644X_EMAC_BASE + 0x4000)
  44 #define DM644X_EMAC_CNTRL_OFFSET        0x0000
  45 #define DM644X_EMAC_CNTRL_MOD_OFFSET    0x1000
  46 #define DM644X_EMAC_CNTRL_RAM_OFFSET    0x2000
  47 #define DM644X_EMAC_CNTRL_RAM_SIZE      0x2000
  48
  49 static struct emac_platform_data dm644x_emac_pdata = {
  50         .ctrl_reg_offset        = DM644X_EMAC_CNTRL_OFFSET,
  51         .ctrl_mod_reg_offset    = DM644X_EMAC_CNTRL_MOD_OFFSET,
  52         .ctrl_ram_offset        = DM644X_EMAC_CNTRL_RAM_OFFSET,
  53         .ctrl_ram_size          = DM644X_EMAC_CNTRL_RAM_SIZE,
  54         .version                = EMAC_VERSION_1,
  55 };
  56
  57 static struct resource dm644x_emac_resources[] = {
  58         {
  59                 .start  = DM644X_EMAC_BASE,
  60                 .end    = DM644X_EMAC_BASE + SZ_16K - 1,
  61                 .flags  = IORESOURCE_MEM,
  62         },
  63         {
  64                 .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
  65                 .end   = DAVINCI_INTC_IRQ(IRQ_EMACINT),
  66                 .flags = IORESOURCE_IRQ,
  67         },
  68 };
  69
  70 static struct platform_device dm644x_emac_device = {
  71        .name            = "davinci_emac",
  72        .id              = 1,
  73        .dev = {
  74                .platform_data   = &dm644x_emac_pdata,
  75        },
  76        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
  77        .resource        = dm644x_emac_resources,
  78 };
  79
  80 static struct resource dm644x_mdio_resources[] = {
  81         {
  82                 .start  = DM644X_EMAC_MDIO_BASE,
  83                 .end    = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
  84                 .flags  = IORESOURCE_MEM,
  85         },
  86 };
  87
  88 static struct platform_device dm644x_mdio_device = {
  89         .name           = "davinci_mdio",
  90         .id             = 0,
  91         .num_resources  = ARRAY_SIZE(dm644x_mdio_resources),
  92         .resource       = dm644x_mdio_resources,
  93 };
  94
  95 /*
  96  * Device specific mux setup
  97  *
  98  *      soc     description     mux  mode   mode  mux    dbg
  99  *                              reg  offset mask  mode
 100  */
 101 static const struct mux_config dm644x_pins[] = {
 102 #ifdef CONFIG_DAVINCI_MUX
 103 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
 104 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
 105 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
 106
 107 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
 108
 109 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
 110 MUX_CFG(DM644X, AEAW0,          0,   0,     1,    0,     true)
 111 MUX_CFG(DM644X, AEAW1,          0,   1,     1,    0,     true)
 112 MUX_CFG(DM644X, AEAW2,          0,   2,     1,    0,     true)
 113 MUX_CFG(DM644X, AEAW3,          0,   3,     1,    0,     true)
 114 MUX_CFG(DM644X, AEAW4,          0,   4,     1,    0,     true)
 115
 116 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
 117
 118 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
 119
 120 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
 121
 122 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
 123 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
 124
 125 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
 126
 127 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
 128
 129 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
 130
 131 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
 132 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
 133 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
 134
 135 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
 136
 137 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
 138
 139 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
 140 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
 141 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
 142 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
 143
 144 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
 145
 146 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
 147 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
 148 #endif
 149 };
 150
 151 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 152 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 153         [IRQ_VDINT0]            = 2,
 154         [IRQ_VDINT1]            = 6,
 155         [IRQ_VDINT2]            = 6,
 156         [IRQ_HISTINT]           = 6,
 157         [IRQ_H3AINT]            = 6,
 158         [IRQ_PRVUINT]           = 6,
 159         [IRQ_RSZINT]            = 6,
 160         [7]                     = 7,
 161         [IRQ_VENCINT]           = 6,
 162         [IRQ_ASQINT]            = 6,
 163         [IRQ_IMXINT]            = 6,
 164         [IRQ_VLCDINT]           = 6,
 165         [IRQ_USBINT]            = 4,
 166         [IRQ_EMACINT]           = 4,
 167         [14]                    = 7,
 168         [15]                    = 7,
 169         [IRQ_CCINT0]            = 5,    /* dma */
 170         [IRQ_CCERRINT]          = 5,    /* dma */
 171         [IRQ_TCERRINT0]         = 5,    /* dma */
 172         [IRQ_TCERRINT]          = 5,    /* dma */
 173         [IRQ_PSCIN]             = 7,
 174         [21]                    = 7,
 175         [IRQ_IDE]               = 4,
 176         [23]                    = 7,
 177         [IRQ_MBXINT]            = 7,
 178         [IRQ_MBRINT]            = 7,
 179         [IRQ_MMCINT]            = 7,
 180         [IRQ_SDIOINT]           = 7,
 181         [28]                    = 7,
 182         [IRQ_DDRINT]            = 7,
 183         [IRQ_AEMIFINT]          = 7,
 184         [IRQ_VLQINT]            = 4,
 185         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
 186         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
 187         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
 188         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
 189         [IRQ_PWMINT0]           = 7,
 190         [IRQ_PWMINT1]           = 7,
 191         [IRQ_PWMINT2]           = 7,
 192         [IRQ_I2C]               = 3,
 193         [IRQ_UARTINT0]          = 3,
 194         [IRQ_UARTINT1]          = 3,
 195         [IRQ_UARTINT2]          = 3,
 196         [IRQ_SPINT0]            = 3,
 197         [IRQ_SPINT1]            = 3,
 198         [45]                    = 7,
 199         [IRQ_DSP2ARM0]          = 4,
 200         [IRQ_DSP2ARM1]          = 4,
 201         [IRQ_GPIO0]             = 7,
 202         [IRQ_GPIO1]             = 7,
 203         [IRQ_GPIO2]             = 7,
 204         [IRQ_GPIO3]             = 7,
 205         [IRQ_GPIO4]             = 7,
 206         [IRQ_GPIO5]             = 7,
 207         [IRQ_GPIO6]             = 7,
 208         [IRQ_GPIO7]             = 7,
 209         [IRQ_GPIOBNK0]          = 7,
 210         [IRQ_GPIOBNK1]          = 7,
 211         [IRQ_GPIOBNK2]          = 7,
 212         [IRQ_GPIOBNK3]          = 7,
 213         [IRQ_GPIOBNK4]          = 7,
 214         [IRQ_COMMTX]            = 7,
 215         [IRQ_COMMRX]            = 7,
 216         [IRQ_EMUINT]            = 7,
 217 };
 218
 219 /*----------------------------------------------------------------------*/
 220
 221 static s8 queue_priority_mapping[][2] = {
 222         /* {event queue no, Priority} */
 223         {0, 3},
 224         {1, 7},
 225         {-1, -1},
 226 };
 227
 228 static const struct dma_slave_map dm644x_edma_map[] = {
 229         { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
 230         { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
 231         { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
 232         { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
 233         { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
 234         { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
 235 };
 236
 237 static struct edma_soc_info dm644x_edma_pdata = {
 238         .queue_priority_mapping = queue_priority_mapping,
 239         .default_queue          = EVENTQ_1,
 240         .slave_map              = dm644x_edma_map,
 241         .slavecnt               = ARRAY_SIZE(dm644x_edma_map),
 242 };
 243
 244 static struct resource edma_resources[] = {
 245         {
 246                 .name   = "edma3_cc",
 247                 .start  = 0x01c00000,
 248                 .end    = 0x01c00000 + SZ_64K - 1,
 249                 .flags  = IORESOURCE_MEM,
 250         },
 251         {
 252                 .name   = "edma3_tc0",
 253                 .start  = 0x01c10000,
 254                 .end    = 0x01c10000 + SZ_1K - 1,
 255                 .flags  = IORESOURCE_MEM,
 256         },
 257         {
 258                 .name   = "edma3_tc1",
 259                 .start  = 0x01c10400,
 260                 .end    = 0x01c10400 + SZ_1K - 1,
 261                 .flags  = IORESOURCE_MEM,
 262         },
 263         {
 264                 .name   = "edma3_ccint",
 265                 .start  = DAVINCI_INTC_IRQ(IRQ_CCINT0),
 266                 .flags  = IORESOURCE_IRQ,
 267         },
 268         {
 269                 .name   = "edma3_ccerrint",
 270                 .start  = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
 271                 .flags  = IORESOURCE_IRQ,
 272         },
 273         /* not using TC*_ERR */
 274 };
 275
 276 static const struct platform_device_info dm644x_edma_device __initconst = {
 277         .name           = "edma",
 278         .id             = 0,
 279         .dma_mask       = DMA_BIT_MASK(32),
 280         .res            = edma_resources,
 281         .num_res        = ARRAY_SIZE(edma_resources),
 282         .data           = &dm644x_edma_pdata,
 283         .size_data      = sizeof(dm644x_edma_pdata),
 284 };
 285
 286 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
 287 static struct resource dm644x_asp_resources[] = {
 288         {
 289                 .name   = "mpu",
 290                 .start  = DAVINCI_ASP0_BASE,
 291                 .end    = DAVINCI_ASP0_BASE + SZ_8K - 1,
 292                 .flags  = IORESOURCE_MEM,
 293         },
 294         {
 295                 .start  = DAVINCI_DMA_ASP0_TX,
 296                 .end    = DAVINCI_DMA_ASP0_TX,
 297                 .flags  = IORESOURCE_DMA,
 298         },
 299         {
 300                 .start  = DAVINCI_DMA_ASP0_RX,
 301                 .end    = DAVINCI_DMA_ASP0_RX,
 302                 .flags  = IORESOURCE_DMA,
 303         },
 304 };
 305
 306 static struct platform_device dm644x_asp_device = {
 307         .name           = "davinci-mcbsp",
 308         .id             = -1,
 309         .num_resources  = ARRAY_SIZE(dm644x_asp_resources),
 310         .resource       = dm644x_asp_resources,
 311 };
 312
 313 #define DM644X_VPSS_BASE        0x01c73400
 314
 315 static struct resource dm644x_vpss_resources[] = {
 316         {
 317                 /* VPSS Base address */
 318                 .name           = "vpss",
 319                 .start          = DM644X_VPSS_BASE,
 320                 .end            = DM644X_VPSS_BASE + 0xff,
 321                 .flags          = IORESOURCE_MEM,
 322         },
 323 };
 324
 325 static struct platform_device dm644x_vpss_device = {
 326         .name                   = "vpss",
 327         .id                     = -1,
 328         .dev.platform_data      = "dm644x_vpss",
 329         .num_resources          = ARRAY_SIZE(dm644x_vpss_resources),
 330         .resource               = dm644x_vpss_resources,
 331 };
 332
 333 static struct resource dm644x_vpfe_resources[] = {
 334         {
 335                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 336                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT0),
 337                 .flags          = IORESOURCE_IRQ,
 338         },
 339         {
 340                 .start          = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 341                 .end            = DAVINCI_INTC_IRQ(IRQ_VDINT1),
 342                 .flags          = IORESOURCE_IRQ,
 343         },
 344 };
 345
 346 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
 347 static struct resource dm644x_ccdc_resource[] = {
 348         /* CCDC Base address */
 349         {
 350                 .start          = 0x01c70400,
 351                 .end            = 0x01c70400 + 0xff,
 352                 .flags          = IORESOURCE_MEM,
 353         },
 354 };
 355
 356 static struct platform_device dm644x_ccdc_dev = {
 357         .name           = "dm644x_ccdc",
 358         .id             = -1,
 359         .num_resources  = ARRAY_SIZE(dm644x_ccdc_resource),
 360         .resource       = dm644x_ccdc_resource,
 361         .dev = {
 362                 .dma_mask               = &dm644x_video_dma_mask,
 363                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 364         },
 365 };
 366
 367 static struct platform_device dm644x_vpfe_dev = {
 368         .name           = CAPTURE_DRV_NAME,
 369         .id             = -1,
 370         .num_resources  = ARRAY_SIZE(dm644x_vpfe_resources),
 371         .resource       = dm644x_vpfe_resources,
 372         .dev = {
 373                 .dma_mask               = &dm644x_video_dma_mask,
 374                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 375         },
 376 };
 377
 378 #define DM644X_OSD_BASE         0x01c72600
 379
 380 static struct resource dm644x_osd_resources[] = {
 381         {
 382                 .start  = DM644X_OSD_BASE,
 383                 .end    = DM644X_OSD_BASE + 0x1ff,
 384                 .flags  = IORESOURCE_MEM,
 385         },
 386 };
 387
 388 static struct platform_device dm644x_osd_dev = {
 389         .name           = DM644X_VPBE_OSD_SUBDEV_NAME,
 390         .id             = -1,
 391         .num_resources  = ARRAY_SIZE(dm644x_osd_resources),
 392         .resource       = dm644x_osd_resources,
 393         .dev            = {
 394                 .dma_mask               = &dm644x_video_dma_mask,
 395                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 396         },
 397 };
 398
 399 #define DM644X_VENC_BASE                0x01c72400
 400
 401 static struct resource dm644x_venc_resources[] = {
 402         {
 403                 .start  = DM644X_VENC_BASE,
 404                 .end    = DM644X_VENC_BASE + 0x17f,
 405                 .flags  = IORESOURCE_MEM,
 406         },
 407 };
 408
 409 #define DM644X_VPSS_MUXSEL_PLL2_MODE          BIT(0)
 410 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE       BIT(1)
 411 #define DM644X_VPSS_VENCLKEN                  BIT(3)
 412 #define DM644X_VPSS_DACCLKEN                  BIT(4)
 413
 414 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
 415                                    unsigned int pclock)
 416 {
 417         int ret = 0;
 418         u32 v = DM644X_VPSS_VENCLKEN;
 419
 420         switch (type) {
 421         case VPBE_ENC_STD:
 422                 v |= DM644X_VPSS_DACCLKEN;
 423                 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
 424                 break;
 425         case VPBE_ENC_DV_TIMINGS:
 426                 if (pclock <= 27000000) {
 427                         v |= DM644X_VPSS_DACCLKEN;
 428                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
 429                 } else {
 430                         /*
 431                          * For HD, use external clock source since
 432                          * HD requires higher clock rate
 433                          */
 434                         v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
 435                         writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
 436                 }
 437                 break;
 438         default:
 439                 ret  = -EINVAL;
 440         }
 441
 442         return ret;
 443 }
 444
 445 static struct resource dm644x_v4l2_disp_resources[] = {
 446         {
 447                 .start  = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 448                 .end    = DAVINCI_INTC_IRQ(IRQ_VENCINT),
 449                 .flags  = IORESOURCE_IRQ,
 450         },
 451 };
 452
 453 static struct platform_device dm644x_vpbe_display = {
 454         .name           = "vpbe-v4l2",
 455         .id             = -1,
 456         .num_resources  = ARRAY_SIZE(dm644x_v4l2_disp_resources),
 457         .resource       = dm644x_v4l2_disp_resources,
 458         .dev            = {
 459                 .dma_mask               = &dm644x_video_dma_mask,
 460                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 461         },
 462 };
 463
 464 static struct venc_platform_data dm644x_venc_pdata = {
 465         .setup_clock    = dm644x_venc_setup_clock,
 466 };
 467
 468 static struct platform_device dm644x_venc_dev = {
 469         .name           = DM644X_VPBE_VENC_SUBDEV_NAME,
 470         .id             = -1,
 471         .num_resources  = ARRAY_SIZE(dm644x_venc_resources),
 472         .resource       = dm644x_venc_resources,
 473         .dev            = {
 474                 .dma_mask               = &dm644x_video_dma_mask,
 475                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 476                 .platform_data          = &dm644x_venc_pdata,
 477         },
 478 };
 479
 480 static struct platform_device dm644x_vpbe_dev = {
 481         .name           = "vpbe_controller",
 482         .id             = -1,
 483         .dev            = {
 484                 .dma_mask               = &dm644x_video_dma_mask,
 485                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 486         },
 487 };
 488
 489 static struct resource dm644_gpio_resources[] = {
 490         {       /* registers */
 491                 .start  = DAVINCI_GPIO_BASE,
 492                 .end    = DAVINCI_GPIO_BASE + SZ_4K - 1,
 493                 .flags  = IORESOURCE_MEM,
 494         },
 495         {       /* interrupt */
 496                 .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
 497                 .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
 498                 .flags  = IORESOURCE_IRQ,
 499         },
 500         {
 501                 .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
 502                 .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
 503                 .flags  = IORESOURCE_IRQ,
 504         },
 505         {
 506                 .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
 507                 .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
 508                 .flags  = IORESOURCE_IRQ,
 509         },
 510         {
 511                 .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
 512                 .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
 513                 .flags  = IORESOURCE_IRQ,
 514         },
 515         {
 516                 .start  = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
 517                 .end    = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
 518                 .flags  = IORESOURCE_IRQ,
 519         },
 520 };
 521
 522 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
 523         .no_auto_base   = true,
 524         .base           = 0,
 525         .ngpio          = 71,
 526 };
 527
 528 int __init dm644x_gpio_register(void)
 529 {
 530         return davinci_gpio_register(dm644_gpio_resources,
 531                                      ARRAY_SIZE(dm644_gpio_resources),
 532                                      &dm644_gpio_platform_data);
 533 }
 534 /*----------------------------------------------------------------------*/
 535
 536 static struct map_desc dm644x_io_desc[] = {
 537         {
 538                 .virtual        = IO_VIRT,
 539                 .pfn            = __phys_to_pfn(IO_PHYS),
 540                 .length         = IO_SIZE,
 541                 .type           = MT_DEVICE
 542         },
 543 };
 544
 545 /* Contents of JTAG ID register used to identify exact cpu type */
 546 static struct davinci_id dm644x_ids[] = {
 547         {
 548                 .variant        = 0x0,
 549                 .part_no        = 0xb700,
 550                 .manufacturer   = 0x017,
 551                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
 552                 .name           = "dm6446",
 553         },
 554         {
 555                 .variant        = 0x1,
 556                 .part_no        = 0xb700,
 557                 .manufacturer   = 0x017,
 558                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
 559                 .name           = "dm6446a",
 560         },
 561 };
 562
 563 /*
 564  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 565  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 566  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 567  * T1_TOP: Timer 1, top   :  <unused>
 568  */
 569 static struct davinci_timer_info dm644x_timer_info = {
 570         .timers         = davinci_timer_instance,
 571         .clockevent_id  = T0_BOT,
 572         .clocksource_id = T0_TOP,
 573 };
 574
 575 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
 576         {
 577                 .mapbase        = DAVINCI_UART0_BASE,
 578                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
 579                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 580                                   UPF_IOREMAP,
 581                 .iotype         = UPIO_MEM,
 582                 .regshift       = 2,
 583         },
 584         {
 585                 .flags  = 0,
 586         }
 587 };
 588 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
 589         {
 590                 .mapbase        = DAVINCI_UART1_BASE,
 591                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
 592                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 593                                   UPF_IOREMAP,
 594                 .iotype         = UPIO_MEM,
 595                 .regshift       = 2,
 596         },
 597         {
 598                 .flags  = 0,
 599         }
 600 };
 601 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
 602         {
 603                 .mapbase        = DAVINCI_UART2_BASE,
 604                 .irq            = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
 605                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 606                                   UPF_IOREMAP,
 607                 .iotype         = UPIO_MEM,
 608                 .regshift       = 2,
 609         },
 610         {
 611                 .flags  = 0,
 612         }
 613 };
 614
 615 struct platform_device dm644x_serial_device[] = {
 616         {
 617                 .name                   = "serial8250",
 618                 .id                     = PLAT8250_DEV_PLATFORM,
 619                 .dev                    = {
 620                         .platform_data  = dm644x_serial0_platform_data,
 621                 }
 622         },
 623         {
 624                 .name                   = "serial8250",
 625                 .id                     = PLAT8250_DEV_PLATFORM1,
 626                 .dev                    = {
 627                         .platform_data  = dm644x_serial1_platform_data,
 628                 }
 629         },
 630         {
 631                 .name                   = "serial8250",
 632                 .id                     = PLAT8250_DEV_PLATFORM2,
 633                 .dev                    = {
 634                         .platform_data  = dm644x_serial2_platform_data,
 635                 }
 636         },
 637         {
 638         }
 639 };
 640
 641 static const struct davinci_soc_info davinci_soc_info_dm644x = {
 642         .io_desc                = dm644x_io_desc,
 643         .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
 644         .jtag_id_reg            = 0x01c40028,
 645         .ids                    = dm644x_ids,
 646         .ids_num                = ARRAY_SIZE(dm644x_ids),
 647         .pinmux_base            = DAVINCI_SYSTEM_MODULE_BASE,
 648         .pinmux_pins            = dm644x_pins,
 649         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
 650         .timer_info             = &dm644x_timer_info,
 651         .emac_pdata             = &dm644x_emac_pdata,
 652         .sram_dma               = 0x00008000,
 653         .sram_len               = SZ_16K,
 654 };
 655
 656 void __init dm644x_init_asp(void)
 657 {
 658         davinci_cfg_reg(DM644X_MCBSP);
 659         platform_device_register(&dm644x_asp_device);
 660 }
 661
 662 void __init dm644x_init(void)
 663 {
 664         davinci_common_init(&davinci_soc_info_dm644x);
 665         davinci_map_sysmod();
 666 }
 667
 668 void __init dm644x_init_time(void)
 669 {
 670         void __iomem *pll1, *psc;
 671         struct clk *clk;
 672
 673         clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
 674
 675         pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
 676         dm644x_pll1_init(NULL, pll1, NULL);
 677
 678         psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
 679         dm644x_psc_init(NULL, psc);
 680
 681         clk = clk_get(NULL, "timer0");
 682
 683         davinci_timer_init(clk);
 684 }
 685
 686 static struct resource dm644x_pll2_resources[] = {
 687         {
 688                 .start  = DAVINCI_PLL2_BASE,
 689                 .end    = DAVINCI_PLL2_BASE + SZ_1K - 1,
 690                 .flags  = IORESOURCE_MEM,
 691         },
 692 };
 693
 694 static struct platform_device dm644x_pll2_device = {
 695         .name           = "dm644x-pll2",
 696         .id             = -1,
 697         .resource       = dm644x_pll2_resources,
 698         .num_resources  = ARRAY_SIZE(dm644x_pll2_resources),
 699 };
 700
 701 void __init dm644x_register_clocks(void)
 702 {
 703         /* PLL1 and PSC are registered in dm644x_init_time() */
 704         platform_device_register(&dm644x_pll2_device);
 705 }
 706
 707 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
 708                                 struct vpbe_config *vpbe_cfg)
 709 {
 710         if (vpfe_cfg || vpbe_cfg)
 711                 platform_device_register(&dm644x_vpss_device);
 712
 713         if (vpfe_cfg) {
 714                 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
 715                 platform_device_register(&dm644x_ccdc_dev);
 716                 platform_device_register(&dm644x_vpfe_dev);
 717         }
 718
 719         if (vpbe_cfg) {
 720                 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
 721                 platform_device_register(&dm644x_osd_dev);
 722                 platform_device_register(&dm644x_venc_dev);
 723                 platform_device_register(&dm644x_vpbe_dev);
 724                 platform_device_register(&dm644x_vpbe_display);
 725         }
 726
 727         return 0;
 728 }
 729
 730 static const struct davinci_aintc_config dm644x_aintc_config = {
 731         .reg = {
 732                 .start          = DAVINCI_ARM_INTC_BASE,
 733                 .end            = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
 734                 .flags          = IORESOURCE_MEM,
 735         },
 736         .num_irqs               = 64,
 737         .prios                  = dm644x_default_priorities,
 738 };
 739
 740 void __init dm644x_init_irq(void)
 741 {
 742         davinci_aintc_init(&dm644x_aintc_config);
 743 }
 744
 745 void __init dm644x_init_devices(void)
 746 {
 747         struct platform_device *edma_pdev;
 748         int ret;
 749
 750         edma_pdev = platform_device_register_full(&dm644x_edma_device);
 751         if (IS_ERR(edma_pdev))
 752                 pr_warn("%s: Failed to register eDMA\n", __func__);
 753
 754         platform_device_register(&dm644x_mdio_device);
 755         platform_device_register(&dm644x_emac_device);
 756
 757         ret = davinci_init_wdt();
 758         if (ret)
 759                 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
 760
 761 }