arch/arm/mach-at91/at91sam9260.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9260.c
   3  *
   4  *  Copyright (C) 2006 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/proc-fns.h>
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <asm/system_misc.h>
  20 #include <mach/cpu.h>
  21 #include <mach/at91_dbgu.h>
  22 #include <mach/at91sam9260.h>
  23 #include <mach/at91_pmc.h>
  24 #include <mach/at91_rstc.h>
  25
  26 #include "soc.h"
  27 #include "generic.h"
  28 #include "clock.h"
  29 #include "sam9_smc.h"
  30
  31 /* --------------------------------------------------------------------
  32  *  Clocks
  33  * -------------------------------------------------------------------- */
  34
  35 /*
  36  * The peripheral clocks.
  37  */
  38 static struct clk pioA_clk = {
  39         .name           = "pioA_clk",
  40         .pmc_mask       = 1 << AT91SAM9260_ID_PIOA,
  41         .type           = CLK_TYPE_PERIPHERAL,
  42 };
  43 static struct clk pioB_clk = {
  44         .name           = "pioB_clk",
  45         .pmc_mask       = 1 << AT91SAM9260_ID_PIOB,
  46         .type           = CLK_TYPE_PERIPHERAL,
  47 };
  48 static struct clk pioC_clk = {
  49         .name           = "pioC_clk",
  50         .pmc_mask       = 1 << AT91SAM9260_ID_PIOC,
  51         .type           = CLK_TYPE_PERIPHERAL,
  52 };
  53 static struct clk adc_clk = {
  54         .name           = "adc_clk",
  55         .pmc_mask       = 1 << AT91SAM9260_ID_ADC,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58
  59 static struct clk adc_op_clk = {
  60         .name           = "adc_op_clk",
  61         .type           = CLK_TYPE_PERIPHERAL,
  62         .rate_hz        = 5000000,
  63 };
  64
  65 static struct clk usart0_clk = {
  66         .name           = "usart0_clk",
  67         .pmc_mask       = 1 << AT91SAM9260_ID_US0,
  68         .type           = CLK_TYPE_PERIPHERAL,
  69 };
  70 static struct clk usart1_clk = {
  71         .name           = "usart1_clk",
  72         .pmc_mask       = 1 << AT91SAM9260_ID_US1,
  73         .type           = CLK_TYPE_PERIPHERAL,
  74 };
  75 static struct clk usart2_clk = {
  76         .name           = "usart2_clk",
  77         .pmc_mask       = 1 << AT91SAM9260_ID_US2,
  78         .type           = CLK_TYPE_PERIPHERAL,
  79 };
  80 static struct clk mmc_clk = {
  81         .name           = "mci_clk",
  82         .pmc_mask       = 1 << AT91SAM9260_ID_MCI,
  83         .type           = CLK_TYPE_PERIPHERAL,
  84 };
  85 static struct clk udc_clk = {
  86         .name           = "udc_clk",
  87         .pmc_mask       = 1 << AT91SAM9260_ID_UDP,
  88         .type           = CLK_TYPE_PERIPHERAL,
  89 };
  90 static struct clk twi_clk = {
  91         .name           = "twi_clk",
  92         .pmc_mask       = 1 << AT91SAM9260_ID_TWI,
  93         .type           = CLK_TYPE_PERIPHERAL,
  94 };
  95 static struct clk spi0_clk = {
  96         .name           = "spi0_clk",
  97         .pmc_mask       = 1 << AT91SAM9260_ID_SPI0,
  98         .type           = CLK_TYPE_PERIPHERAL,
  99 };
 100 static struct clk spi1_clk = {
 101         .name           = "spi1_clk",
 102         .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
 103         .type           = CLK_TYPE_PERIPHERAL,
 104 };
 105 static struct clk ssc_clk = {
 106         .name           = "ssc_clk",
 107         .pmc_mask       = 1 << AT91SAM9260_ID_SSC,
 108         .type           = CLK_TYPE_PERIPHERAL,
 109 };
 110 static struct clk tc0_clk = {
 111         .name           = "tc0_clk",
 112         .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
 113         .type           = CLK_TYPE_PERIPHERAL,
 114 };
 115 static struct clk tc1_clk = {
 116         .name           = "tc1_clk",
 117         .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
 118         .type           = CLK_TYPE_PERIPHERAL,
 119 };
 120 static struct clk tc2_clk = {
 121         .name           = "tc2_clk",
 122         .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
 123         .type           = CLK_TYPE_PERIPHERAL,
 124 };
 125 static struct clk ohci_clk = {
 126         .name           = "ohci_clk",
 127         .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
 128         .type           = CLK_TYPE_PERIPHERAL,
 129 };
 130 static struct clk macb_clk = {
 131         .name           = "pclk",
 132         .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
 133         .type           = CLK_TYPE_PERIPHERAL,
 134 };
 135 static struct clk isi_clk = {
 136         .name           = "isi_clk",
 137         .pmc_mask       = 1 << AT91SAM9260_ID_ISI,
 138         .type           = CLK_TYPE_PERIPHERAL,
 139 };
 140 static struct clk usart3_clk = {
 141         .name           = "usart3_clk",
 142         .pmc_mask       = 1 << AT91SAM9260_ID_US3,
 143         .type           = CLK_TYPE_PERIPHERAL,
 144 };
 145 static struct clk usart4_clk = {
 146         .name           = "usart4_clk",
 147         .pmc_mask       = 1 << AT91SAM9260_ID_US4,
 148         .type           = CLK_TYPE_PERIPHERAL,
 149 };
 150 static struct clk usart5_clk = {
 151         .name           = "usart5_clk",
 152         .pmc_mask       = 1 << AT91SAM9260_ID_US5,
 153         .type           = CLK_TYPE_PERIPHERAL,
 154 };
 155 static struct clk tc3_clk = {
 156         .name           = "tc3_clk",
 157         .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
 158         .type           = CLK_TYPE_PERIPHERAL,
 159 };
 160 static struct clk tc4_clk = {
 161         .name           = "tc4_clk",
 162         .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
 163         .type           = CLK_TYPE_PERIPHERAL,
 164 };
 165 static struct clk tc5_clk = {
 166         .name           = "tc5_clk",
 167         .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
 168         .type           = CLK_TYPE_PERIPHERAL,
 169 };
 170
 171 static struct clk *periph_clocks[] __initdata = {
 172         &pioA_clk,
 173         &pioB_clk,
 174         &pioC_clk,
 175         &adc_clk,
 176         &adc_op_clk,
 177         &usart0_clk,
 178         &usart1_clk,
 179         &usart2_clk,
 180         &mmc_clk,
 181         &udc_clk,
 182         &twi_clk,
 183         &spi0_clk,
 184         &spi1_clk,
 185         &ssc_clk,
 186         &tc0_clk,
 187         &tc1_clk,
 188         &tc2_clk,
 189         &ohci_clk,
 190         &macb_clk,
 191         &isi_clk,
 192         &usart3_clk,
 193         &usart4_clk,
 194         &usart5_clk,
 195         &tc3_clk,
 196         &tc4_clk,
 197         &tc5_clk,
 198         // irq0 .. irq2
 199 };
 200
 201 static struct clk_lookup periph_clocks_lookups[] = {
 202         /* One additional fake clock for macb_hclk */
 203         CLKDEV_CON_ID("hclk", &macb_clk),
 204         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 205         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 206         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 207         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 208         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 209         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 210         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 211         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 212         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
 213         /* more usart lookup table for DT entries */
 214         CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
 215         CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
 216         CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
 217         CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
 218         CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
 219         CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
 220         CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
 221         /* more tc lookup table for DT entries */
 222         CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
 223         CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
 224         CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
 225         CLKDEV_CON_DEV_ID("t0_clk", "fffdc000.timer", &tc3_clk),
 226         CLKDEV_CON_DEV_ID("t1_clk", "fffdc000.timer", &tc4_clk),
 227         CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 228         CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
 229         /* fake hclk clock */
 230         CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 231         CLKDEV_CON_ID("pioA", &pioA_clk),
 232         CLKDEV_CON_ID("pioB", &pioB_clk),
 233         CLKDEV_CON_ID("pioC", &pioC_clk),
 234 };
 235
 236 static struct clk_lookup usart_clocks_lookups[] = {
 237         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 238         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 239         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 240         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 241         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 242         CLKDEV_CON_DEV_ID("usart", "atmel_usart.5", &usart4_clk),
 243         CLKDEV_CON_DEV_ID("usart", "atmel_usart.6", &usart5_clk),
 244 };
 245
 246 /*
 247  * The two programmable clocks.
 248  * You must configure pin multiplexing to bring these signals out.
 249  */
 250 static struct clk pck0 = {
 251         .name           = "pck0",
 252         .pmc_mask       = AT91_PMC_PCK0,
 253         .type           = CLK_TYPE_PROGRAMMABLE,
 254         .id             = 0,
 255 };
 256 static struct clk pck1 = {
 257         .name           = "pck1",
 258         .pmc_mask       = AT91_PMC_PCK1,
 259         .type           = CLK_TYPE_PROGRAMMABLE,
 260         .id             = 1,
 261 };
 262
 263 static void __init at91sam9260_register_clocks(void)
 264 {
 265         int i;
 266
 267         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 268                 clk_register(periph_clocks[i]);
 269
 270         clkdev_add_table(periph_clocks_lookups,
 271                          ARRAY_SIZE(periph_clocks_lookups));
 272         clkdev_add_table(usart_clocks_lookups,
 273                          ARRAY_SIZE(usart_clocks_lookups));
 274
 275         clk_register(&pck0);
 276         clk_register(&pck1);
 277 }
 278
 279 /* --------------------------------------------------------------------
 280  *  GPIO
 281  * -------------------------------------------------------------------- */
 282
 283 static struct at91_gpio_bank at91sam9260_gpio[] __initdata = {
 284         {
 285                 .id             = AT91SAM9260_ID_PIOA,
 286                 .regbase        = AT91SAM9260_BASE_PIOA,
 287         }, {
 288                 .id             = AT91SAM9260_ID_PIOB,
 289                 .regbase        = AT91SAM9260_BASE_PIOB,
 290         }, {
 291                 .id             = AT91SAM9260_ID_PIOC,
 292                 .regbase        = AT91SAM9260_BASE_PIOC,
 293         }
 294 };
 295
 296 /* --------------------------------------------------------------------
 297  *  AT91SAM9260 processor initialization
 298  * -------------------------------------------------------------------- */
 299
 300 static void __init at91sam9xe_map_io(void)
 301 {
 302         unsigned long sram_size;
 303
 304         switch (at91_soc_initdata.cidr & AT91_CIDR_SRAMSIZ) {
 305                 case AT91_CIDR_SRAMSIZ_32K:
 306                         sram_size = 2 * SZ_16K;
 307                         break;
 308                 case AT91_CIDR_SRAMSIZ_16K:
 309                 default:
 310                         sram_size = SZ_16K;
 311         }
 312
 313         at91_init_sram(0, AT91SAM9XE_SRAM_BASE, sram_size);
 314 }
 315
 316 static void __init at91sam9260_map_io(void)
 317 {
 318         if (cpu_is_at91sam9xe())
 319                 at91sam9xe_map_io();
 320         else if (cpu_is_at91sam9g20())
 321                 at91_init_sram(0, AT91SAM9G20_SRAM_BASE, AT91SAM9G20_SRAM_SIZE);
 322         else
 323                 at91_init_sram(0, AT91SAM9260_SRAM_BASE, AT91SAM9260_SRAM_SIZE);
 324 }
 325
 326 static void __init at91sam9260_ioremap_registers(void)
 327 {
 328         at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
 329         at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
 330         at91_ioremap_ramc(0, AT91SAM9260_BASE_SDRAMC, 512);
 331         at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
 332         at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
 333         at91_ioremap_matrix(AT91SAM9260_BASE_MATRIX);
 334 }
 335
 336 static void __init at91sam9260_initialize(void)
 337 {
 338         arm_pm_idle = at91sam9_idle;
 339         arm_pm_restart = at91sam9_alt_restart;
 340         at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
 341                         | (1 << AT91SAM9260_ID_IRQ2);
 342
 343         /* Register GPIO subsystem */
 344         at91_gpio_init(at91sam9260_gpio, 3);
 345 }
 346
 347 /* --------------------------------------------------------------------
 348  *  Interrupt initialization
 349  * -------------------------------------------------------------------- */
 350
 351 /*
 352  * The default interrupt priority levels (0 = lowest, 7 = highest).
 353  */
 354 static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
 355         7,      /* Advanced Interrupt Controller */
 356         7,      /* System Peripherals */
 357         1,      /* Parallel IO Controller A */
 358         1,      /* Parallel IO Controller B */
 359         1,      /* Parallel IO Controller C */
 360         0,      /* Analog-to-Digital Converter */
 361         5,      /* USART 0 */
 362         5,      /* USART 1 */
 363         5,      /* USART 2 */
 364         0,      /* Multimedia Card Interface */
 365         2,      /* USB Device Port */
 366         6,      /* Two-Wire Interface */
 367         5,      /* Serial Peripheral Interface 0 */
 368         5,      /* Serial Peripheral Interface 1 */
 369         5,      /* Serial Synchronous Controller */
 370         0,
 371         0,
 372         0,      /* Timer Counter 0 */
 373         0,      /* Timer Counter 1 */
 374         0,      /* Timer Counter 2 */
 375         2,      /* USB Host port */
 376         3,      /* Ethernet */
 377         0,      /* Image Sensor Interface */
 378         5,      /* USART 3 */
 379         5,      /* USART 4 */
 380         5,      /* USART 5 */
 381         0,      /* Timer Counter 3 */
 382         0,      /* Timer Counter 4 */
 383         0,      /* Timer Counter 5 */
 384         0,      /* Advanced Interrupt Controller */
 385         0,      /* Advanced Interrupt Controller */
 386         0,      /* Advanced Interrupt Controller */
 387 };
 388
 389 struct at91_init_soc __initdata at91sam9260_soc = {
 390         .map_io = at91sam9260_map_io,
 391         .default_irq_priority = at91sam9260_default_irq_priority,
 392         .ioremap_registers = at91sam9260_ioremap_registers,
 393         .register_clocks = at91sam9260_register_clocks,
 394         .init = at91sam9260_initialize,
 395 };