arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB SPU3 board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * SPU - Seat Power Unit
   8  *
   9  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB SPU3 Board";
  20         compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 reg = <0x80000000 0x20000000>;
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-0 = <&pinctrl_leds_debug>;
  34                 pinctrl-names = "default";
  35
  36                 led-debug {
  37                         label = "zii:green:debug1";
  38                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  39                         linux,default-trigger = "heartbeat";
  40                         max-brightness = <1>;
  41                 };
  42         };
  43
  44         reg_vcc_3v3_mcu: regulator {
  45                 compatible = "regulator-fixed";
  46                 regulator-name = "vcc_3v3_mcu";
  47                 regulator-min-microvolt = <3300000>;
  48                 regulator-max-microvolt = <3300000>;
  49         };
  50 };
  51
  52 &adc0 {
  53         vref-supply = <&reg_vcc_3v3_mcu>;
  54         status = "okay";
  55 };
  56
  57 &adc1 {
  58         vref-supply = <&reg_vcc_3v3_mcu>;
  59         status = "okay";
  60 };
  61
  62 &dspi1 {
  63         bus-num = <1>;
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_dspi1>;
  66         /*
  67          * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
  68          * node disabled by default and rely on bootloader to enable
  69          * it when appropriate.
  70          */
  71         status = "disabled";
  72
  73         m25p128@0 {
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 compatible = "m25p128", "jedec,spi-nor";
  77                 reg = <0>;
  78                 spi-max-frequency = <50000000>;
  79
  80                 partition@0 {
  81                         label = "m25p128-0";
  82                         reg = <0x0 0x01000000>;
  83                 };
  84         };
  85 };
  86
  87 &edma0 {
  88         status = "okay";
  89 };
  90
  91 &edma1 {
  92         status = "okay";
  93 };
  94
  95 &esdhc0 {
  96         pinctrl-names = "default";
  97         pinctrl-0 = <&pinctrl_esdhc0>;
  98         bus-width = <8>;
  99         non-removable;
 100         no-1-8-v;
 101         keep-power-in-suspend;
 102         status = "okay";
 103 };
 104
 105 &esdhc1 {
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&pinctrl_esdhc1>;
 108         bus-width = <4>;
 109         status = "okay";
 110 };
 111
 112 &fec1 {
 113         phy-mode = "rmii";
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&pinctrl_fec1>;
 116         status = "okay";
 117
 118         fixed-link {
 119                 speed = <100>;
 120                 full-duplex;
 121         };
 122
 123         mdio1: mdio {
 124                 #address-cells = <1>;
 125                 #size-cells = <0>;
 126                 status = "okay";
 127
 128                 switch0: switch0@0 {
 129                         compatible = "marvell,mv88e6190";
 130                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 131                         pinctrl-names = "default";
 132                         reg = <0>;
 133                         eeprom-length = <65536>;
 134                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 135                         interrupt-parent = <&gpio3>;
 136                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 137                         interrupt-controller;
 138                         #interrupt-cells = <2>;
 139
 140                         ports {
 141                                 #address-cells = <1>;
 142                                 #size-cells = <0>;
 143
 144                                 port@0 {
 145                                         reg = <0>;
 146                                         label = "cpu";
 147                                         ethernet = <&fec1>;
 148
 149                                         fixed-link {
 150                                                 speed = <100>;
 151                                                 full-duplex;
 152                                         };
 153                                 };
 154
 155                                 port@1 {
 156                                         reg = <1>;
 157                                         label = "eth_cu_1000_1";
 158                                 };
 159
 160                                 port@2 {
 161                                         reg = <2>;
 162                                         label = "eth_cu_1000_2";
 163                                 };
 164
 165                                 port@3 {
 166                                         reg = <3>;
 167                                         label = "eth_cu_1000_3";
 168                                 };
 169
 170                                 port@4 {
 171                                         reg = <4>;
 172                                         label = "eth_cu_1000_4";
 173                                 };
 174
 175                                 port@5 {
 176                                         reg = <5>;
 177                                         label = "eth_cu_1000_5";
 178                                 };
 179
 180                                 port@6 {
 181                                         reg = <6>;
 182                                         label = "eth_cu_1000_6";
 183                                 };
 184                         };
 185                 };
 186         };
 187 };
 188
 189 &i2c0 {
 190         clock-frequency = <100000>;
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_i2c0>;
 193         status = "okay";
 194
 195         gpio6: pca9505@22 {
 196                 compatible = "nxp,pca9554";
 197                 reg = <0x22>;
 198                 gpio-controller;
 199                 #gpio-cells = <2>;
 200         };
 201
 202         lm75@48 {
 203                 compatible = "national,lm75";
 204                 reg = <0x48>;
 205         };
 206
 207         at24c04@50 {
 208                 compatible = "atmel,24c04";
 209                 reg = <0x50>;
 210                 label = "nameplate";
 211         };
 212
 213         at24c04@52 {
 214                 compatible = "atmel,24c04";
 215                 reg = <0x52>;
 216         };
 217 };
 218
 219 &uart0 {
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_uart0>;
 222         status = "okay";
 223 };
 224
 225 &uart1 {
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_uart1>;
 228         status = "okay";
 229
 230         rave-sp {
 231                 compatible = "zii,rave-sp-rdu2";
 232                 current-speed = <1000000>;
 233                 #address-cells = <1>;
 234                 #size-cells = <1>;
 235
 236                 watchdog {
 237                         compatible = "zii,rave-sp-watchdog";
 238                 };
 239
 240                 eeprom@a3 {
 241                         compatible = "zii,rave-sp-eeprom";
 242                         reg = <0xa3 0x4000>;
 243                         #address-cells = <1>;
 244                         #size-cells = <1>;
 245                         zii,eeprom-name = "main-eeprom";
 246                 };
 247         };
 248 };
 249
 250 &iomuxc {
 251         pinctrl_dspi1: dspi1grp {
 252                 fsl,pins = <
 253                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 254                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 255                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 256                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 257                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 258                 >;
 259         };
 260
 261         pinctrl_esdhc0: esdhc0grp {
 262                 fsl,pins = <
 263                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 264                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 265                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 266                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 267                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 268                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 269                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 270                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 271                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 272                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 273                 >;
 274         };
 275
 276         pinctrl_esdhc1: esdhc1grp {
 277                 fsl,pins = <
 278                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 279                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 280                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 281                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 282                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 283                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 284                 >;
 285         };
 286
 287         pinctrl_fec1: fec1grp {
 288                 fsl,pins = <
 289                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 290                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 291                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 292                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 293                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 294                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 295                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 296                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 297                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 298                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 299                 >;
 300         };
 301
 302         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 303                 fsl,pins = <
 304                         VF610_PAD_PTE2__GPIO_107                0x31c2
 305                         VF610_PAD_PTB28__GPIO_98                0x219d
 306                 >;
 307         };
 308
 309         pinctrl_i2c0: i2c0grp {
 310                 fsl,pins = <
 311                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 312                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 313                 >;
 314         };
 315
 316         pinctrl_i2c1: i2c1grp {
 317                 fsl,pins = <
 318                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 319                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 320                 >;
 321         };
 322
 323         pinctrl_leds_debug: pinctrl-leds-debug {
 324                 fsl,pins = <
 325                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 326                 >;
 327         };
 328
 329         pinctrl_uart0: uart0grp {
 330                 fsl,pins = <
 331                         VF610_PAD_PTB10__UART0_TX               0x21a2
 332                         VF610_PAD_PTB11__UART0_RX               0x21a1
 333                 >;
 334         };
 335
 336         pinctrl_uart1: uart1grp {
 337                 fsl,pins = <
 338                         VF610_PAD_PTB23__UART1_TX               0x21a2
 339                         VF610_PAD_PTB24__UART1_RX               0x21a1
 340                 >;
 341         };
 342 };