arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /*
   4  * Device tree file for ZII's SSMB SPU3 board
   5  *
   6  * SSMB - SPU3 Switch Management Board
   7  * SPU - Seat Power Unit
   8  *
   9  * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
  10  *
  11  * Based on an original 'vf610-twr.dts' which is Copyright 2015,
  12  * Freescale Semiconductor, Inc.
  13  */
  14
  15 /dts-v1/;
  16 #include "vf610.dtsi"
  17
  18 / {
  19         model = "ZII VF610 SSMB SPU3 Board";
  20         compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
  21
  22         chosen {
  23                 stdout-path = &uart0;
  24         };
  25
  26         memory@80000000 {
  27                 device_type = "memory";
  28                 reg = <0x80000000 0x20000000>;
  29         };
  30
  31         gpio-leds {
  32                 compatible = "gpio-leds";
  33                 pinctrl-0 = <&pinctrl_leds_debug>;
  34                 pinctrl-names = "default";
  35
  36                 led-debug {
  37                         label = "zii:green:debug1";
  38                         gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
  39                         linux,default-trigger = "heartbeat";
  40                 };
  41         };
  42
  43         reg_vcc_3v3_mcu: regulator {
  44                 compatible = "regulator-fixed";
  45                 regulator-name = "vcc_3v3_mcu";
  46                 regulator-min-microvolt = <3300000>;
  47                 regulator-max-microvolt = <3300000>;
  48         };
  49 };
  50
  51 &adc0 {
  52         vref-supply = <&reg_vcc_3v3_mcu>;
  53         status = "okay";
  54 };
  55
  56 &adc1 {
  57         vref-supply = <&reg_vcc_3v3_mcu>;
  58         status = "okay";
  59 };
  60
  61 &dspi1 {
  62         bus-num = <1>;
  63         pinctrl-names = "default";
  64         pinctrl-0 = <&pinctrl_dspi1>;
  65         /*
  66          * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
  67          * node disabled by default and rely on bootloader to enable
  68          * it when appropriate.
  69          */
  70         status = "disabled";
  71
  72         flash@0 {
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75                 compatible = "m25p128", "jedec,spi-nor";
  76                 reg = <0>;
  77                 spi-max-frequency = <50000000>;
  78
  79                 partition@0 {
  80                         label = "m25p128-0";
  81                         reg = <0x0 0x01000000>;
  82                 };
  83         };
  84 };
  85
  86 &edma0 {
  87         status = "okay";
  88 };
  89
  90 &edma1 {
  91         status = "okay";
  92 };
  93
  94 &esdhc0 {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_esdhc0>;
  97         bus-width = <8>;
  98         non-removable;
  99         no-1-8-v;
 100         keep-power-in-suspend;
 101         no-sdio;
 102         no-sd;
 103         status = "okay";
 104 };
 105
 106 &esdhc1 {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_esdhc1>;
 109         bus-width = <4>;
 110         no-sdio;
 111         status = "okay";
 112 };
 113
 114 &fec1 {
 115         phy-mode = "rmii";
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&pinctrl_fec1>;
 118         status = "okay";
 119
 120         fixed-link {
 121                 speed = <100>;
 122                 full-duplex;
 123         };
 124
 125         mdio1: mdio {
 126                 #address-cells = <1>;
 127                 #size-cells = <0>;
 128                 status = "okay";
 129
 130                 switch0: switch0@0 {
 131                         compatible = "marvell,mv88e6190";
 132                         pinctrl-0 = <&pinctrl_gpio_switch0>;
 133                         pinctrl-names = "default";
 134                         reg = <0>;
 135                         eeprom-length = <65536>;
 136                         reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
 137                         interrupt-parent = <&gpio3>;
 138                         interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
 139                         interrupt-controller;
 140                         #interrupt-cells = <2>;
 141
 142                         ports {
 143                                 #address-cells = <1>;
 144                                 #size-cells = <0>;
 145
 146                                 port@0 {
 147                                         reg = <0>;
 148                                         label = "cpu";
 149                                         ethernet = <&fec1>;
 150
 151                                         fixed-link {
 152                                                 speed = <100>;
 153                                                 full-duplex;
 154                                         };
 155                                 };
 156
 157                                 port@1 {
 158                                         reg = <1>;
 159                                         label = "eth_cu_1000_1";
 160                                 };
 161
 162                                 port@2 {
 163                                         reg = <2>;
 164                                         label = "eth_cu_1000_2";
 165                                 };
 166
 167                                 port@3 {
 168                                         reg = <3>;
 169                                         label = "eth_cu_1000_3";
 170                                 };
 171
 172                                 port@4 {
 173                                         reg = <4>;
 174                                         label = "eth_cu_1000_4";
 175                                 };
 176
 177                                 port@5 {
 178                                         reg = <5>;
 179                                         label = "eth_cu_1000_5";
 180                                 };
 181
 182                                 port@6 {
 183                                         reg = <6>;
 184                                         label = "eth_cu_1000_6";
 185                                 };
 186                         };
 187                 };
 188         };
 189 };
 190
 191 &i2c0 {
 192         clock-frequency = <100000>;
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&pinctrl_i2c0>;
 195         status = "okay";
 196
 197         gpio6: io-expander@22 {
 198                 compatible = "nxp,pca9554";
 199                 reg = <0x22>;
 200                 gpio-controller;
 201                 #gpio-cells = <2>;
 202         };
 203
 204         lm75@48 {
 205                 compatible = "national,lm75";
 206                 reg = <0x48>;
 207         };
 208
 209         eeprom@50 {
 210                 compatible = "atmel,24c04";
 211                 reg = <0x50>;
 212                 label = "nameplate";
 213         };
 214
 215         eeprom@52 {
 216                 compatible = "atmel,24c04";
 217                 reg = <0x52>;
 218         };
 219 };
 220
 221 &snvsrtc {
 222         status = "disabled";
 223 };
 224
 225 &uart0 {
 226         pinctrl-names = "default";
 227         pinctrl-0 = <&pinctrl_uart0>;
 228         status = "okay";
 229 };
 230
 231 &uart1 {
 232         pinctrl-names = "default";
 233         pinctrl-0 = <&pinctrl_uart1>;
 234         status = "okay";
 235
 236         rave-sp {
 237                 compatible = "zii,rave-sp-rdu2";
 238                 current-speed = <1000000>;
 239                 #address-cells = <1>;
 240                 #size-cells = <1>;
 241
 242                 watchdog {
 243                         compatible = "zii,rave-sp-watchdog";
 244                 };
 245
 246                 eeprom@a3 {
 247                         compatible = "zii,rave-sp-eeprom";
 248                         reg = <0xa3 0x4000>;
 249                         #address-cells = <1>;
 250                         #size-cells = <1>;
 251                         zii,eeprom-name = "main-eeprom";
 252                 };
 253         };
 254 };
 255
 256 &wdoga5 {
 257         status = "disabled";
 258 };
 259
 260 &iomuxc {
 261         pinctrl_dspi1: dspi1grp {
 262                 fsl,pins = <
 263                         VF610_PAD_PTD5__DSPI1_CS0               0x1182
 264                         VF610_PAD_PTD4__DSPI1_CS1               0x1182
 265                         VF610_PAD_PTC6__DSPI1_SIN               0x1181
 266                         VF610_PAD_PTC7__DSPI1_SOUT              0x1182
 267                         VF610_PAD_PTC8__DSPI1_SCK               0x1182
 268                 >;
 269         };
 270
 271         pinctrl_esdhc0: esdhc0grp {
 272                 fsl,pins = <
 273                         VF610_PAD_PTC0__ESDHC0_CLK              0x31ef
 274                         VF610_PAD_PTC1__ESDHC0_CMD              0x31ef
 275                         VF610_PAD_PTC2__ESDHC0_DAT0             0x31ef
 276                         VF610_PAD_PTC3__ESDHC0_DAT1             0x31ef
 277                         VF610_PAD_PTC4__ESDHC0_DAT2             0x31ef
 278                         VF610_PAD_PTC5__ESDHC0_DAT3             0x31ef
 279                         VF610_PAD_PTD23__ESDHC0_DAT4            0x31ef
 280                         VF610_PAD_PTD22__ESDHC0_DAT5            0x31ef
 281                         VF610_PAD_PTD21__ESDHC0_DAT6            0x31ef
 282                         VF610_PAD_PTD20__ESDHC0_DAT7            0x31ef
 283                 >;
 284         };
 285
 286         pinctrl_esdhc1: esdhc1grp {
 287                 fsl,pins = <
 288                         VF610_PAD_PTA24__ESDHC1_CLK             0x31ef
 289                         VF610_PAD_PTA25__ESDHC1_CMD             0x31ef
 290                         VF610_PAD_PTA26__ESDHC1_DAT0            0x31ef
 291                         VF610_PAD_PTA27__ESDHC1_DAT1            0x31ef
 292                         VF610_PAD_PTA28__ESDHC1_DATA2           0x31ef
 293                         VF610_PAD_PTA29__ESDHC1_DAT3            0x31ef
 294                 >;
 295         };
 296
 297         pinctrl_fec1: fec1grp {
 298                 fsl,pins = <
 299                         VF610_PAD_PTA6__RMII_CLKIN              0x30d1
 300                         VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
 301                         VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
 302                         VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
 303                         VF610_PAD_PTC12__ENET_RMII1_RXD1        0x30d1
 304                         VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
 305                         VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
 306                         VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
 307                         VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
 308                         VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
 309                 >;
 310         };
 311
 312         pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
 313                 fsl,pins = <
 314                         VF610_PAD_PTE2__GPIO_107                0x31c2
 315                         VF610_PAD_PTB28__GPIO_98                0x219d
 316                 >;
 317         };
 318
 319         pinctrl_i2c0: i2c0grp {
 320                 fsl,pins = <
 321                         VF610_PAD_PTB14__I2C0_SCL               0x37ff
 322                         VF610_PAD_PTB15__I2C0_SDA               0x37ff
 323                 >;
 324         };
 325
 326         pinctrl_i2c1: i2c1grp {
 327                 fsl,pins = <
 328                         VF610_PAD_PTB16__I2C1_SCL               0x37ff
 329                         VF610_PAD_PTB17__I2C1_SDA               0x37ff
 330                 >;
 331         };
 332
 333         pinctrl_leds_debug: pinctrl-leds-debug {
 334                 fsl,pins = <
 335                         VF610_PAD_PTD3__GPIO_82                 0x31c2
 336                 >;
 337         };
 338
 339         pinctrl_uart0: uart0grp {
 340                 fsl,pins = <
 341                         VF610_PAD_PTB10__UART0_TX               0x21a2
 342                         VF610_PAD_PTB11__UART0_RX               0x21a1
 343                 >;
 344         };
 345
 346         pinctrl_uart1: uart1grp {
 347                 fsl,pins = <
 348                         VF610_PAD_PTB23__UART1_TX               0x21a2
 349                         VF610_PAD_PTB24__UART1_RX               0x21a1
 350                 >;
 351         };
 352 };