1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * CoreTile Express A15x2 A7x3
6 * Cortex-A15_A7 MPCore (V2P-CA15_A7)
12 #include "vexpress-v2m-rs1.dtsi"
15 model = "V2P-CA15_CA7";
17 arm,vexpress,site = <0xf>;
18 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
19 interrupt-parent = <&gic>;
26 serial0 = &v2m_serial0;
27 serial1 = &v2m_serial1;
28 serial2 = &v2m_serial2;
29 serial3 = &v2m_serial3;
40 compatible = "arm,cortex-a15";
42 cci-control-port = <&cci_control1>;
43 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
44 capacity-dmips-mhz = <1024>;
49 compatible = "arm,cortex-a15";
51 cci-control-port = <&cci_control1>;
52 cpu-idle-states = <&CLUSTER_SLEEP_BIG>;
53 capacity-dmips-mhz = <1024>;
58 compatible = "arm,cortex-a7";
60 cci-control-port = <&cci_control2>;
61 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
62 capacity-dmips-mhz = <516>;
67 compatible = "arm,cortex-a7";
69 cci-control-port = <&cci_control2>;
70 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
71 capacity-dmips-mhz = <516>;
76 compatible = "arm,cortex-a7";
78 cci-control-port = <&cci_control2>;
79 cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>;
80 capacity-dmips-mhz = <516>;
84 CLUSTER_SLEEP_BIG: cluster-sleep-big {
85 compatible = "arm,idle-state";
87 entry-latency-us = <1000>;
88 exit-latency-us = <700>;
89 min-residency-us = <2000>;
92 CLUSTER_SLEEP_LITTLE: cluster-sleep-little {
93 compatible = "arm,idle-state";
95 entry-latency-us = <1000>;
96 exit-latency-us = <500>;
97 min-residency-us = <2500>;
103 device_type = "memory";
104 reg = <0 0x80000000 0 0x40000000>;
108 #address-cells = <2>;
112 /* Chipselect 2 is physically at 0x18000000 */
113 vram: vram@18000000 {
114 /* 8 MB of designated video RAM */
115 compatible = "shared-dma-pool";
116 reg = <0 0x18000000 0 0x00800000>;
122 compatible = "arm,sp805", "arm,primecell";
123 reg = <0 0x2a490000 0 0x1000>;
124 interrupts = <0 98 4>;
125 clocks = <&oscclk6a>, <&oscclk6a>;
126 clock-names = "wdogclk", "apb_pclk";
130 compatible = "arm,hdlcd";
131 reg = <0 0x2b000000 0 0x1000>;
132 interrupts = <0 85 4>;
133 clocks = <&hdlcd_clk>;
134 clock-names = "pxlclk";
137 memory-controller@2b0a0000 {
138 compatible = "arm,pl341", "arm,primecell";
139 reg = <0 0x2b0a0000 0 0x1000>;
140 clocks = <&oscclk6a>;
141 clock-names = "apb_pclk";
144 gic: interrupt-controller@2c001000 {
145 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
146 #interrupt-cells = <3>;
147 #address-cells = <0>;
148 interrupt-controller;
149 reg = <0 0x2c001000 0 0x1000>,
150 <0 0x2c002000 0 0x2000>,
151 <0 0x2c004000 0 0x2000>,
152 <0 0x2c006000 0 0x2000>;
153 interrupts = <1 9 0xf04>;
157 compatible = "arm,cci-400";
158 #address-cells = <1>;
160 reg = <0 0x2c090000 0 0x1000>;
161 ranges = <0x0 0x0 0x2c090000 0x10000>;
163 cci_control1: slave-if@4000 {
164 compatible = "arm,cci-400-ctrl-if";
165 interface-type = "ace";
166 reg = <0x4000 0x1000>;
169 cci_control2: slave-if@5000 {
170 compatible = "arm,cci-400-ctrl-if";
171 interface-type = "ace";
172 reg = <0x5000 0x1000>;
176 compatible = "arm,cci-400-pmu,r0";
177 reg = <0x9000 0x5000>;
178 interrupts = <0 105 4>,
186 memory-controller@7ffd0000 {
187 compatible = "arm,pl354", "arm,primecell";
188 reg = <0 0x7ffd0000 0 0x1000>;
189 interrupts = <0 86 4>,
191 clocks = <&oscclk6a>;
192 clock-names = "apb_pclk";
196 compatible = "arm,pl330", "arm,primecell";
197 reg = <0 0x7ff00000 0 0x1000>;
198 interrupts = <0 92 4>,
203 clocks = <&oscclk6a>;
204 clock-names = "apb_pclk";
208 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
209 reg = <0 0x7fff0000 0 0x1000>;
210 interrupts = <0 95 4>;
214 compatible = "arm,armv7-timer";
215 interrupts = <1 13 0xf08>,
222 compatible = "arm,cortex-a15-pmu";
223 interrupts = <0 68 4>,
225 interrupt-affinity = <&cpu0>,
230 compatible = "arm,cortex-a7-pmu";
231 interrupts = <0 128 4>,
234 interrupt-affinity = <&cpu2>,
240 /* Reference 24MHz clock */
241 compatible = "fixed-clock";
243 clock-frequency = <24000000>;
244 clock-output-names = "oscclk6a";
248 compatible = "arm,vexpress,config-bus";
249 arm,vexpress,config-bridge = <&v2m_sysreg>;
252 /* A15 PLL 0 reference clock */
253 compatible = "arm,vexpress-osc";
254 arm,vexpress-sysreg,func = <1 0>;
255 freq-range = <17000000 50000000>;
257 clock-output-names = "oscclk0";
261 /* A15 PLL 1 reference clock */
262 compatible = "arm,vexpress-osc";
263 arm,vexpress-sysreg,func = <1 1>;
264 freq-range = <17000000 50000000>;
266 clock-output-names = "oscclk1";
270 /* A7 PLL 0 reference clock */
271 compatible = "arm,vexpress-osc";
272 arm,vexpress-sysreg,func = <1 2>;
273 freq-range = <17000000 50000000>;
275 clock-output-names = "oscclk2";
279 /* A7 PLL 1 reference clock */
280 compatible = "arm,vexpress-osc";
281 arm,vexpress-sysreg,func = <1 3>;
282 freq-range = <17000000 50000000>;
284 clock-output-names = "oscclk3";
288 /* External AXI master clock */
289 compatible = "arm,vexpress-osc";
290 arm,vexpress-sysreg,func = <1 4>;
291 freq-range = <20000000 40000000>;
293 clock-output-names = "oscclk4";
297 /* HDLCD PLL reference clock */
298 compatible = "arm,vexpress-osc";
299 arm,vexpress-sysreg,func = <1 5>;
300 freq-range = <23750000 165000000>;
302 clock-output-names = "oscclk5";
306 /* Static memory controller clock */
307 compatible = "arm,vexpress-osc";
308 arm,vexpress-sysreg,func = <1 6>;
309 freq-range = <20000000 40000000>;
311 clock-output-names = "oscclk6";
315 /* SYS PLL reference clock */
316 compatible = "arm,vexpress-osc";
317 arm,vexpress-sysreg,func = <1 7>;
318 freq-range = <17000000 50000000>;
320 clock-output-names = "oscclk7";
324 /* DDR2 PLL reference clock */
325 compatible = "arm,vexpress-osc";
326 arm,vexpress-sysreg,func = <1 8>;
327 freq-range = <20000000 50000000>;
329 clock-output-names = "oscclk8";
333 /* A15 CPU core voltage */
334 compatible = "arm,vexpress-volt";
335 arm,vexpress-sysreg,func = <2 0>;
336 regulator-name = "A15 Vcore";
337 regulator-min-microvolt = <800000>;
338 regulator-max-microvolt = <1050000>;
344 /* A7 CPU core voltage */
345 compatible = "arm,vexpress-volt";
346 arm,vexpress-sysreg,func = <2 1>;
347 regulator-name = "A7 Vcore";
348 regulator-min-microvolt = <800000>;
349 regulator-max-microvolt = <1050000>;
355 /* Total current for the two A15 cores */
356 compatible = "arm,vexpress-amp";
357 arm,vexpress-sysreg,func = <3 0>;
362 /* Total current for the three A7 cores */
363 compatible = "arm,vexpress-amp";
364 arm,vexpress-sysreg,func = <3 1>;
369 /* DCC internal temperature */
370 compatible = "arm,vexpress-temp";
371 arm,vexpress-sysreg,func = <4 0>;
376 /* Total power for the two A15 cores */
377 compatible = "arm,vexpress-power";
378 arm,vexpress-sysreg,func = <12 0>;
383 /* Total power for the three A7 cores */
384 compatible = "arm,vexpress-power";
385 arm,vexpress-sysreg,func = <12 1>;
390 /* Total energy for the two A15 cores */
391 compatible = "arm,vexpress-energy";
392 arm,vexpress-sysreg,func = <13 0>, <13 1>;
397 /* Total energy for the three A7 cores */
398 compatible = "arm,vexpress-energy";
399 arm,vexpress-sysreg,func = <13 2>, <13 3>;
405 compatible = "arm,coresight-etb10", "arm,primecell";
406 reg = <0 0x20010000 0 0x1000>;
408 clocks = <&oscclk6a>;
409 clock-names = "apb_pclk";
412 etb_in_port: endpoint {
413 remote-endpoint = <&replicator_out_port0>;
420 compatible = "arm,coresight-tpiu", "arm,primecell";
421 reg = <0 0x20030000 0 0x1000>;
423 clocks = <&oscclk6a>;
424 clock-names = "apb_pclk";
427 tpiu_in_port: endpoint {
428 remote-endpoint = <&replicator_out_port1>;
435 /* non-configurable replicators don't show up on the
436 * AMBA bus. As such no need to add "arm,primecell".
438 compatible = "arm,coresight-replicator";
441 #address-cells = <1>;
446 replicator_out_port0: endpoint {
447 remote-endpoint = <&etb_in_port>;
453 replicator_out_port1: endpoint {
454 remote-endpoint = <&tpiu_in_port>;
461 replicator_in_port0: endpoint {
462 remote-endpoint = <&funnel_out_port0>;
469 compatible = "arm,coresight-funnel", "arm,primecell";
470 reg = <0 0x20040000 0 0x1000>;
472 clocks = <&oscclk6a>;
473 clock-names = "apb_pclk";
476 funnel_out_port0: endpoint {
478 <&replicator_in_port0>;
484 #address-cells = <1>;
489 funnel_in_port0: endpoint {
490 remote-endpoint = <&ptm0_out_port>;
496 funnel_in_port1: endpoint {
497 remote-endpoint = <&ptm1_out_port>;
503 funnel_in_port2: endpoint {
504 remote-endpoint = <&etm0_out_port>;
508 /* Input port #3 is for ITM, not supported here */
512 funnel_in_port4: endpoint {
513 remote-endpoint = <&etm1_out_port>;
519 funnel_in_port5: endpoint {
520 remote-endpoint = <&etm2_out_port>;
527 compatible = "arm,coresight-etm3x", "arm,primecell";
528 reg = <0 0x2201c000 0 0x1000>;
531 clocks = <&oscclk6a>;
532 clock-names = "apb_pclk";
535 ptm0_out_port: endpoint {
536 remote-endpoint = <&funnel_in_port0>;
543 compatible = "arm,coresight-etm3x", "arm,primecell";
544 reg = <0 0x2201d000 0 0x1000>;
547 clocks = <&oscclk6a>;
548 clock-names = "apb_pclk";
551 ptm1_out_port: endpoint {
552 remote-endpoint = <&funnel_in_port1>;
559 compatible = "arm,coresight-etm3x", "arm,primecell";
560 reg = <0 0x2203c000 0 0x1000>;
563 clocks = <&oscclk6a>;
564 clock-names = "apb_pclk";
567 etm0_out_port: endpoint {
568 remote-endpoint = <&funnel_in_port2>;
575 compatible = "arm,coresight-etm3x", "arm,primecell";
576 reg = <0 0x2203d000 0 0x1000>;
579 clocks = <&oscclk6a>;
580 clock-names = "apb_pclk";
583 etm1_out_port: endpoint {
584 remote-endpoint = <&funnel_in_port4>;
591 compatible = "arm,coresight-etm3x", "arm,primecell";
592 reg = <0 0x2203e000 0 0x1000>;
595 clocks = <&oscclk6a>;
596 clock-names = "apb_pclk";
599 etm2_out_port: endpoint {
600 remote-endpoint = <&funnel_in_port5>;
607 compatible = "simple-bus";
609 #address-cells = <2>;
611 ranges = <0 0 0 0x08000000 0x04000000>,
612 <1 0 0 0x14000000 0x04000000>,
613 <2 0 0 0x18000000 0x04000000>,
614 <3 0 0 0x1c000000 0x04000000>,
615 <4 0 0 0x0c000000 0x04000000>,
616 <5 0 0 0x10000000 0x04000000>;
618 #interrupt-cells = <1>;
619 interrupt-map-mask = <0 0 63>;
620 interrupt-map = <0 0 0 &gic 0 0 4>,
630 <0 0 10 &gic 0 10 4>,
631 <0 0 11 &gic 0 11 4>,
632 <0 0 12 &gic 0 12 4>,
633 <0 0 13 &gic 0 13 4>,
634 <0 0 14 &gic 0 14 4>,
635 <0 0 15 &gic 0 15 4>,
636 <0 0 16 &gic 0 16 4>,
637 <0 0 17 &gic 0 17 4>,
638 <0 0 18 &gic 0 18 4>,
639 <0 0 19 &gic 0 19 4>,
640 <0 0 20 &gic 0 20 4>,
641 <0 0 21 &gic 0 21 4>,
642 <0 0 22 &gic 0 22 4>,
643 <0 0 23 &gic 0 23 4>,
644 <0 0 24 &gic 0 24 4>,
645 <0 0 25 &gic 0 25 4>,
646 <0 0 26 &gic 0 26 4>,
647 <0 0 27 &gic 0 27 4>,
648 <0 0 28 &gic 0 28 4>,
649 <0 0 29 &gic 0 29 4>,
650 <0 0 30 &gic 0 30 4>,
651 <0 0 31 &gic 0 31 4>,
652 <0 0 32 &gic 0 32 4>,
653 <0 0 33 &gic 0 33 4>,
654 <0 0 34 &gic 0 34 4>,
655 <0 0 35 &gic 0 35 4>,
656 <0 0 36 &gic 0 36 4>,
657 <0 0 37 &gic 0 37 4>,
658 <0 0 38 &gic 0 38 4>,
659 <0 0 39 &gic 0 39 4>,
660 <0 0 40 &gic 0 40 4>,
661 <0 0 41 &gic 0 41 4>,
662 <0 0 42 &gic 0 42 4>;
665 site2: hsb@40000000 {
666 compatible = "simple-bus";
667 #address-cells = <1>;
669 ranges = <0 0 0x40000000 0x3fef0000>;
670 #interrupt-cells = <1>;
671 interrupt-map-mask = <0 3>;
672 interrupt-map = <0 0 &gic 0 36 4>,