1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Ltd. Versatile Express
5 * CoreTile Express A15x2 (version with Test Chip 1)
6 * Cortex-A15 MPCore (V2P-CA15)
12 #include "vexpress-v2m-rs1.dtsi"
17 arm,vexpress,site = <0xf>;
18 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
19 interrupt-parent = <&gic>;
26 serial0 = &v2m_serial0;
27 serial1 = &v2m_serial1;
28 serial2 = &v2m_serial2;
29 serial3 = &v2m_serial3;
40 compatible = "arm,cortex-a15";
46 compatible = "arm,cortex-a15";
52 device_type = "memory";
53 reg = <0 0x80000000 0 0x40000000>;
61 /* Chipselect 2 is physically at 0x18000000 */
63 /* 8 MB of designated video RAM */
64 compatible = "shared-dma-pool";
65 reg = <0 0x18000000 0 0x00800000>;
71 compatible = "arm,hdlcd";
72 reg = <0 0x2b000000 0 0x1000>;
73 interrupts = <0 85 4>;
74 clocks = <&hdlcd_clk>;
75 clock-names = "pxlclk";
78 memory-controller@2b0a0000 {
79 compatible = "arm,pl341", "arm,primecell";
80 reg = <0 0x2b0a0000 0 0x1000>;
82 clock-names = "apb_pclk";
86 compatible = "arm,sp805", "arm,primecell";
88 reg = <0 0x2b060000 0 0x1000>;
89 interrupts = <0 98 4>;
90 clocks = <&sys_pll>, <&sys_pll>;
91 clock-names = "wdog_clk", "apb_pclk";
94 gic: interrupt-controller@2c001000 {
95 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
96 #interrupt-cells = <3>;
99 reg = <0 0x2c001000 0 0x1000>,
100 <0 0x2c002000 0 0x2000>,
101 <0 0x2c004000 0 0x2000>,
102 <0 0x2c006000 0 0x2000>;
103 interrupts = <1 9 0xf04>;
106 memory-controller@7ffd0000 {
107 compatible = "arm,pl354", "arm,primecell";
108 reg = <0 0x7ffd0000 0 0x1000>;
109 interrupts = <0 86 4>,
112 clock-names = "apb_pclk";
116 compatible = "arm,pl330", "arm,primecell";
117 reg = <0 0x7ffb0000 0 0x1000>;
118 interrupts = <0 92 4>,
124 clock-names = "apb_pclk";
128 compatible = "arm,armv7-timer";
129 interrupts = <1 13 0xf08>,
136 compatible = "arm,cortex-a15-pmu";
137 interrupts = <0 68 4>,
142 compatible = "arm,vexpress,config-bus";
143 arm,vexpress,config-bridge = <&v2m_sysreg>;
146 /* CPU PLL reference clock */
147 compatible = "arm,vexpress-osc";
148 arm,vexpress-sysreg,func = <1 0>;
149 freq-range = <50000000 60000000>;
151 clock-output-names = "oscclk0";
155 /* Multiplexed AXI master clock */
156 compatible = "arm,vexpress-osc";
157 arm,vexpress-sysreg,func = <1 4>;
158 freq-range = <20000000 40000000>;
160 clock-output-names = "oscclk4";
164 /* HDLCD PLL reference clock */
165 compatible = "arm,vexpress-osc";
166 arm,vexpress-sysreg,func = <1 5>;
167 freq-range = <23750000 165000000>;
169 clock-output-names = "oscclk5";
174 compatible = "arm,vexpress-osc";
175 arm,vexpress-sysreg,func = <1 6>;
176 freq-range = <20000000 50000000>;
178 clock-output-names = "oscclk6";
182 /* SYS PLL reference clock */
183 compatible = "arm,vexpress-osc";
184 arm,vexpress-sysreg,func = <1 7>;
185 freq-range = <20000000 60000000>;
187 clock-output-names = "oscclk7";
191 /* DDR2 PLL reference clock */
192 compatible = "arm,vexpress-osc";
193 arm,vexpress-sysreg,func = <1 8>;
194 freq-range = <40000000 40000000>;
196 clock-output-names = "oscclk8";
200 /* CPU core voltage */
201 compatible = "arm,vexpress-volt";
202 arm,vexpress-sysreg,func = <2 0>;
203 regulator-name = "Cores";
204 regulator-min-microvolt = <800000>;
205 regulator-max-microvolt = <1050000>;
211 /* Total current for the two cores */
212 compatible = "arm,vexpress-amp";
213 arm,vexpress-sysreg,func = <3 0>;
218 /* DCC internal temperature */
219 compatible = "arm,vexpress-temp";
220 arm,vexpress-sysreg,func = <4 0>;
226 compatible = "arm,vexpress-power";
227 arm,vexpress-sysreg,func = <12 0>;
233 compatible = "arm,vexpress-energy";
234 arm,vexpress-sysreg,func = <13 0>;
240 ranges = <0x8000000 0 0x8000000 0x18000000>;
243 site2: hsb@40000000 {
244 compatible = "simple-bus";
245 #address-cells = <1>;
247 ranges = <0 0 0x40000000 0x3fef0000>;
248 #interrupt-cells = <1>;
249 interrupt-map-mask = <0 3>;
250 interrupt-map = <0 0 &gic 0 36 4>,