2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org>
3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/arm-gic.h>
45 #include <dt-bindings/clock/sun8i-de2.h>
46 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47 #include <dt-bindings/reset/sun8i-r40-ccu.h>
48 #include <dt-bindings/reset/sun8i-de2.h>
53 interrupt-parent = <&gic>;
62 compatible = "fixed-clock";
63 clock-frequency = <24000000>;
64 clock-accuracy = <50000>;
65 clock-output-names = "osc24M";
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
72 clock-accuracy = <20000>;
73 clock-output-names = "ext-osc32k";
82 compatible = "arm,cortex-a7";
88 compatible = "arm,cortex-a7";
94 compatible = "arm,cortex-a7";
100 compatible = "arm,cortex-a7";
107 compatible = "allwinner,sun8i-r40-display-engine";
108 allwinner,pipelines = <&mixer0>, <&mixer1>;
113 compatible = "simple-bus";
114 #address-cells = <1>;
118 display_clocks: clock@1000000 {
119 compatible = "allwinner,sun8i-r40-de2-clk",
120 "allwinner,sun8i-h3-de2-clk";
121 reg = <0x01000000 0x100000>;
122 clocks = <&ccu CLK_DE>,
126 resets = <&ccu RST_BUS_DE>;
131 mixer0: mixer@1100000 {
132 compatible = "allwinner,sun8i-r40-de2-mixer-0";
133 reg = <0x01100000 0x100000>;
134 clocks = <&display_clocks CLK_BUS_MIXER0>,
135 <&display_clocks CLK_MIXER0>;
138 resets = <&display_clocks RST_MIXER0>;
141 #address-cells = <1>;
146 mixer0_out_tcon_top: endpoint {
147 remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
153 mixer1: mixer@1200000 {
154 compatible = "allwinner,sun8i-r40-de2-mixer-1";
155 reg = <0x01200000 0x100000>;
156 clocks = <&display_clocks CLK_BUS_MIXER1>,
157 <&display_clocks CLK_MIXER1>;
160 resets = <&display_clocks RST_WB>;
163 #address-cells = <1>;
168 mixer1_out_tcon_top: endpoint {
169 remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
175 nmi_intc: interrupt-controller@1c00030 {
176 compatible = "allwinner,sun7i-a20-sc-nmi";
177 interrupt-controller;
178 #interrupt-cells = <2>;
179 reg = <0x01c00030 0x0c>;
180 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
184 compatible = "allwinner,sun8i-r40-mmc",
185 "allwinner,sun50i-a64-mmc";
186 reg = <0x01c0f000 0x1000>;
187 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
188 clock-names = "ahb", "mmc";
189 resets = <&ccu RST_BUS_MMC0>;
191 pinctrl-0 = <&mmc0_pins>;
192 pinctrl-names = "default";
193 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
195 #address-cells = <1>;
200 compatible = "allwinner,sun8i-r40-mmc",
201 "allwinner,sun50i-a64-mmc";
202 reg = <0x01c10000 0x1000>;
203 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
204 clock-names = "ahb", "mmc";
205 resets = <&ccu RST_BUS_MMC1>;
207 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
214 compatible = "allwinner,sun8i-r40-emmc",
215 "allwinner,sun50i-a64-emmc";
216 reg = <0x01c11000 0x1000>;
217 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
218 clock-names = "ahb", "mmc";
219 resets = <&ccu RST_BUS_MMC2>;
221 pinctrl-0 = <&mmc2_pins>;
222 pinctrl-names = "default";
223 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
225 #address-cells = <1>;
230 compatible = "allwinner,sun8i-r40-mmc",
231 "allwinner,sun50i-a64-mmc";
232 reg = <0x01c12000 0x1000>;
233 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>;
234 clock-names = "ahb", "mmc";
235 resets = <&ccu RST_BUS_MMC3>;
237 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
239 #address-cells = <1>;
243 usbphy: phy@1c13400 {
244 compatible = "allwinner,sun8i-r40-usb-phy";
245 reg = <0x01c13400 0x14>,
249 reg-names = "phy_ctrl",
253 clocks = <&ccu CLK_USB_PHY0>,
256 clock-names = "usb0_phy",
259 resets = <&ccu RST_USB_PHY0>,
262 reset-names = "usb0_reset",
270 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
271 reg = <0x01c19000 0x100>;
272 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&ccu CLK_BUS_EHCI1>;
274 resets = <&ccu RST_BUS_EHCI1>;
281 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
282 reg = <0x01c19400 0x100>;
283 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
284 clocks = <&ccu CLK_BUS_OHCI1>,
285 <&ccu CLK_USB_OHCI1>;
286 resets = <&ccu RST_BUS_OHCI1>;
293 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
294 reg = <0x01c1c000 0x100>;
295 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
296 clocks = <&ccu CLK_BUS_EHCI2>;
297 resets = <&ccu RST_BUS_EHCI2>;
304 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci";
305 reg = <0x01c1c400 0x100>;
306 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&ccu CLK_BUS_OHCI2>,
308 <&ccu CLK_USB_OHCI2>;
309 resets = <&ccu RST_BUS_OHCI2>;
316 compatible = "allwinner,sun8i-r40-ccu";
317 reg = <0x01c20000 0x400>;
318 clocks = <&osc24M>, <&rtc 0>;
319 clock-names = "hosc", "losc";
325 compatible = "allwinner,sun8i-r40-rtc",
326 "allwinner,sun8i-h3-rtc";
327 reg = <0x01c20400 0x400>;
328 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
329 clock-output-names = "osc32k", "osc32k-out";
334 pio: pinctrl@1c20800 {
335 compatible = "allwinner,sun8i-r40-pinctrl";
336 reg = <0x01c20800 0x400>;
337 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
339 clock-names = "apb", "hosc", "losc";
341 interrupt-controller;
342 #interrupt-cells = <3>;
345 gmac_rgmii_pins: gmac-rgmii-pins {
346 pins = "PA0", "PA1", "PA2", "PA3",
347 "PA4", "PA5", "PA6", "PA7",
348 "PA8", "PA10", "PA11", "PA12",
349 "PA13", "PA15", "PA16";
352 * data lines in RGMII mode use DDR mode
353 * and need a higher signal drive strength
355 drive-strength = <40>;
358 i2c0_pins: i2c0-pins {
363 mmc0_pins: mmc0-pins {
364 pins = "PF0", "PF1", "PF2",
367 drive-strength = <30>;
371 mmc1_pg_pins: mmc1-pg-pins {
372 pins = "PG0", "PG1", "PG2",
375 drive-strength = <30>;
379 mmc2_pins: mmc2-pins {
380 pins = "PC5", "PC6", "PC7", "PC8", "PC9",
381 "PC10", "PC11", "PC12", "PC13", "PC14",
384 drive-strength = <30>;
388 uart0_pb_pins: uart0-pb-pins {
389 pins = "PB22", "PB23";
394 wdt: watchdog@1c20c90 {
395 compatible = "allwinner,sun4i-a10-wdt";
396 reg = <0x01c20c90 0x10>;
399 uart0: serial@1c28000 {
400 compatible = "snps,dw-apb-uart";
401 reg = <0x01c28000 0x400>;
402 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&ccu CLK_BUS_UART0>;
406 resets = <&ccu RST_BUS_UART0>;
410 uart1: serial@1c28400 {
411 compatible = "snps,dw-apb-uart";
412 reg = <0x01c28400 0x400>;
413 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&ccu CLK_BUS_UART1>;
417 resets = <&ccu RST_BUS_UART1>;
421 uart2: serial@1c28800 {
422 compatible = "snps,dw-apb-uart";
423 reg = <0x01c28800 0x400>;
424 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&ccu CLK_BUS_UART2>;
428 resets = <&ccu RST_BUS_UART2>;
432 uart3: serial@1c28c00 {
433 compatible = "snps,dw-apb-uart";
434 reg = <0x01c28c00 0x400>;
435 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&ccu CLK_BUS_UART3>;
439 resets = <&ccu RST_BUS_UART3>;
443 uart4: serial@1c29000 {
444 compatible = "snps,dw-apb-uart";
445 reg = <0x01c29000 0x400>;
446 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&ccu CLK_BUS_UART4>;
450 resets = <&ccu RST_BUS_UART4>;
454 uart5: serial@1c29400 {
455 compatible = "snps,dw-apb-uart";
456 reg = <0x01c29400 0x400>;
457 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&ccu CLK_BUS_UART5>;
461 resets = <&ccu RST_BUS_UART5>;
465 uart6: serial@1c29800 {
466 compatible = "snps,dw-apb-uart";
467 reg = <0x01c29800 0x400>;
468 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&ccu CLK_BUS_UART6>;
472 resets = <&ccu RST_BUS_UART6>;
476 uart7: serial@1c29c00 {
477 compatible = "snps,dw-apb-uart";
478 reg = <0x01c29c00 0x400>;
479 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&ccu CLK_BUS_UART7>;
483 resets = <&ccu RST_BUS_UART7>;
488 compatible = "allwinner,sun6i-a31-i2c";
489 reg = <0x01c2ac00 0x400>;
490 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&ccu CLK_BUS_I2C0>;
492 resets = <&ccu RST_BUS_I2C0>;
493 pinctrl-0 = <&i2c0_pins>;
494 pinctrl-names = "default";
496 #address-cells = <1>;
501 compatible = "allwinner,sun6i-a31-i2c";
502 reg = <0x01c2b000 0x400>;
503 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
504 clocks = <&ccu CLK_BUS_I2C1>;
505 resets = <&ccu RST_BUS_I2C1>;
507 #address-cells = <1>;
512 compatible = "allwinner,sun6i-a31-i2c";
513 reg = <0x01c2b400 0x400>;
514 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&ccu CLK_BUS_I2C2>;
516 resets = <&ccu RST_BUS_I2C2>;
518 #address-cells = <1>;
523 compatible = "allwinner,sun6i-a31-i2c";
524 reg = <0x01c2b800 0x400>;
525 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&ccu CLK_BUS_I2C3>;
527 resets = <&ccu RST_BUS_I2C3>;
529 #address-cells = <1>;
534 compatible = "allwinner,sun6i-a31-i2c";
535 reg = <0x01c2c000 0x400>;
536 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&ccu CLK_BUS_I2C4>;
538 resets = <&ccu RST_BUS_I2C4>;
540 #address-cells = <1>;
545 compatible = "allwinner,sun8i-r40-ahci";
546 reg = <0x01c18000 0x1000>;
547 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
549 resets = <&ccu RST_BUS_SATA>;
550 resets-name = "ahci";
551 #address-cells = <1>;
557 gmac: ethernet@1c50000 {
558 compatible = "allwinner,sun8i-r40-gmac";
560 reg = <0x01c50000 0x10000>;
561 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
562 interrupt-names = "macirq";
563 resets = <&ccu RST_BUS_GMAC>;
564 reset-names = "stmmaceth";
565 clocks = <&ccu CLK_BUS_GMAC>;
566 clock-names = "stmmaceth";
570 compatible = "snps,dwmac-mdio";
571 #address-cells = <1>;
576 tcon_top: tcon-top@1c70000 {
577 compatible = "allwinner,sun8i-r40-tcon-top";
578 reg = <0x01c70000 0x1000>;
579 clocks = <&ccu CLK_BUS_TCON_TOP>,
591 clock-output-names = "tcon-top-tv0",
594 resets = <&ccu RST_BUS_TCON_TOP>;
598 #address-cells = <1>;
601 tcon_top_mixer0_in: port@0 {
602 #address-cells = <1>;
606 tcon_top_mixer0_in_mixer0: endpoint@0 {
608 remote-endpoint = <&mixer0_out_tcon_top>;
612 tcon_top_mixer0_out: port@1 {
613 #address-cells = <1>;
617 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
621 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 {
625 tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
627 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
630 tcon_top_mixer0_out_tcon_tv1: endpoint@3 {
632 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>;
636 tcon_top_mixer1_in: port@2 {
637 #address-cells = <1>;
641 tcon_top_mixer1_in_mixer1: endpoint@1 {
643 remote-endpoint = <&mixer1_out_tcon_top>;
647 tcon_top_mixer1_out: port@3 {
648 #address-cells = <1>;
652 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
656 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 {
660 tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
662 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
665 tcon_top_mixer1_out_tcon_tv1: endpoint@3 {
667 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>;
671 tcon_top_hdmi_in: port@4 {
672 #address-cells = <1>;
676 tcon_top_hdmi_in_tcon_tv0: endpoint@0 {
678 remote-endpoint = <&tcon_tv0_out_tcon_top>;
681 tcon_top_hdmi_in_tcon_tv1: endpoint@1 {
683 remote-endpoint = <&tcon_tv1_out_tcon_top>;
687 tcon_top_hdmi_out: port@5 {
690 tcon_top_hdmi_out_hdmi: endpoint {
691 remote-endpoint = <&hdmi_in_tcon_top>;
697 tcon_tv0: lcd-controller@1c73000 {
698 compatible = "allwinner,sun8i-r40-tcon-tv";
699 reg = <0x01c73000 0x1000>;
700 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
702 clock-names = "ahb", "tcon-ch1";
703 resets = <&ccu RST_BUS_TCON_TV0>;
708 #address-cells = <1>;
711 tcon_tv0_in: port@0 {
712 #address-cells = <1>;
716 tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
718 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
721 tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
723 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
727 tcon_tv0_out: port@1 {
728 #address-cells = <1>;
732 tcon_tv0_out_tcon_top: endpoint@1 {
734 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
740 tcon_tv1: lcd-controller@1c74000 {
741 compatible = "allwinner,sun8i-r40-tcon-tv";
742 reg = <0x01c74000 0x1000>;
743 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
745 clock-names = "ahb", "tcon-ch1";
746 resets = <&ccu RST_BUS_TCON_TV1>;
751 #address-cells = <1>;
754 tcon_tv1_in: port@0 {
755 #address-cells = <1>;
759 tcon_tv1_in_tcon_top_mixer0: endpoint@0 {
761 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>;
764 tcon_tv1_in_tcon_top_mixer1: endpoint@1 {
766 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>;
770 tcon_tv1_out: port@1 {
771 #address-cells = <1>;
775 tcon_tv1_out_tcon_top: endpoint@1 {
777 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>;
783 gic: interrupt-controller@1c81000 {
784 compatible = "arm,gic-400";
785 reg = <0x01c81000 0x1000>,
789 interrupt-controller;
790 #interrupt-cells = <3>;
791 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
795 compatible = "allwinner,sun8i-r40-dw-hdmi",
796 "allwinner,sun8i-a83t-dw-hdmi";
797 reg = <0x01ee0000 0x10000>;
799 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
802 clock-names = "iahb", "isfr", "tmds";
803 resets = <&ccu RST_BUS_HDMI1>;
804 reset-names = "ctrl";
806 phy-names = "hdmi-phy";
810 #address-cells = <1>;
816 hdmi_in_tcon_top: endpoint {
817 remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
827 hdmi_phy: hdmi-phy@1ef0000 {
828 compatible = "allwinner,sun8i-r40-hdmi-phy";
829 reg = <0x01ef0000 0x10000>;
830 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
832 clock-names = "bus", "mod", "pll-0", "pll-1";
833 resets = <&ccu RST_BUS_HDMI0>;
840 compatible = "arm,armv7-timer";
841 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
842 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
843 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
844 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;