arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/dma/sun4i-a10.h>
  48 #include <dt-bindings/clock/sun7i-a20-ccu.h>
  49 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53         #address-cells = <1>;
  54         #size-cells = <1>;
  55
  56         aliases {
  57                 ethernet0 = &gmac;
  58         };
  59
  60         chosen {
  61                 #address-cells = <1>;
  62                 #size-cells = <1>;
  63                 ranges;
  64
  65                 framebuffer-lcd0-hdmi {
  66                         compatible = "allwinner,simple-framebuffer",
  67                                      "simple-framebuffer";
  68                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  69                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  70                                  <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  71                                  <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
  72                                  <&ccu CLK_HDMI>;
  73                         status = "disabled";
  74                 };
  75
  76                 framebuffer-lcd0 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  81                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
  82                                  <&ccu CLK_DRAM_DE_BE0>;
  83                         status = "disabled";
  84                 };
  85
  86                 framebuffer-lcd0-tve0 {
  87                         compatible = "allwinner,simple-framebuffer",
  88                                      "simple-framebuffer";
  89                         allwinner,pipeline = "de_be0-lcd0-tve0";
  90                         clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
  91                                  <&ccu CLK_AHB_DE_BE0>,
  92                                  <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
  93                                  <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
  94                         status = "disabled";
  95                 };
  96         };
  97
  98         cpus {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 cpu0: cpu@0 {
 103                         compatible = "arm,cortex-a7";
 104                         device_type = "cpu";
 105                         reg = <0>;
 106                         clocks = <&ccu CLK_CPU>;
 107                         clock-latency = <244144>; /* 8 32k periods */
 108                         operating-points = <
 109                                 /* kHz    uV */
 110                                 960000  1400000
 111                                 912000  1400000
 112                                 864000  1300000
 113                                 720000  1200000
 114                                 528000  1100000
 115                                 312000  1000000
 116                                 144000  1000000
 117                                 >;
 118                         #cooling-cells = <2>;
 119                 };
 120
 121                 cpu1: cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                         clocks = <&ccu CLK_CPU>;
 126                         clock-latency = <244144>; /* 8 32k periods */
 127                         operating-points = <
 128                                 /* kHz    uV */
 129                                 960000  1400000
 130                                 912000  1400000
 131                                 864000  1300000
 132                                 720000  1200000
 133                                 528000  1100000
 134                                 312000  1000000
 135                                 144000  1000000
 136                                 >;
 137                         #cooling-cells = <2>;
 138                 };
 139         };
 140
 141         thermal-zones {
 142                 cpu_thermal {
 143                         /* milliseconds */
 144                         polling-delay-passive = <250>;
 145                         polling-delay = <1000>;
 146                         thermal-sensors = <&rtp>;
 147
 148                         cooling-maps {
 149                                 map0 {
 150                                         trip = <&cpu_alert0>;
 151                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 152                                                          <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 153                                 };
 154                         };
 155
 156                         trips {
 157                                 cpu_alert0: cpu_alert0 {
 158                                         /* milliCelsius */
 159                                         temperature = <75000>;
 160                                         hysteresis = <2000>;
 161                                         type = "passive";
 162                                 };
 163
 164                                 cpu_crit: cpu_crit {
 165                                         /* milliCelsius */
 166                                         temperature = <100000>;
 167                                         hysteresis = <2000>;
 168                                         type = "critical";
 169                                 };
 170                         };
 171                 };
 172         };
 173
 174         reserved-memory {
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 ranges;
 178
 179                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 180                 default-pool {
 181                         compatible = "shared-dma-pool";
 182                         size = <0x6000000>;
 183                         alloc-ranges = <0x4a000000 0x6000000>;
 184                         reusable;
 185                         linux,cma-default;
 186                 };
 187         };
 188
 189         timer {
 190                 compatible = "arm,armv7-timer";
 191                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 193                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 194                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 195         };
 196
 197         pmu {
 198                 compatible = "arm,cortex-a7-pmu";
 199                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 200                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 201         };
 202
 203         clocks {
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 ranges;
 207
 208                 osc24M: clk-24M {
 209                         #clock-cells = <0>;
 210                         compatible = "fixed-clock";
 211                         clock-frequency = <24000000>;
 212                         clock-output-names = "osc24M";
 213                 };
 214
 215                 osc32k: clk-32k {
 216                         #clock-cells = <0>;
 217                         compatible = "fixed-clock";
 218                         clock-frequency = <32768>;
 219                         clock-output-names = "osc32k";
 220                 };
 221
 222                 /*
 223                  * The following two are dummy clocks, placeholders
 224                  * used in the gmac_tx clock. The gmac driver will
 225                  * choose one parent depending on the PHY interface
 226                  * mode, using clk_set_rate auto-reparenting.
 227                  *
 228                  * The actual TX clock rate is not controlled by the
 229                  * gmac_tx clock.
 230                  */
 231                 mii_phy_tx_clk: clk-mii-phy-tx {
 232                         #clock-cells = <0>;
 233                         compatible = "fixed-clock";
 234                         clock-frequency = <25000000>;
 235                         clock-output-names = "mii_phy_tx";
 236                 };
 237
 238                 gmac_int_tx_clk: clk-gmac-int-tx {
 239                         #clock-cells = <0>;
 240                         compatible = "fixed-clock";
 241                         clock-frequency = <125000000>;
 242                         clock-output-names = "gmac_int_tx";
 243                 };
 244
 245                 gmac_tx_clk: clk@1c20164 {
 246                         #clock-cells = <0>;
 247                         compatible = "allwinner,sun7i-a20-gmac-clk";
 248                         reg = <0x01c20164 0x4>;
 249                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 250                         clock-output-names = "gmac_tx";
 251                 };
 252         };
 253
 254
 255         de: display-engine {
 256                 compatible = "allwinner,sun7i-a20-display-engine";
 257                 allwinner,pipelines = <&fe0>, <&fe1>;
 258                 status = "disabled";
 259         };
 260
 261         soc {
 262                 compatible = "simple-bus";
 263                 #address-cells = <1>;
 264                 #size-cells = <1>;
 265                 ranges;
 266
 267                 system-control@1c00000 {
 268                         compatible = "allwinner,sun7i-a20-system-control",
 269                                      "allwinner,sun4i-a10-system-control";
 270                         reg = <0x01c00000 0x30>;
 271                         #address-cells = <1>;
 272                         #size-cells = <1>;
 273                         ranges;
 274
 275                         sram_a: sram@0 {
 276                                 compatible = "mmio-sram";
 277                                 reg = <0x00000000 0xc000>;
 278                                 #address-cells = <1>;
 279                                 #size-cells = <1>;
 280                                 ranges = <0 0x00000000 0xc000>;
 281
 282                                 emac_sram: sram-section@8000 {
 283                                         compatible = "allwinner,sun7i-a20-sram-a3-a4",
 284                                                      "allwinner,sun4i-a10-sram-a3-a4";
 285                                         reg = <0x8000 0x4000>;
 286                                         status = "disabled";
 287                                 };
 288                         };
 289
 290                         sram_d: sram@10000 {
 291                                 compatible = "mmio-sram";
 292                                 reg = <0x00010000 0x1000>;
 293                                 #address-cells = <1>;
 294                                 #size-cells = <1>;
 295                                 ranges = <0 0x00010000 0x1000>;
 296
 297                                 otg_sram: sram-section@0 {
 298                                         compatible = "allwinner,sun7i-a20-sram-d",
 299                                                      "allwinner,sun4i-a10-sram-d";
 300                                         reg = <0x0000 0x1000>;
 301                                         status = "disabled";
 302                                 };
 303                         };
 304
 305                         sram_c: sram@1d00000 {
 306                                 compatible = "mmio-sram";
 307                                 reg = <0x01d00000 0xd0000>;
 308                                 #address-cells = <1>;
 309                                 #size-cells = <1>;
 310                                 ranges = <0 0x01d00000 0xd0000>;
 311
 312                                 ve_sram: sram-section@0 {
 313                                         compatible = "allwinner,sun7i-a20-sram-c1",
 314                                                      "allwinner,sun4i-a10-sram-c1";
 315                                         reg = <0x000000 0x80000>;
 316                                 };
 317                         };
 318                 };
 319
 320                 nmi_intc: interrupt-controller@1c00030 {
 321                         compatible = "allwinner,sun7i-a20-sc-nmi";
 322                         interrupt-controller;
 323                         #interrupt-cells = <2>;
 324                         reg = <0x01c00030 0x0c>;
 325                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 326                 };
 327
 328                 dma: dma-controller@1c02000 {
 329                         compatible = "allwinner,sun4i-a10-dma";
 330                         reg = <0x01c02000 0x1000>;
 331                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 332                         clocks = <&ccu CLK_AHB_DMA>;
 333                         #dma-cells = <2>;
 334                 };
 335
 336                 nfc: nand-controller@1c03000 {
 337                         compatible = "allwinner,sun4i-a10-nand";
 338                         reg = <0x01c03000 0x1000>;
 339                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 341                         clock-names = "ahb", "mod";
 342                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 343                         dma-names = "rxtx";
 344                         status = "disabled";
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                 };
 348
 349                 spi0: spi@1c05000 {
 350                         compatible = "allwinner,sun4i-a10-spi";
 351                         reg = <0x01c05000 0x1000>;
 352                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 353                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 354                         clock-names = "ahb", "mod";
 355                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 356                                <&dma SUN4I_DMA_DEDICATED 26>;
 357                         dma-names = "rx", "tx";
 358                         status = "disabled";
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         num-cs = <4>;
 362                 };
 363
 364                 spi1: spi@1c06000 {
 365                         compatible = "allwinner,sun4i-a10-spi";
 366                         reg = <0x01c06000 0x1000>;
 367                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 368                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 369                         clock-names = "ahb", "mod";
 370                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 371                                <&dma SUN4I_DMA_DEDICATED 8>;
 372                         dma-names = "rx", "tx";
 373                         status = "disabled";
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         num-cs = <1>;
 377                 };
 378
 379                 emac: ethernet@1c0b000 {
 380                         compatible = "allwinner,sun4i-a10-emac";
 381                         reg = <0x01c0b000 0x1000>;
 382                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&ccu CLK_AHB_EMAC>;
 384                         allwinner,sram = <&emac_sram 1>;
 385                         status = "disabled";
 386                 };
 387
 388                 mdio: mdio@1c0b080 {
 389                         compatible = "allwinner,sun4i-a10-mdio";
 390                         reg = <0x01c0b080 0x14>;
 391                         status = "disabled";
 392                         #address-cells = <1>;
 393                         #size-cells = <0>;
 394                 };
 395
 396                 tcon0: lcd-controller@1c0c000 {
 397                         compatible = "allwinner,sun7i-a20-tcon";
 398                         reg = <0x01c0c000 0x1000>;
 399                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 400                         resets = <&ccu RST_TCON0>;
 401                         reset-names = "lcd";
 402                         clocks = <&ccu CLK_AHB_LCD0>,
 403                                  <&ccu CLK_TCON0_CH0>,
 404                                  <&ccu CLK_TCON0_CH1>;
 405                         clock-names = "ahb",
 406                                       "tcon-ch0",
 407                                       "tcon-ch1";
 408                         clock-output-names = "tcon0-pixel-clock";
 409                         #clock-cells = <0>;
 410                         dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 411
 412                         ports {
 413                                 #address-cells = <1>;
 414                                 #size-cells = <0>;
 415
 416                                 tcon0_in: port@0 {
 417                                         #address-cells = <1>;
 418                                         #size-cells = <0>;
 419                                         reg = <0>;
 420
 421                                         tcon0_in_be0: endpoint@0 {
 422                                                 reg = <0>;
 423                                                 remote-endpoint = <&be0_out_tcon0>;
 424                                         };
 425
 426                                         tcon0_in_be1: endpoint@1 {
 427                                                 reg = <1>;
 428                                                 remote-endpoint = <&be1_out_tcon0>;
 429                                         };
 430                                 };
 431
 432                                 tcon0_out: port@1 {
 433                                         #address-cells = <1>;
 434                                         #size-cells = <0>;
 435                                         reg = <1>;
 436
 437                                         tcon0_out_hdmi: endpoint@1 {
 438                                                 reg = <1>;
 439                                                 remote-endpoint = <&hdmi_in_tcon0>;
 440                                                 allwinner,tcon-channel = <1>;
 441                                         };
 442                                 };
 443                         };
 444                 };
 445
 446                 tcon1: lcd-controller@1c0d000 {
 447                         compatible = "allwinner,sun7i-a20-tcon";
 448                         reg = <0x01c0d000 0x1000>;
 449                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 450                         resets = <&ccu RST_TCON1>;
 451                         reset-names = "lcd";
 452                         clocks = <&ccu CLK_AHB_LCD1>,
 453                                  <&ccu CLK_TCON1_CH0>,
 454                                  <&ccu CLK_TCON1_CH1>;
 455                         clock-names = "ahb",
 456                                       "tcon-ch0",
 457                                       "tcon-ch1";
 458                         clock-output-names = "tcon1-pixel-clock";
 459                         #clock-cells = <0>;
 460                         dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 461
 462                         ports {
 463                                 #address-cells = <1>;
 464                                 #size-cells = <0>;
 465
 466                                 tcon1_in: port@0 {
 467                                         #address-cells = <1>;
 468                                         #size-cells = <0>;
 469                                         reg = <0>;
 470
 471                                         tcon1_in_be0: endpoint@0 {
 472                                                 reg = <0>;
 473                                                 remote-endpoint = <&be0_out_tcon1>;
 474                                         };
 475
 476                                         tcon1_in_be1: endpoint@1 {
 477                                                 reg = <1>;
 478                                                 remote-endpoint = <&be1_out_tcon1>;
 479                                         };
 480                                 };
 481
 482                                 tcon1_out: port@1 {
 483                                         #address-cells = <1>;
 484                                         #size-cells = <0>;
 485                                         reg = <1>;
 486
 487                                         tcon1_out_hdmi: endpoint@1 {
 488                                                 reg = <1>;
 489                                                 remote-endpoint = <&hdmi_in_tcon1>;
 490                                                 allwinner,tcon-channel = <1>;
 491                                         };
 492                                 };
 493                         };
 494                 };
 495
 496                 video-codec@1c0e000 {
 497                         compatible = "allwinner,sun7i-a20-video-engine";
 498                         reg = <0x01c0e000 0x1000>;
 499                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 500                                  <&ccu CLK_DRAM_VE>;
 501                         clock-names = "ahb", "mod", "ram";
 502                         resets = <&ccu RST_VE>;
 503                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 504                         allwinner,sram = <&ve_sram 1>;
 505                 };
 506
 507                 mmc0: mmc@1c0f000 {
 508                         compatible = "allwinner,sun7i-a20-mmc";
 509                         reg = <0x01c0f000 0x1000>;
 510                         clocks = <&ccu CLK_AHB_MMC0>,
 511                                  <&ccu CLK_MMC0>,
 512                                  <&ccu CLK_MMC0_OUTPUT>,
 513                                  <&ccu CLK_MMC0_SAMPLE>;
 514                         clock-names = "ahb",
 515                                       "mmc",
 516                                       "output",
 517                                       "sample";
 518                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 519                         pinctrl-names = "default";
 520                         pinctrl-0 = <&mmc0_pins>;
 521                         status = "disabled";
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                 };
 525
 526                 mmc1: mmc@1c10000 {
 527                         compatible = "allwinner,sun7i-a20-mmc";
 528                         reg = <0x01c10000 0x1000>;
 529                         clocks = <&ccu CLK_AHB_MMC1>,
 530                                  <&ccu CLK_MMC1>,
 531                                  <&ccu CLK_MMC1_OUTPUT>,
 532                                  <&ccu CLK_MMC1_SAMPLE>;
 533                         clock-names = "ahb",
 534                                       "mmc",
 535                                       "output",
 536                                       "sample";
 537                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 538                         status = "disabled";
 539                         #address-cells = <1>;
 540                         #size-cells = <0>;
 541                 };
 542
 543                 mmc2: mmc@1c11000 {
 544                         compatible = "allwinner,sun7i-a20-mmc";
 545                         reg = <0x01c11000 0x1000>;
 546                         clocks = <&ccu CLK_AHB_MMC2>,
 547                                  <&ccu CLK_MMC2>,
 548                                  <&ccu CLK_MMC2_OUTPUT>,
 549                                  <&ccu CLK_MMC2_SAMPLE>;
 550                         clock-names = "ahb",
 551                                       "mmc",
 552                                       "output",
 553                                       "sample";
 554                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 555                         pinctrl-names = "default";
 556                         pinctrl-0 = <&mmc2_pins>;
 557                         status = "disabled";
 558                         #address-cells = <1>;
 559                         #size-cells = <0>;
 560                 };
 561
 562                 mmc3: mmc@1c12000 {
 563                         compatible = "allwinner,sun7i-a20-mmc";
 564                         reg = <0x01c12000 0x1000>;
 565                         clocks = <&ccu CLK_AHB_MMC3>,
 566                                  <&ccu CLK_MMC3>,
 567                                  <&ccu CLK_MMC3_OUTPUT>,
 568                                  <&ccu CLK_MMC3_SAMPLE>;
 569                         clock-names = "ahb",
 570                                       "mmc",
 571                                       "output",
 572                                       "sample";
 573                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 574                         pinctrl-names = "default";
 575                         pinctrl-0 = <&mmc3_pins>;
 576                         status = "disabled";
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                 };
 580
 581                 usb_otg: usb@1c13000 {
 582                         compatible = "allwinner,sun4i-a10-musb";
 583                         reg = <0x01c13000 0x0400>;
 584                         clocks = <&ccu CLK_AHB_OTG>;
 585                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 586                         interrupt-names = "mc";
 587                         phys = <&usbphy 0>;
 588                         phy-names = "usb";
 589                         extcon = <&usbphy 0>;
 590                         allwinner,sram = <&otg_sram 1>;
 591                         dr_mode = "otg";
 592                         status = "disabled";
 593                 };
 594
 595                 usbphy: phy@1c13400 {
 596                         #phy-cells = <1>;
 597                         compatible = "allwinner,sun7i-a20-usb-phy";
 598                         reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 599                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 600                         clocks = <&ccu CLK_USB_PHY>;
 601                         clock-names = "usb_phy";
 602                         resets = <&ccu RST_USB_PHY0>,
 603                                  <&ccu RST_USB_PHY1>,
 604                                  <&ccu RST_USB_PHY2>;
 605                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 606                         status = "disabled";
 607                 };
 608
 609                 ehci0: usb@1c14000 {
 610                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 611                         reg = <0x01c14000 0x100>;
 612                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&ccu CLK_AHB_EHCI0>;
 614                         phys = <&usbphy 1>;
 615                         status = "disabled";
 616                 };
 617
 618                 ohci0: usb@1c14400 {
 619                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 620                         reg = <0x01c14400 0x100>;
 621                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 622                         clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 623                         phys = <&usbphy 1>;
 624                         status = "disabled";
 625                 };
 626
 627                 crypto: crypto-engine@1c15000 {
 628                         compatible = "allwinner,sun7i-a20-crypto",
 629                                      "allwinner,sun4i-a10-crypto";
 630                         reg = <0x01c15000 0x1000>;
 631                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 633                         clock-names = "ahb", "mod";
 634                 };
 635
 636                 hdmi: hdmi@1c16000 {
 637                         compatible = "allwinner,sun7i-a20-hdmi",
 638                                      "allwinner,sun5i-a10s-hdmi";
 639                         reg = <0x01c16000 0x1000>;
 640                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 641                         clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 642                                  <&ccu CLK_PLL_VIDEO0_2X>,
 643                                  <&ccu CLK_PLL_VIDEO1_2X>;
 644                         clock-names = "ahb", "mod", "pll-0", "pll-1";
 645                         dmas = <&dma SUN4I_DMA_NORMAL 16>,
 646                                <&dma SUN4I_DMA_NORMAL 16>,
 647                                <&dma SUN4I_DMA_DEDICATED 24>;
 648                         dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 649                         status = "disabled";
 650
 651                         ports {
 652                                 #address-cells = <1>;
 653                                 #size-cells = <0>;
 654
 655                                 hdmi_in: port@0 {
 656                                         #address-cells = <1>;
 657                                         #size-cells = <0>;
 658                                         reg = <0>;
 659
 660                                         hdmi_in_tcon0: endpoint@0 {
 661                                                 reg = <0>;
 662                                                 remote-endpoint = <&tcon0_out_hdmi>;
 663                                         };
 664
 665                                         hdmi_in_tcon1: endpoint@1 {
 666                                                 reg = <1>;
 667                                                 remote-endpoint = <&tcon1_out_hdmi>;
 668                                         };
 669                                 };
 670
 671                                 hdmi_out: port@1 {
 672                                         reg = <1>;
 673                                 };
 674                         };
 675                 };
 676
 677                 spi2: spi@1c17000 {
 678                         compatible = "allwinner,sun4i-a10-spi";
 679                         reg = <0x01c17000 0x1000>;
 680                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 681                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 682                         clock-names = "ahb", "mod";
 683                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 684                                <&dma SUN4I_DMA_DEDICATED 28>;
 685                         dma-names = "rx", "tx";
 686                         status = "disabled";
 687                         #address-cells = <1>;
 688                         #size-cells = <0>;
 689                         num-cs = <1>;
 690                 };
 691
 692                 ahci: sata@1c18000 {
 693                         compatible = "allwinner,sun4i-a10-ahci";
 694                         reg = <0x01c18000 0x1000>;
 695                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 696                         clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 697                         status = "disabled";
 698                 };
 699
 700                 ehci1: usb@1c1c000 {
 701                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 702                         reg = <0x01c1c000 0x100>;
 703                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 704                         clocks = <&ccu CLK_AHB_EHCI1>;
 705                         phys = <&usbphy 2>;
 706                         status = "disabled";
 707                 };
 708
 709                 ohci1: usb@1c1c400 {
 710                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 711                         reg = <0x01c1c400 0x100>;
 712                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 713                         clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 714                         phys = <&usbphy 2>;
 715                         status = "disabled";
 716                 };
 717
 718                 spi3: spi@1c1f000 {
 719                         compatible = "allwinner,sun4i-a10-spi";
 720                         reg = <0x01c1f000 0x1000>;
 721                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 722                         clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 723                         clock-names = "ahb", "mod";
 724                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 725                                <&dma SUN4I_DMA_DEDICATED 30>;
 726                         dma-names = "rx", "tx";
 727                         status = "disabled";
 728                         #address-cells = <1>;
 729                         #size-cells = <0>;
 730                         num-cs = <1>;
 731                 };
 732
 733                 ccu: clock@1c20000 {
 734                         compatible = "allwinner,sun7i-a20-ccu";
 735                         reg = <0x01c20000 0x400>;
 736                         clocks = <&osc24M>, <&osc32k>;
 737                         clock-names = "hosc", "losc";
 738                         #clock-cells = <1>;
 739                         #reset-cells = <1>;
 740                 };
 741
 742                 pio: pinctrl@1c20800 {
 743                         compatible = "allwinner,sun7i-a20-pinctrl";
 744                         reg = <0x01c20800 0x400>;
 745                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 746                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 747                         clock-names = "apb", "hosc", "losc";
 748                         gpio-controller;
 749                         interrupt-controller;
 750                         #interrupt-cells = <3>;
 751                         #gpio-cells = <3>;
 752
 753                         /omit-if-no-ref/
 754                         can_pa_pins: can-pa-pins {
 755                                 pins = "PA16", "PA17";
 756                                 function = "can";
 757                         };
 758
 759                         /omit-if-no-ref/
 760                         can_ph_pins: can-ph-pins {
 761                                 pins = "PH20", "PH21";
 762                                 function = "can";
 763                         };
 764
 765                         /omit-if-no-ref/
 766                         clk_out_a_pin: clk-out-a-pin {
 767                                 pins = "PI12";
 768                                 function = "clk_out_a";
 769                         };
 770
 771                         /omit-if-no-ref/
 772                         clk_out_b_pin: clk-out-b-pin {
 773                                 pins = "PI13";
 774                                 function = "clk_out_b";
 775                         };
 776
 777                         /omit-if-no-ref/
 778                         emac_pa_pins: emac-pa-pins {
 779                                 pins = "PA0", "PA1", "PA2",
 780                                        "PA3", "PA4", "PA5", "PA6",
 781                                        "PA7", "PA8", "PA9", "PA10",
 782                                        "PA11", "PA12", "PA13", "PA14",
 783                                        "PA15", "PA16";
 784                                 function = "emac";
 785                         };
 786
 787                         /omit-if-no-ref/
 788                         emac_ph_pins: emac-ph-pins {
 789                                 pins = "PH8", "PH9", "PH10", "PH11",
 790                                        "PH14", "PH15", "PH16", "PH17",
 791                                        "PH18", "PH19", "PH20", "PH21",
 792                                        "PH22", "PH23", "PH24", "PH25",
 793                                        "PH26";
 794                                 function = "emac";
 795                         };
 796
 797                         /omit-if-no-ref/
 798                         gmac_mii_pins: gmac-mii-pins {
 799                                 pins = "PA0", "PA1", "PA2",
 800                                        "PA3", "PA4", "PA5", "PA6",
 801                                        "PA7", "PA8", "PA9", "PA10",
 802                                        "PA11", "PA12", "PA13", "PA14",
 803                                        "PA15", "PA16";
 804                                 function = "gmac";
 805                         };
 806
 807                         /omit-if-no-ref/
 808                         gmac_rgmii_pins: gmac-rgmii-pins {
 809                                 pins = "PA0", "PA1", "PA2",
 810                                        "PA3", "PA4", "PA5", "PA6",
 811                                         "PA7", "PA8", "PA10",
 812                                        "PA11", "PA12", "PA13",
 813                                        "PA15", "PA16";
 814                                 function = "gmac";
 815                                 /*
 816                                  * data lines in RGMII mode use DDR mode
 817                                  * and need a higher signal drive strength
 818                                  */
 819                                 drive-strength = <40>;
 820                         };
 821
 822                         /omit-if-no-ref/
 823                         i2c0_pins: i2c0-pins {
 824                                 pins = "PB0", "PB1";
 825                                 function = "i2c0";
 826                         };
 827
 828                         /omit-if-no-ref/
 829                         i2c1_pins: i2c1-pins {
 830                                 pins = "PB18", "PB19";
 831                                 function = "i2c1";
 832                         };
 833
 834                         /omit-if-no-ref/
 835                         i2c2_pins: i2c2-pins {
 836                                 pins = "PB20", "PB21";
 837                                 function = "i2c2";
 838                         };
 839
 840                         /omit-if-no-ref/
 841                         i2c3_pins: i2c3-pins {
 842                                 pins = "PI0", "PI1";
 843                                 function = "i2c3";
 844                         };
 845
 846                         /omit-if-no-ref/
 847                         ir0_rx_pin: ir0-rx-pin {
 848                                 pins = "PB4";
 849                                 function = "ir0";
 850                         };
 851
 852                         /omit-if-no-ref/
 853                         ir0_tx_pin: ir0-tx-pin {
 854                                 pins = "PB3";
 855                                 function = "ir0";
 856                         };
 857
 858                         /omit-if-no-ref/
 859                         ir1_rx_pin: ir1-rx-pin {
 860                                 pins = "PB23";
 861                                 function = "ir1";
 862                         };
 863
 864                         /omit-if-no-ref/
 865                         ir1_tx_pin: ir1-tx-pin {
 866                                 pins = "PB22";
 867                                 function = "ir1";
 868                         };
 869
 870                         /omit-if-no-ref/
 871                         mmc0_pins: mmc0-pins {
 872                                 pins = "PF0", "PF1", "PF2",
 873                                        "PF3", "PF4", "PF5";
 874                                 function = "mmc0";
 875                                 drive-strength = <30>;
 876                                 bias-pull-up;
 877                         };
 878
 879                         /omit-if-no-ref/
 880                         mmc2_pins: mmc2-pins {
 881                                 pins = "PC6", "PC7", "PC8",
 882                                        "PC9", "PC10", "PC11";
 883                                 function = "mmc2";
 884                                 drive-strength = <30>;
 885                                 bias-pull-up;
 886                         };
 887
 888                         /omit-if-no-ref/
 889                         mmc3_pins: mmc3-pins {
 890                                 pins = "PI4", "PI5", "PI6",
 891                                        "PI7", "PI8", "PI9";
 892                                 function = "mmc3";
 893                                 drive-strength = <30>;
 894                                 bias-pull-up;
 895                         };
 896
 897                         /omit-if-no-ref/
 898                         ps2_0_pins: ps2-0-pins {
 899                                 pins = "PI20", "PI21";
 900                                 function = "ps2";
 901                         };
 902
 903                         /omit-if-no-ref/
 904                         ps2_1_ph_pins: ps2-1-ph-pins {
 905                                 pins = "PH12", "PH13";
 906                                 function = "ps2";
 907                         };
 908
 909                         /omit-if-no-ref/
 910                         pwm0_pin: pwm0-pin {
 911                                 pins = "PB2";
 912                                 function = "pwm";
 913                         };
 914
 915                         /omit-if-no-ref/
 916                         pwm1_pin: pwm1-pin {
 917                                 pins = "PI3";
 918                                 function = "pwm";
 919                         };
 920
 921                         /omit-if-no-ref/
 922                         spdif_tx_pin: spdif-tx-pin {
 923                                 pins = "PB13";
 924                                 function = "spdif";
 925                                 bias-pull-up;
 926                         };
 927
 928                         /omit-if-no-ref/
 929                         spi0_pi_pins: spi0-pi-pins {
 930                                 pins = "PI11", "PI12", "PI13";
 931                                 function = "spi0";
 932                         };
 933
 934                         /omit-if-no-ref/
 935                         spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 936                                 pins = "PI10";
 937                                 function = "spi0";
 938                         };
 939
 940                         /omit-if-no-ref/
 941                         spi0_cs1_pi_pin: spi0-cs1-pi-pin {
 942                                 pins = "PI14";
 943                                 function = "spi0";
 944                         };
 945
 946                         /omit-if-no-ref/
 947                         spi1_pi_pins: spi1-pi-pins {
 948                                 pins = "PI17", "PI18", "PI19";
 949                                 function = "spi1";
 950                         };
 951
 952                         /omit-if-no-ref/
 953                         spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 954                                 pins = "PI16";
 955                                 function = "spi1";
 956                         };
 957
 958                         /omit-if-no-ref/
 959                         spi2_pb_pins: spi2-pb-pins {
 960                                 pins = "PB15", "PB16", "PB17";
 961                                 function = "spi2";
 962                         };
 963
 964                         /omit-if-no-ref/
 965                         spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 966                                 pins = "PB14";
 967                                 function = "spi2";
 968                         };
 969
 970                         /omit-if-no-ref/
 971                         spi2_pc_pins: spi2-pc-pins {
 972                                 pins = "PC20", "PC21", "PC22";
 973                                 function = "spi2";
 974                         };
 975
 976                         /omit-if-no-ref/
 977                         spi2_cs0_pc_pin: spi2-cs0-pc-pin {
 978                                 pins = "PC19";
 979                                 function = "spi2";
 980                         };
 981
 982                         /omit-if-no-ref/
 983                         uart0_pb_pins: uart0-pb-pins {
 984                                 pins = "PB22", "PB23";
 985                                 function = "uart0";
 986                         };
 987
 988                         /omit-if-no-ref/
 989                         uart0_pf_pins: uart0-pf-pins {
 990                                 pins = "PF2", "PF4";
 991                                 function = "uart0";
 992                         };
 993
 994                         /omit-if-no-ref/
 995                         uart1_pa_pins: uart1-pa-pins {
 996                                 pins = "PA10", "PA11";
 997                                 function = "uart1";
 998                         };
 999
1000                         /omit-if-no-ref/
1001                         uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1002                                 pins = "PA12", "PA13";
1003                                 function = "uart1";
1004                         };
1005
1006                         /omit-if-no-ref/
1007                         uart2_pa_pins: uart2-pa-pins {
1008                                 pins = "PA2", "PA3";
1009                                 function = "uart2";
1010                         };
1011
1012                         /omit-if-no-ref/
1013                         uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1014                                 pins = "PA0", "PA1";
1015                                 function = "uart2";
1016                         };
1017
1018                         /omit-if-no-ref/
1019                         uart2_pi_pins: uart2-pi-pins {
1020                                 pins = "PI18", "PI19";
1021                                 function = "uart2";
1022                         };
1023
1024                         /omit-if-no-ref/
1025                         uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1026                                 pins = "PI16", "PI17";
1027                                 function = "uart2";
1028                         };
1029
1030                         /omit-if-no-ref/
1031                         uart3_pg_pins: uart3-pg-pins {
1032                                 pins = "PG6", "PG7";
1033                                 function = "uart3";
1034                         };
1035
1036                         /omit-if-no-ref/
1037                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1038                                 pins = "PG8", "PG9";
1039                                 function = "uart3";
1040                         };
1041
1042                         /omit-if-no-ref/
1043                         uart3_ph_pins: uart3-ph-pins {
1044                                 pins = "PH0", "PH1";
1045                                 function = "uart3";
1046                         };
1047
1048                         /omit-if-no-ref/
1049                         uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1050                                 pins = "PH2", "PH3";
1051                                 function = "uart3";
1052                         };
1053
1054                         /omit-if-no-ref/
1055                         uart4_pg_pins: uart4-pg-pins {
1056                                 pins = "PG10", "PG11";
1057                                 function = "uart4";
1058                         };
1059
1060                         /omit-if-no-ref/
1061                         uart4_ph_pins: uart4-ph-pins {
1062                                 pins = "PH4", "PH5";
1063                                 function = "uart4";
1064                         };
1065
1066                         /omit-if-no-ref/
1067                         uart5_ph_pins: uart5-ph-pins {
1068                                 pins = "PH6", "PH7";
1069                                 function = "uart5";
1070                         };
1071
1072                         /omit-if-no-ref/
1073                         uart5_pi_pins: uart5-pi-pins {
1074                                 pins = "PI10", "PI11";
1075                                 function = "uart5";
1076                         };
1077
1078                         /omit-if-no-ref/
1079                         uart6_pa_pins: uart6-pa-pins {
1080                                 pins = "PA12", "PA13";
1081                                 function = "uart6";
1082                         };
1083
1084                         /omit-if-no-ref/
1085                         uart6_pi_pins: uart6-pi-pins {
1086                                 pins = "PI12", "PI13";
1087                                 function = "uart6";
1088                         };
1089
1090                         /omit-if-no-ref/
1091                         uart7_pa_pins: uart7-pa-pins {
1092                                 pins = "PA14", "PA15";
1093                                 function = "uart7";
1094                         };
1095
1096                         /omit-if-no-ref/
1097                         uart7_pi_pins: uart7-pi-pins {
1098                                 pins = "PI20", "PI21";
1099                                 function = "uart7";
1100                         };
1101                 };
1102
1103                 timer@1c20c00 {
1104                         compatible = "allwinner,sun4i-a10-timer";
1105                         reg = <0x01c20c00 0x90>;
1106                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1107                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1108                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1109                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1110                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1111                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1112                         clocks = <&osc24M>;
1113                 };
1114
1115                 wdt: watchdog@1c20c90 {
1116                         compatible = "allwinner,sun4i-a10-wdt";
1117                         reg = <0x01c20c90 0x10>;
1118                 };
1119
1120                 rtc: rtc@1c20d00 {
1121                         compatible = "allwinner,sun7i-a20-rtc";
1122                         reg = <0x01c20d00 0x20>;
1123                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1124                 };
1125
1126                 pwm: pwm@1c20e00 {
1127                         compatible = "allwinner,sun7i-a20-pwm";
1128                         reg = <0x01c20e00 0xc>;
1129                         clocks = <&osc24M>;
1130                         #pwm-cells = <3>;
1131                         status = "disabled";
1132                 };
1133
1134                 spdif: spdif@1c21000 {
1135                         #sound-dai-cells = <0>;
1136                         compatible = "allwinner,sun4i-a10-spdif";
1137                         reg = <0x01c21000 0x400>;
1138                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1139                         clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1140                         clock-names = "apb", "spdif";
1141                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1142                                <&dma SUN4I_DMA_NORMAL 2>;
1143                         dma-names = "rx", "tx";
1144                         status = "disabled";
1145                 };
1146
1147                 ir0: ir@1c21800 {
1148                         compatible = "allwinner,sun4i-a10-ir";
1149                         clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1150                         clock-names = "apb", "ir";
1151                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1152                         reg = <0x01c21800 0x40>;
1153                         status = "disabled";
1154                 };
1155
1156                 ir1: ir@1c21c00 {
1157                         compatible = "allwinner,sun4i-a10-ir";
1158                         clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1159                         clock-names = "apb", "ir";
1160                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1161                         reg = <0x01c21c00 0x40>;
1162                         status = "disabled";
1163                 };
1164
1165                 i2s1: i2s@1c22000 {
1166                         #sound-dai-cells = <0>;
1167                         compatible = "allwinner,sun4i-a10-i2s";
1168                         reg = <0x01c22000 0x400>;
1169                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1170                         clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1171                         clock-names = "apb", "mod";
1172                         dmas = <&dma SUN4I_DMA_NORMAL 4>,
1173                                <&dma SUN4I_DMA_NORMAL 4>;
1174                         dma-names = "rx", "tx";
1175                         status = "disabled";
1176                 };
1177
1178                 i2s0: i2s@1c22400 {
1179                         #sound-dai-cells = <0>;
1180                         compatible = "allwinner,sun4i-a10-i2s";
1181                         reg = <0x01c22400 0x400>;
1182                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1183                         clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1184                         clock-names = "apb", "mod";
1185                         dmas = <&dma SUN4I_DMA_NORMAL 3>,
1186                                <&dma SUN4I_DMA_NORMAL 3>;
1187                         dma-names = "rx", "tx";
1188                         status = "disabled";
1189                 };
1190
1191                 lradc: lradc@1c22800 {
1192                         compatible = "allwinner,sun4i-a10-lradc-keys";
1193                         reg = <0x01c22800 0x100>;
1194                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1195                         status = "disabled";
1196                 };
1197
1198                 codec: codec@1c22c00 {
1199                         #sound-dai-cells = <0>;
1200                         compatible = "allwinner,sun7i-a20-codec";
1201                         reg = <0x01c22c00 0x40>;
1202                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1203                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1204                         clock-names = "apb", "codec";
1205                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1206                                <&dma SUN4I_DMA_NORMAL 19>;
1207                         dma-names = "rx", "tx";
1208                         status = "disabled";
1209                 };
1210
1211                 sid: eeprom@1c23800 {
1212                         compatible = "allwinner,sun7i-a20-sid";
1213                         reg = <0x01c23800 0x200>;
1214                 };
1215
1216                 i2s2: i2s@1c24400 {
1217                         #sound-dai-cells = <0>;
1218                         compatible = "allwinner,sun4i-a10-i2s";
1219                         reg = <0x01c24400 0x400>;
1220                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1221                         clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1222                         clock-names = "apb", "mod";
1223                         dmas = <&dma SUN4I_DMA_NORMAL 6>,
1224                                <&dma SUN4I_DMA_NORMAL 6>;
1225                         dma-names = "rx", "tx";
1226                         status = "disabled";
1227                 };
1228
1229                 rtp: rtp@1c25000 {
1230                         compatible = "allwinner,sun5i-a13-ts";
1231                         reg = <0x01c25000 0x100>;
1232                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1233                         #thermal-sensor-cells = <0>;
1234                 };
1235
1236                 uart0: serial@1c28000 {
1237                         compatible = "snps,dw-apb-uart";
1238                         reg = <0x01c28000 0x400>;
1239                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1240                         reg-shift = <2>;
1241                         reg-io-width = <4>;
1242                         clocks = <&ccu CLK_APB1_UART0>;
1243                         status = "disabled";
1244                 };
1245
1246                 uart1: serial@1c28400 {
1247                         compatible = "snps,dw-apb-uart";
1248                         reg = <0x01c28400 0x400>;
1249                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1250                         reg-shift = <2>;
1251                         reg-io-width = <4>;
1252                         clocks = <&ccu CLK_APB1_UART1>;
1253                         status = "disabled";
1254                 };
1255
1256                 uart2: serial@1c28800 {
1257                         compatible = "snps,dw-apb-uart";
1258                         reg = <0x01c28800 0x400>;
1259                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1260                         reg-shift = <2>;
1261                         reg-io-width = <4>;
1262                         clocks = <&ccu CLK_APB1_UART2>;
1263                         status = "disabled";
1264                 };
1265
1266                 uart3: serial@1c28c00 {
1267                         compatible = "snps,dw-apb-uart";
1268                         reg = <0x01c28c00 0x400>;
1269                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1270                         reg-shift = <2>;
1271                         reg-io-width = <4>;
1272                         clocks = <&ccu CLK_APB1_UART3>;
1273                         status = "disabled";
1274                 };
1275
1276                 uart4: serial@1c29000 {
1277                         compatible = "snps,dw-apb-uart";
1278                         reg = <0x01c29000 0x400>;
1279                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1280                         reg-shift = <2>;
1281                         reg-io-width = <4>;
1282                         clocks = <&ccu CLK_APB1_UART4>;
1283                         status = "disabled";
1284                 };
1285
1286                 uart5: serial@1c29400 {
1287                         compatible = "snps,dw-apb-uart";
1288                         reg = <0x01c29400 0x400>;
1289                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1290                         reg-shift = <2>;
1291                         reg-io-width = <4>;
1292                         clocks = <&ccu CLK_APB1_UART5>;
1293                         status = "disabled";
1294                 };
1295
1296                 uart6: serial@1c29800 {
1297                         compatible = "snps,dw-apb-uart";
1298                         reg = <0x01c29800 0x400>;
1299                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1300                         reg-shift = <2>;
1301                         reg-io-width = <4>;
1302                         clocks = <&ccu CLK_APB1_UART6>;
1303                         status = "disabled";
1304                 };
1305
1306                 uart7: serial@1c29c00 {
1307                         compatible = "snps,dw-apb-uart";
1308                         reg = <0x01c29c00 0x400>;
1309                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1310                         reg-shift = <2>;
1311                         reg-io-width = <4>;
1312                         clocks = <&ccu CLK_APB1_UART7>;
1313                         status = "disabled";
1314                 };
1315
1316                 ps20: ps2@1c2a000 {
1317                         compatible = "allwinner,sun4i-a10-ps2";
1318                         reg = <0x01c2a000 0x400>;
1319                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1320                         clocks = <&ccu CLK_APB1_PS20>;
1321                         status = "disabled";
1322                 };
1323
1324                 ps21: ps2@1c2a400 {
1325                         compatible = "allwinner,sun4i-a10-ps2";
1326                         reg = <0x01c2a400 0x400>;
1327                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1328                         clocks = <&ccu CLK_APB1_PS21>;
1329                         status = "disabled";
1330                 };
1331
1332                 i2c0: i2c@1c2ac00 {
1333                         compatible = "allwinner,sun7i-a20-i2c",
1334                                      "allwinner,sun4i-a10-i2c";
1335                         reg = <0x01c2ac00 0x400>;
1336                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1337                         clocks = <&ccu CLK_APB1_I2C0>;
1338                         pinctrl-names = "default";
1339                         pinctrl-0 = <&i2c0_pins>;
1340                         status = "disabled";
1341                         #address-cells = <1>;
1342                         #size-cells = <0>;
1343                 };
1344
1345                 i2c1: i2c@1c2b000 {
1346                         compatible = "allwinner,sun7i-a20-i2c",
1347                                      "allwinner,sun4i-a10-i2c";
1348                         reg = <0x01c2b000 0x400>;
1349                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1350                         clocks = <&ccu CLK_APB1_I2C1>;
1351                         pinctrl-names = "default";
1352                         pinctrl-0 = <&i2c1_pins>;
1353                         status = "disabled";
1354                         #address-cells = <1>;
1355                         #size-cells = <0>;
1356                 };
1357
1358                 i2c2: i2c@1c2b400 {
1359                         compatible = "allwinner,sun7i-a20-i2c",
1360                                      "allwinner,sun4i-a10-i2c";
1361                         reg = <0x01c2b400 0x400>;
1362                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1363                         clocks = <&ccu CLK_APB1_I2C2>;
1364                         pinctrl-names = "default";
1365                         pinctrl-0 = <&i2c2_pins>;
1366                         status = "disabled";
1367                         #address-cells = <1>;
1368                         #size-cells = <0>;
1369                 };
1370
1371                 i2c3: i2c@1c2b800 {
1372                         compatible = "allwinner,sun7i-a20-i2c",
1373                                      "allwinner,sun4i-a10-i2c";
1374                         reg = <0x01c2b800 0x400>;
1375                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1376                         clocks = <&ccu CLK_APB1_I2C3>;
1377                         pinctrl-names = "default";
1378                         pinctrl-0 = <&i2c3_pins>;
1379                         status = "disabled";
1380                         #address-cells = <1>;
1381                         #size-cells = <0>;
1382                 };
1383
1384                 can0: can@1c2bc00 {
1385                         compatible = "allwinner,sun7i-a20-can",
1386                                      "allwinner,sun4i-a10-can";
1387                         reg = <0x01c2bc00 0x400>;
1388                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1389                         clocks = <&ccu CLK_APB1_CAN>;
1390                         status = "disabled";
1391                 };
1392
1393                 i2c4: i2c@1c2c000 {
1394                         compatible = "allwinner,sun7i-a20-i2c",
1395                                      "allwinner,sun4i-a10-i2c";
1396                         reg = <0x01c2c000 0x400>;
1397                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1398                         clocks = <&ccu CLK_APB1_I2C4>;
1399                         status = "disabled";
1400                         #address-cells = <1>;
1401                         #size-cells = <0>;
1402                 };
1403
1404                 mali: gpu@1c40000 {
1405                         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1406                         reg = <0x01c40000 0x10000>;
1407                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1408                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1409                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1410                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1411                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1412                                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1413                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1414                         interrupt-names = "gp",
1415                                           "gpmmu",
1416                                           "pp0",
1417                                           "ppmmu0",
1418                                           "pp1",
1419                                           "ppmmu1",
1420                                           "pmu";
1421                         clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1422                         clock-names = "bus", "core";
1423                         resets = <&ccu RST_GPU>;
1424
1425                         assigned-clocks = <&ccu CLK_GPU>;
1426                         assigned-clock-rates = <384000000>;
1427                 };
1428
1429                 gmac: ethernet@1c50000 {
1430                         compatible = "allwinner,sun7i-a20-gmac";
1431                         reg = <0x01c50000 0x10000>;
1432                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1433                         interrupt-names = "macirq";
1434                         clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1435                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1436                         snps,pbl = <2>;
1437                         snps,fixed-burst;
1438                         snps,force_sf_dma_mode;
1439                         status = "disabled";
1440                         #address-cells = <1>;
1441                         #size-cells = <0>;
1442                 };
1443
1444                 hstimer@1c60000 {
1445                         compatible = "allwinner,sun7i-a20-hstimer";
1446                         reg = <0x01c60000 0x1000>;
1447                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1448                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1449                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1450                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1451                         clocks = <&ccu CLK_AHB_HSTIMER>;
1452                 };
1453
1454                 gic: interrupt-controller@1c81000 {
1455                         compatible = "arm,gic-400";
1456                         reg = <0x01c81000 0x1000>,
1457                               <0x01c82000 0x2000>,
1458                               <0x01c84000 0x2000>,
1459                               <0x01c86000 0x2000>;
1460                         interrupt-controller;
1461                         #interrupt-cells = <3>;
1462                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1463                 };
1464
1465                 fe0: display-frontend@1e00000 {
1466                         compatible = "allwinner,sun7i-a20-display-frontend";
1467                         reg = <0x01e00000 0x20000>;
1468                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1469                         clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1470                                  <&ccu CLK_DRAM_DE_FE0>;
1471                         clock-names = "ahb", "mod",
1472                                       "ram";
1473                         resets = <&ccu RST_DE_FE0>;
1474
1475                         ports {
1476                                 #address-cells = <1>;
1477                                 #size-cells = <0>;
1478
1479                                 fe0_out: port@1 {
1480                                         #address-cells = <1>;
1481                                         #size-cells = <0>;
1482                                         reg = <1>;
1483
1484                                         fe0_out_be0: endpoint@0 {
1485                                                 reg = <0>;
1486                                                 remote-endpoint = <&be0_in_fe0>;
1487                                         };
1488
1489                                         fe0_out_be1: endpoint@1 {
1490                                                 reg = <1>;
1491                                                 remote-endpoint = <&be1_in_fe0>;
1492                                         };
1493                                 };
1494                         };
1495                 };
1496
1497                 fe1: display-frontend@1e20000 {
1498                         compatible = "allwinner,sun7i-a20-display-frontend";
1499                         reg = <0x01e20000 0x20000>;
1500                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1501                         clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1502                                  <&ccu CLK_DRAM_DE_FE1>;
1503                         clock-names = "ahb", "mod",
1504                                       "ram";
1505                         resets = <&ccu RST_DE_FE1>;
1506
1507                         ports {
1508                                 #address-cells = <1>;
1509                                 #size-cells = <0>;
1510
1511                                 fe1_out: port@1 {
1512                                         #address-cells = <1>;
1513                                         #size-cells = <0>;
1514                                         reg = <1>;
1515
1516                                         fe1_out_be0: endpoint@0 {
1517                                                 reg = <0>;
1518                                                 remote-endpoint = <&be0_in_fe1>;
1519                                         };
1520
1521                                         fe1_out_be1: endpoint@1 {
1522                                                 reg = <1>;
1523                                                 remote-endpoint = <&be1_in_fe1>;
1524                                         };
1525                                 };
1526                         };
1527                 };
1528
1529                 be1: display-backend@1e40000 {
1530                         compatible = "allwinner,sun7i-a20-display-backend";
1531                         reg = <0x01e40000 0x10000>;
1532                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1533                         clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1534                                  <&ccu CLK_DRAM_DE_BE1>;
1535                         clock-names = "ahb", "mod",
1536                                       "ram";
1537                         resets = <&ccu RST_DE_BE1>;
1538
1539                         ports {
1540                                 #address-cells = <1>;
1541                                 #size-cells = <0>;
1542
1543                                 be1_in: port@0 {
1544                                         #address-cells = <1>;
1545                                         #size-cells = <0>;
1546                                         reg = <0>;
1547
1548                                         be1_in_fe0: endpoint@0 {
1549                                                 reg = <0>;
1550                                                 remote-endpoint = <&fe0_out_be1>;
1551                                         };
1552
1553                                         be1_in_fe1: endpoint@1 {
1554                                                 reg = <1>;
1555                                                 remote-endpoint = <&fe1_out_be1>;
1556                                         };
1557                                 };
1558
1559                                 be1_out: port@1 {
1560                                         #address-cells = <1>;
1561                                         #size-cells = <0>;
1562                                         reg = <1>;
1563
1564                                         be1_out_tcon0: endpoint@0 {
1565                                                 reg = <0>;
1566                                                 remote-endpoint = <&tcon0_in_be1>;
1567                                         };
1568
1569                                         be1_out_tcon1: endpoint@1 {
1570                                                 reg = <1>;
1571                                                 remote-endpoint = <&tcon1_in_be1>;
1572                                         };
1573                                 };
1574                         };
1575                 };
1576
1577                 be0: display-backend@1e60000 {
1578                         compatible = "allwinner,sun7i-a20-display-backend";
1579                         reg = <0x01e60000 0x10000>;
1580                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1581                         clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1582                                  <&ccu CLK_DRAM_DE_BE0>;
1583                         clock-names = "ahb", "mod",
1584                                       "ram";
1585                         resets = <&ccu RST_DE_BE0>;
1586
1587                         ports {
1588                                 #address-cells = <1>;
1589                                 #size-cells = <0>;
1590
1591                                 be0_in: port@0 {
1592                                         #address-cells = <1>;
1593                                         #size-cells = <0>;
1594                                         reg = <0>;
1595
1596                                         be0_in_fe0: endpoint@0 {
1597                                                 reg = <0>;
1598                                                 remote-endpoint = <&fe0_out_be0>;
1599                                         };
1600
1601                                         be0_in_fe1: endpoint@1 {
1602                                                 reg = <1>;
1603                                                 remote-endpoint = <&fe1_out_be0>;
1604                                         };
1605                                 };
1606
1607                                 be0_out: port@1 {
1608                                         #address-cells = <1>;
1609                                         #size-cells = <0>;
1610                                         reg = <1>;
1611
1612                                         be0_out_tcon0: endpoint@0 {
1613                                                 reg = <0>;
1614                                                 remote-endpoint = <&tcon0_in_be0>;
1615                                         };
1616
1617                                         be0_out_tcon1: endpoint@1 {
1618                                                 reg = <1>;
1619                                                 remote-endpoint = <&tcon1_in_be0>;
1620                                         };
1621                                 };
1622                         };
1623                 };
1624         };
1625 };