arch/arm/boot/dts/sun5i.dtsi

   1 /*
   2  * Copyright 2012-2015 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include <dt-bindings/clock/sun5i-ccu.h>
  46 #include <dt-bindings/dma/sun4i-a10.h>
  47 #include <dt-bindings/reset/sun5i-ccu.h>
  48
  49 / {
  50         interrupt-parent = <&intc>;
  51         #address-cells = <1>;
  52         #size-cells = <1>;
  53
  54         cpus {
  55                 #address-cells = <1>;
  56                 #size-cells = <0>;
  57
  58                 cpu0: cpu@0 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a8";
  61                         reg = <0x0>;
  62                         clocks = <&ccu CLK_CPU>;
  63                 };
  64         };
  65
  66         chosen {
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 framebuffer-lcd0 {
  72                         compatible = "allwinner,simple-framebuffer",
  73                                      "simple-framebuffer";
  74                         allwinner,pipeline = "de_be0-lcd0";
  75                         clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  76                                  <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
  77                         status = "disabled";
  78                 };
  79
  80                 framebuffer-lcd0-tve0 {
  81                         compatible = "allwinner,simple-framebuffer",
  82                                      "simple-framebuffer";
  83                         allwinner,pipeline = "de_be0-lcd0-tve0";
  84                         clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>,
  85                                  <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  86                                  <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>;
  87                         status = "disabled";
  88                 };
  89         };
  90
  91         clocks {
  92                 #address-cells = <1>;
  93                 #size-cells = <1>;
  94                 ranges;
  95
  96                 osc24M: clk-24M {
  97                         #clock-cells = <0>;
  98                         compatible = "fixed-clock";
  99                         clock-frequency = <24000000>;
 100                         clock-output-names = "osc24M";
 101                 };
 102
 103                 osc32k: clk-32k {
 104                         #clock-cells = <0>;
 105                         compatible = "fixed-clock";
 106                         clock-frequency = <32768>;
 107                         clock-output-names = "osc32k";
 108                 };
 109         };
 110
 111         reserved-memory {
 112                 #address-cells = <1>;
 113                 #size-cells = <1>;
 114                 ranges;
 115
 116                 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 117                 default-pool {
 118                         compatible = "shared-dma-pool";
 119                         size = <0x6000000>;
 120                         alloc-ranges = <0x4a000000 0x6000000>;
 121                         reusable;
 122                         linux,cma-default;
 123                 };
 124         };
 125
 126         soc {
 127                 compatible = "simple-bus";
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130                 ranges;
 131
 132                 system-control@1c00000 {
 133                         compatible = "allwinner,sun5i-a13-system-control";
 134                         reg = <0x01c00000 0x30>;
 135                         #address-cells = <1>;
 136                         #size-cells = <1>;
 137                         ranges;
 138
 139                         sram_a: sram@0 {
 140                                 compatible = "mmio-sram";
 141                                 reg = <0x00000000 0xc000>;
 142                                 #address-cells = <1>;
 143                                 #size-cells = <1>;
 144                                 ranges = <0 0x00000000 0xc000>;
 145
 146                                 emac_sram: sram-section@8000 {
 147                                         compatible = "allwinner,sun5i-a13-sram-a3-a4",
 148                                                      "allwinner,sun4i-a10-sram-a3-a4";
 149                                         reg = <0x8000 0x4000>;
 150                                         status = "disabled";
 151                                 };
 152                         };
 153
 154                         sram_d: sram@10000 {
 155                                 compatible = "mmio-sram";
 156                                 reg = <0x00010000 0x1000>;
 157                                 #address-cells = <1>;
 158                                 #size-cells = <1>;
 159                                 ranges = <0 0x00010000 0x1000>;
 160
 161                                 otg_sram: sram-section@0 {
 162                                         compatible = "allwinner,sun5i-a13-sram-d",
 163                                                      "allwinner,sun4i-a10-sram-d";
 164                                         reg = <0x0000 0x1000>;
 165                                         status = "disabled";
 166                                 };
 167                         };
 168
 169                         sram_c: sram@1d00000 {
 170                                 compatible = "mmio-sram";
 171                                 reg = <0x01d00000 0xd0000>;
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 ranges = <0 0x01d00000 0xd0000>;
 175
 176                                 ve_sram: sram-section@0 {
 177                                         compatible = "allwinner,sun5i-a13-sram-c1",
 178                                                      "allwinner,sun4i-a10-sram-c1";
 179                                         reg = <0x000000 0x80000>;
 180                                 };
 181                         };
 182                 };
 183
 184                 dma: dma-controller@1c02000 {
 185                         compatible = "allwinner,sun4i-a10-dma";
 186                         reg = <0x01c02000 0x1000>;
 187                         interrupts = <27>;
 188                         clocks = <&ccu CLK_AHB_DMA>;
 189                         #dma-cells = <2>;
 190                 };
 191
 192                 nfc: nand@1c03000 {
 193                         compatible = "allwinner,sun4i-a10-nand";
 194                         reg = <0x01c03000 0x1000>;
 195                         interrupts = <37>;
 196                         clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 197                         clock-names = "ahb", "mod";
 198                         dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 199                         dma-names = "rxtx";
 200                         status = "disabled";
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                 };
 204
 205                 spi0: spi@1c05000 {
 206                         compatible = "allwinner,sun4i-a10-spi";
 207                         reg = <0x01c05000 0x1000>;
 208                         interrupts = <10>;
 209                         clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 210                         clock-names = "ahb", "mod";
 211                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 212                                <&dma SUN4I_DMA_DEDICATED 26>;
 213                         dma-names = "rx", "tx";
 214                         status = "disabled";
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                 };
 218
 219                 spi1: spi@1c06000 {
 220                         compatible = "allwinner,sun4i-a10-spi";
 221                         reg = <0x01c06000 0x1000>;
 222                         interrupts = <11>;
 223                         clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 224                         clock-names = "ahb", "mod";
 225                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 226                                <&dma SUN4I_DMA_DEDICATED 8>;
 227                         dma-names = "rx", "tx";
 228                         status = "disabled";
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                 };
 232
 233                 tve0: tv-encoder@1c0a000 {
 234                         compatible = "allwinner,sun4i-a10-tv-encoder";
 235                         reg = <0x01c0a000 0x1000>;
 236                         clocks = <&ccu CLK_AHB_TVE>;
 237                         resets = <&ccu RST_TVE>;
 238                         status = "disabled";
 239
 240                         port {
 241                                 #address-cells = <1>;
 242                                 #size-cells = <0>;
 243
 244                                 tve0_in_tcon0: endpoint@0 {
 245                                         reg = <0>;
 246                                         remote-endpoint = <&tcon0_out_tve0>;
 247                                 };
 248                         };
 249                 };
 250
 251                 emac: ethernet@1c0b000 {
 252                         compatible = "allwinner,sun4i-a10-emac";
 253                         reg = <0x01c0b000 0x1000>;
 254                         interrupts = <55>;
 255                         clocks = <&ccu CLK_AHB_EMAC>;
 256                         allwinner,sram = <&emac_sram 1>;
 257                         status = "disabled";
 258                 };
 259
 260                 mdio: mdio@1c0b080 {
 261                         compatible = "allwinner,sun4i-a10-mdio";
 262                         reg = <0x01c0b080 0x14>;
 263                         status = "disabled";
 264                         #address-cells = <1>;
 265                         #size-cells = <0>;
 266                 };
 267
 268                 tcon0: lcd-controller@1c0c000 {
 269                         compatible = "allwinner,sun5i-a13-tcon";
 270                         reg = <0x01c0c000 0x1000>;
 271                         interrupts = <44>;
 272                         resets = <&ccu RST_LCD>;
 273                         reset-names = "lcd";
 274                         clocks = <&ccu CLK_AHB_LCD>,
 275                                  <&ccu CLK_TCON_CH0>,
 276                                  <&ccu CLK_TCON_CH1>;
 277                         clock-names = "ahb",
 278                                       "tcon-ch0",
 279                                       "tcon-ch1";
 280                         clock-output-names = "tcon-pixel-clock";
 281                         status = "disabled";
 282
 283                         ports {
 284                                 #address-cells = <1>;
 285                                 #size-cells = <0>;
 286
 287                                 tcon0_in: port@0 {
 288                                         #address-cells = <1>;
 289                                         #size-cells = <0>;
 290                                         reg = <0>;
 291
 292                                         tcon0_in_be0: endpoint@0 {
 293                                                 reg = <0>;
 294                                                 remote-endpoint = <&be0_out_tcon0>;
 295                                         };
 296                                 };
 297
 298                                 tcon0_out: port@1 {
 299                                         #address-cells = <1>;
 300                                         #size-cells = <0>;
 301                                         reg = <1>;
 302
 303                                         tcon0_out_tve0: endpoint@1 {
 304                                                 reg = <1>;
 305                                                 remote-endpoint = <&tve0_in_tcon0>;
 306                                                 allwinner,tcon-channel = <1>;
 307                                         };
 308                                 };
 309                         };
 310                 };
 311
 312                 video-codec@1c0e000 {
 313                         compatible = "allwinner,sun5i-a13-video-engine";
 314                         reg = <0x01c0e000 0x1000>;
 315                         clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 316                                  <&ccu CLK_DRAM_VE>;
 317                         clock-names = "ahb", "mod", "ram";
 318                         resets = <&ccu RST_VE>;
 319                         interrupts = <53>;
 320                         allwinner,sram = <&ve_sram 1>;
 321                 };
 322
 323                 mmc0: mmc@1c0f000 {
 324                         compatible = "allwinner,sun5i-a13-mmc";
 325                         reg = <0x01c0f000 0x1000>;
 326                         clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>;
 327                         clock-names = "ahb", "mmc";
 328                         interrupts = <32>;
 329                         pinctrl-names = "default";
 330                         pinctrl-0 = <&mmc0_pins>;
 331                         status = "disabled";
 332                         #address-cells = <1>;
 333                         #size-cells = <0>;
 334                 };
 335
 336                 mmc1: mmc@1c10000 {
 337                         compatible = "allwinner,sun5i-a13-mmc";
 338                         reg = <0x01c10000 0x1000>;
 339                         clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>;
 340                         clock-names = "ahb", "mmc";
 341                         interrupts = <33>;
 342                         status = "disabled";
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                 };
 346
 347                 mmc2: mmc@1c11000 {
 348                         compatible = "allwinner,sun5i-a13-mmc";
 349                         reg = <0x01c11000 0x1000>;
 350                         clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>;
 351                         clock-names = "ahb", "mmc";
 352                         interrupts = <34>;
 353                         status = "disabled";
 354                         #address-cells = <1>;
 355                         #size-cells = <0>;
 356                 };
 357
 358                 usb_otg: usb@1c13000 {
 359                         compatible = "allwinner,sun4i-a10-musb";
 360                         reg = <0x01c13000 0x0400>;
 361                         clocks = <&ccu CLK_AHB_OTG>;
 362                         interrupts = <38>;
 363                         interrupt-names = "mc";
 364                         phys = <&usbphy 0>;
 365                         phy-names = "usb";
 366                         extcon = <&usbphy 0>;
 367                         allwinner,sram = <&otg_sram 1>;
 368                         status = "disabled";
 369                 };
 370
 371                 usbphy: phy@1c13400 {
 372                         #phy-cells = <1>;
 373                         compatible = "allwinner,sun5i-a13-usb-phy";
 374                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 375                         reg-names = "phy_ctrl", "pmu1";
 376                         clocks = <&ccu CLK_USB_PHY0>;
 377                         clock-names = "usb_phy";
 378                         resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
 379                         reset-names = "usb0_reset", "usb1_reset";
 380                         status = "disabled";
 381                 };
 382
 383                 ehci0: usb@1c14000 {
 384                         compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
 385                         reg = <0x01c14000 0x100>;
 386                         interrupts = <39>;
 387                         clocks = <&ccu CLK_AHB_EHCI>;
 388                         phys = <&usbphy 1>;
 389                         phy-names = "usb";
 390                         status = "disabled";
 391                 };
 392
 393                 ohci0: usb@1c14400 {
 394                         compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
 395                         reg = <0x01c14400 0x100>;
 396                         interrupts = <40>;
 397                         clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>;
 398                         phys = <&usbphy 1>;
 399                         phy-names = "usb";
 400                         status = "disabled";
 401                 };
 402
 403                 crypto: crypto-engine@1c15000 {
 404                         compatible = "allwinner,sun5i-a13-crypto",
 405                                      "allwinner,sun4i-a10-crypto";
 406                         reg = <0x01c15000 0x1000>;
 407                         interrupts = <54>;
 408                         clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 409                         clock-names = "ahb", "mod";
 410                 };
 411
 412                 spi2: spi@1c17000 {
 413                         compatible = "allwinner,sun4i-a10-spi";
 414                         reg = <0x01c17000 0x1000>;
 415                         interrupts = <12>;
 416                         clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 417                         clock-names = "ahb", "mod";
 418                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 419                                <&dma SUN4I_DMA_DEDICATED 28>;
 420                         dma-names = "rx", "tx";
 421                         status = "disabled";
 422                         #address-cells = <1>;
 423                         #size-cells = <0>;
 424                 };
 425
 426                 ccu: clock@1c20000 {
 427                         reg = <0x01c20000 0x400>;
 428                         clocks = <&osc24M>, <&osc32k>;
 429                         clock-names = "hosc", "losc";
 430                         #clock-cells = <1>;
 431                         #reset-cells = <1>;
 432                 };
 433
 434                 intc: interrupt-controller@1c20400 {
 435                         compatible = "allwinner,sun4i-a10-ic";
 436                         reg = <0x01c20400 0x400>;
 437                         interrupt-controller;
 438                         #interrupt-cells = <1>;
 439                 };
 440
 441                 pio: pinctrl@1c20800 {
 442                         reg = <0x01c20800 0x400>;
 443                         interrupts = <28>;
 444                         clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 445                         clock-names = "apb", "hosc", "losc";
 446                         gpio-controller;
 447                         interrupt-controller;
 448                         #interrupt-cells = <3>;
 449                         #gpio-cells = <3>;
 450
 451                         emac_pd_pins: emac-pd-pins {
 452                                 pins = "PD6", "PD7", "PD10",
 453                                        "PD11", "PD12", "PD13", "PD14",
 454                                        "PD15", "PD18", "PD19", "PD20",
 455                                        "PD21", "PD22", "PD23", "PD24",
 456                                        "PD25", "PD26", "PD27";
 457                                 function = "emac";
 458                         };
 459
 460                         i2c0_pins: i2c0-pins {
 461                                 pins = "PB0", "PB1";
 462                                 function = "i2c0";
 463                         };
 464
 465                         i2c1_pins: i2c1-pins {
 466                                 pins = "PB15", "PB16";
 467                                 function = "i2c1";
 468                         };
 469
 470                         i2c2_pins: i2c2-pins {
 471                                 pins = "PB17", "PB18";
 472                                 function = "i2c2";
 473                         };
 474
 475                         ir0_rx_pin: ir0-rx-pin {
 476                                 pins = "PB4";
 477                                 function = "ir0";
 478                         };
 479
 480                         lcd_rgb565_pins: lcd-rgb565-pins {
 481                                 pins = "PD3", "PD4", "PD5", "PD6", "PD7",
 482                                                  "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 483                                                  "PD19", "PD20", "PD21", "PD22", "PD23",
 484                                                  "PD24", "PD25", "PD26", "PD27";
 485                                 function = "lcd0";
 486                         };
 487
 488                         lcd_rgb666_pins: lcd-rgb666-pins {
 489                                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 490                                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 491                                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 492                                        "PD24", "PD25", "PD26", "PD27";
 493                                 function = "lcd0";
 494                         };
 495
 496                         mmc0_pins: mmc0-pins {
 497                                 pins = "PF0", "PF1", "PF2", "PF3",
 498                                        "PF4", "PF5";
 499                                 function = "mmc0";
 500                                 drive-strength = <30>;
 501                                 bias-pull-up;
 502                         };
 503
 504                         mmc2_8bit_pins: mmc2-8bit-pins {
 505                                 pins = "PC6", "PC7", "PC8", "PC9",
 506                                        "PC10", "PC11", "PC12", "PC13",
 507                                        "PC14", "PC15";
 508                                 function = "mmc2";
 509                                 drive-strength = <30>;
 510                                 bias-pull-up;
 511                         };
 512
 513                         mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
 514                                 pins = "PC6", "PC7", "PC8", "PC9",
 515                                        "PC10", "PC11";
 516                                 function = "mmc2";
 517                                 drive-strength = <30>;
 518                                 bias-pull-up;
 519                         };
 520
 521                         nand_pins: nand-pins {
 522                                 pins = "PC0", "PC1", "PC2",
 523                                        "PC5", "PC8", "PC9", "PC10",
 524                                        "PC11", "PC12", "PC13", "PC14",
 525                                        "PC15";
 526                                 function = "nand0";
 527                         };
 528
 529                         nand_cs0_pin: nand-cs0-pin {
 530                                 pins = "PC4";
 531                                 function = "nand0";
 532                         };
 533
 534                         nand_rb0_pin: nand-rb0-pin {
 535                                 pins = "PC6";
 536                                 function = "nand0";
 537                         };
 538
 539                         spi2_pe_pins: spi2-pe-pins {
 540                                 pins = "PE1", "PE2", "PE3";
 541                                 function = "spi2";
 542                         };
 543
 544                         spi2_cs0_pe_pin: spi2-cs0-pe-pin {
 545                                 pins = "PE0";
 546                                 function = "spi2";
 547                         };
 548
 549                         uart1_pe_pins: uart1-pe-pins {
 550                                 pins = "PE10", "PE11";
 551                                 function = "uart1";
 552                         };
 553
 554                         uart1_pg_pins: uart1-pg-pins {
 555                                 pins = "PG3", "PG4";
 556                                 function = "uart1";
 557                         };
 558
 559                         uart2_pd_pins: uart2-pd-pins {
 560                                 pins = "PD2", "PD3";
 561                                 function = "uart2";
 562                         };
 563
 564                         uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins {
 565                                 pins = "PD4", "PD5";
 566                                 function = "uart2";
 567                         };
 568
 569                         uart3_pg_pins: uart3-pg-pins {
 570                                 pins = "PG9", "PG10";
 571                                 function = "uart3";
 572                         };
 573
 574                         uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
 575                                 pins = "PG11", "PG12";
 576                                 function = "uart3";
 577                         };
 578
 579                         pwm0_pin: pwm0-pin {
 580                                 pins = "PB2";
 581                                 function = "pwm";
 582                         };
 583                 };
 584
 585                 timer@1c20c00 {
 586                         compatible = "allwinner,sun4i-a10-timer";
 587                         reg = <0x01c20c00 0x90>;
 588                         interrupts = <22>;
 589                         clocks = <&ccu CLK_HOSC>;
 590                 };
 591
 592                 wdt: watchdog@1c20c90 {
 593                         compatible = "allwinner,sun4i-a10-wdt";
 594                         reg = <0x01c20c90 0x10>;
 595                 };
 596
 597                 ir0: ir@1c21800 {
 598                         compatible = "allwinner,sun4i-a10-ir";
 599                         clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>;
 600                         clock-names = "apb", "ir";
 601                         interrupts = <5>;
 602                         reg = <0x01c21800 0x40>;
 603                         status = "disabled";
 604                 };
 605
 606                 lradc: lradc@1c22800 {
 607                         compatible = "allwinner,sun4i-a10-lradc-keys";
 608                         reg = <0x01c22800 0x100>;
 609                         interrupts = <31>;
 610                         status = "disabled";
 611                 };
 612
 613                 codec: codec@1c22c00 {
 614                         #sound-dai-cells = <0>;
 615                         compatible = "allwinner,sun4i-a10-codec";
 616                         reg = <0x01c22c00 0x40>;
 617                         interrupts = <30>;
 618                         clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
 619                         clock-names = "apb", "codec";
 620                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
 621                                <&dma SUN4I_DMA_NORMAL 19>;
 622                         dma-names = "rx", "tx";
 623                         status = "disabled";
 624                 };
 625
 626                 sid: eeprom@1c23800 {
 627                         compatible = "allwinner,sun4i-a10-sid";
 628                         reg = <0x01c23800 0x10>;
 629                 };
 630
 631                 rtp: rtp@1c25000 {
 632                         compatible = "allwinner,sun5i-a13-ts";
 633                         reg = <0x01c25000 0x100>;
 634                         interrupts = <29>;
 635                         #thermal-sensor-cells = <0>;
 636                 };
 637
 638                 uart0: serial@1c28000 {
 639                         compatible = "snps,dw-apb-uart";
 640                         reg = <0x01c28000 0x400>;
 641                         interrupts = <1>;
 642                         reg-shift = <2>;
 643                         reg-io-width = <4>;
 644                         clocks = <&ccu CLK_APB1_UART0>;
 645                         status = "disabled";
 646                 };
 647
 648                 uart1: serial@1c28400 {
 649                         compatible = "snps,dw-apb-uart";
 650                         reg = <0x01c28400 0x400>;
 651                         interrupts = <2>;
 652                         reg-shift = <2>;
 653                         reg-io-width = <4>;
 654                         clocks = <&ccu CLK_APB1_UART1>;
 655                         status = "disabled";
 656                 };
 657
 658                 uart2: serial@1c28800 {
 659                         compatible = "snps,dw-apb-uart";
 660                         reg = <0x01c28800 0x400>;
 661                         interrupts = <3>;
 662                         reg-shift = <2>;
 663                         reg-io-width = <4>;
 664                         clocks = <&ccu CLK_APB1_UART2>;
 665                         status = "disabled";
 666                 };
 667
 668                 uart3: serial@1c28c00 {
 669                         compatible = "snps,dw-apb-uart";
 670                         reg = <0x01c28c00 0x400>;
 671                         interrupts = <4>;
 672                         reg-shift = <2>;
 673                         reg-io-width = <4>;
 674                         clocks = <&ccu CLK_APB1_UART3>;
 675                         status = "disabled";
 676                 };
 677
 678                 i2c0: i2c@1c2ac00 {
 679                         compatible = "allwinner,sun4i-a10-i2c";
 680                         reg = <0x01c2ac00 0x400>;
 681                         interrupts = <7>;
 682                         clocks = <&ccu CLK_APB1_I2C0>;
 683                         pinctrl-names = "default";
 684                         pinctrl-0 = <&i2c0_pins>;
 685                         status = "disabled";
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                 };
 689
 690                 i2c1: i2c@1c2b000 {
 691                         compatible = "allwinner,sun4i-a10-i2c";
 692                         reg = <0x01c2b000 0x400>;
 693                         interrupts = <8>;
 694                         clocks = <&ccu CLK_APB1_I2C1>;
 695                         pinctrl-names = "default";
 696                         pinctrl-0 = <&i2c1_pins>;
 697                         status = "disabled";
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                 };
 701
 702                 i2c2: i2c@1c2b400 {
 703                         compatible = "allwinner,sun4i-a10-i2c";
 704                         reg = <0x01c2b400 0x400>;
 705                         interrupts = <9>;
 706                         clocks = <&ccu CLK_APB1_I2C2>;
 707                         pinctrl-names = "default";
 708                         pinctrl-0 = <&i2c2_pins>;
 709                         status = "disabled";
 710                         #address-cells = <1>;
 711                         #size-cells = <0>;
 712                 };
 713
 714                 timer@1c60000 {
 715                         compatible = "allwinner,sun5i-a13-hstimer";
 716                         reg = <0x01c60000 0x1000>;
 717                         interrupts = <82>, <83>;
 718                         clocks = <&ccu CLK_AHB_HSTIMER>;
 719                 };
 720
 721                 fe0: display-frontend@1e00000 {
 722                         compatible = "allwinner,sun5i-a13-display-frontend";
 723                         reg = <0x01e00000 0x20000>;
 724                         interrupts = <47>;
 725                         clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
 726                                  <&ccu CLK_DRAM_DE_FE>;
 727                         clock-names = "ahb", "mod",
 728                                       "ram";
 729                         resets = <&ccu RST_DE_FE>;
 730                         status = "disabled";
 731
 732                         ports {
 733                                 #address-cells = <1>;
 734                                 #size-cells = <0>;
 735
 736                                 fe0_out: port@1 {
 737                                         #address-cells = <1>;
 738                                         #size-cells = <0>;
 739                                         reg = <1>;
 740
 741                                         fe0_out_be0: endpoint@0 {
 742                                                 reg = <0>;
 743                                                 remote-endpoint = <&be0_in_fe0>;
 744                                         };
 745                                 };
 746                         };
 747                 };
 748
 749                 be0: display-backend@1e60000 {
 750                         compatible = "allwinner,sun5i-a13-display-backend";
 751                         reg = <0x01e60000 0x10000>;
 752                         interrupts = <47>;
 753                         clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
 754                                  <&ccu CLK_DRAM_DE_BE>;
 755                         clock-names = "ahb", "mod",
 756                                       "ram";
 757                         resets = <&ccu RST_DE_BE>;
 758                         status = "disabled";
 759
 760                         assigned-clocks = <&ccu CLK_DE_BE>;
 761                         assigned-clock-rates = <300000000>;
 762
 763                         ports {
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766
 767                                 be0_in: port@0 {
 768                                         #address-cells = <1>;
 769                                         #size-cells = <0>;
 770                                         reg = <0>;
 771
 772                                         be0_in_fe0: endpoint@0 {
 773                                                 reg = <0>;
 774                                                 remote-endpoint = <&fe0_out_be0>;
 775                                         };
 776                                 };
 777
 778                                 be0_out: port@1 {
 779                                         #address-cells = <1>;
 780                                         #size-cells = <0>;
 781                                         reg = <1>;
 782
 783                                         be0_out_tcon0: endpoint@0 {
 784                                                 reg = <0>;
 785                                                 remote-endpoint = <&tcon0_in_be0>;
 786                                         };
 787                                 };
 788                         };
 789                 };
 790         };
 791 };