arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include "sun5i.dtsi"
  48
  49 #include <dt-bindings/pinctrl/sun4i-a10.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         interrupt-parent = <&intc>;
  54
  55         chosen {
  56                 #address-cells = <1>;
  57                 #size-cells = <1>;
  58                 ranges;
  59
  60                 framebuffer@0 {
  61                         compatible = "allwinner,simple-framebuffer",
  62                                      "simple-framebuffer";
  63                         allwinner,pipeline = "de_be0-lcd0";
  64                         clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
  65                                  <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>;
  66                         status = "disabled";
  67                 };
  68         };
  69
  70         thermal-zones {
  71                 cpu_thermal {
  72                         /* milliseconds */
  73                         polling-delay-passive = <250>;
  74                         polling-delay = <1000>;
  75                         thermal-sensors = <&rtp>;
  76
  77                         cooling-maps {
  78                                 map0 {
  79                                         trip = <&cpu_alert0>;
  80                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  81                                 };
  82                         };
  83
  84                         trips {
  85                                 cpu_alert0: cpu_alert0 {
  86                                         /* milliCelsius */
  87                                         temperature = <85000>;
  88                                         hysteresis = <2000>;
  89                                         type = "passive";
  90                                 };
  91
  92                                 cpu_crit: cpu_crit {
  93                                         /* milliCelsius */
  94                                         temperature = <100000>;
  95                                         hysteresis = <2000>;
  96                                         type = "critical";
  97                                 };
  98                         };
  99                 };
 100         };
 101
 102         display-engine {
 103                 compatible = "allwinner,sun5i-a13-display-engine";
 104                 allwinner,pipelines = <&fe0>;
 105         };
 106
 107         soc@01c00000 {
 108                 tcon0: lcd-controller@01c0c000 {
 109                         compatible = "allwinner,sun5i-a13-tcon";
 110                         reg = <0x01c0c000 0x1000>;
 111                         interrupts = <44>;
 112                         resets = <&ccu RST_LCD>;
 113                         reset-names = "lcd";
 114                         clocks = <&ccu CLK_AHB_LCD>,
 115                                  <&ccu CLK_TCON_CH0>,
 116                                  <&ccu CLK_TCON_CH1>;
 117                         clock-names = "ahb",
 118                                       "tcon-ch0",
 119                                       "tcon-ch1";
 120                         clock-output-names = "tcon-pixel-clock";
 121                         status = "disabled";
 122
 123                         ports {
 124                                 #address-cells = <1>;
 125                                 #size-cells = <0>;
 126
 127                                 tcon0_in: port@0 {
 128                                         #address-cells = <1>;
 129                                         #size-cells = <0>;
 130                                         reg = <0>;
 131
 132                                         tcon0_in_be0: endpoint@0 {
 133                                                 reg = <0>;
 134                                                 remote-endpoint = <&be0_out_tcon0>;
 135                                         };
 136                                 };
 137
 138                                 tcon0_out: port@1 {
 139                                         #address-cells = <1>;
 140                                         #size-cells = <0>;
 141                                         reg = <1>;
 142                                 };
 143                         };
 144                 };
 145
 146                 pwm: pwm@01c20e00 {
 147                         compatible = "allwinner,sun5i-a13-pwm";
 148                         reg = <0x01c20e00 0xc>;
 149                         clocks = <&ccu CLK_HOSC>;
 150                         #pwm-cells = <3>;
 151                         status = "disabled";
 152                 };
 153
 154                 fe0: display-frontend@01e00000 {
 155                         compatible = "allwinner,sun5i-a13-display-frontend";
 156                         reg = <0x01e00000 0x20000>;
 157                         interrupts = <47>;
 158                         clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>,
 159                                  <&ccu CLK_DRAM_DE_FE>;
 160                         clock-names = "ahb", "mod",
 161                                       "ram";
 162                         resets = <&ccu RST_DE_FE>;
 163                         status = "disabled";
 164
 165                         ports {
 166                                 #address-cells = <1>;
 167                                 #size-cells = <0>;
 168
 169                                 fe0_out: port@1 {
 170                                         #address-cells = <1>;
 171                                         #size-cells = <0>;
 172                                         reg = <1>;
 173
 174                                         fe0_out_be0: endpoint@0 {
 175                                                 reg = <0>;
 176                                                 remote-endpoint = <&be0_in_fe0>;
 177                                         };
 178                                 };
 179                         };
 180                 };
 181
 182                 be0: display-backend@01e60000 {
 183                         compatible = "allwinner,sun5i-a13-display-backend";
 184                         reg = <0x01e60000 0x10000>;
 185                         clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
 186                                  <&ccu CLK_DRAM_DE_BE>;
 187                         clock-names = "ahb", "mod",
 188                                       "ram";
 189                         resets = <&ccu RST_DE_BE>;
 190                         status = "disabled";
 191
 192                         assigned-clocks = <&ccu CLK_DE_BE>;
 193                         assigned-clock-rates = <300000000>;
 194
 195                         ports {
 196                                 #address-cells = <1>;
 197                                 #size-cells = <0>;
 198
 199                                 be0_in: port@0 {
 200                                         #address-cells = <1>;
 201                                         #size-cells = <0>;
 202                                         reg = <0>;
 203
 204                                         be0_in_fe0: endpoint@0 {
 205                                                 reg = <0>;
 206                                                 remote-endpoint = <&fe0_out_be0>;
 207                                         };
 208                                 };
 209
 210                                 be0_out: port@1 {
 211                                         #address-cells = <1>;
 212                                         #size-cells = <0>;
 213                                         reg = <1>;
 214
 215                                         be0_out_tcon0: endpoint@0 {
 216                                                 reg = <0>;
 217                                                 remote-endpoint = <&tcon0_in_be0>;
 218                                         };
 219                                 };
 220                         };
 221                 };
 222         };
 223 };
 224
 225 &ccu {
 226         compatible = "allwinner,sun5i-a13-ccu";
 227 };
 228
 229 &cpu0 {
 230         clock-latency = <244144>; /* 8 32k periods */
 231         operating-points = <
 232                 /* kHz    uV */
 233                 1008000 1400000
 234                 912000  1350000
 235                 864000  1300000
 236                 624000  1200000
 237                 576000  1200000
 238                 432000  1200000
 239                 >;
 240         #cooling-cells = <2>;
 241         cooling-min-level = <0>;
 242         cooling-max-level = <5>;
 243 };
 244
 245 &pio {
 246         compatible = "allwinner,sun5i-a13-pinctrl";
 247
 248         lcd_rgb666_pins: lcd_rgb666@0 {
 249                 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
 250                        "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
 251                        "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
 252                        "PD24", "PD25", "PD26", "PD27";
 253                 function = "lcd0";
 254         };
 255
 256         uart1_pins_a: uart1@0 {
 257                 pins = "PE10", "PE11";
 258                 function = "uart1";
 259         };
 260
 261         uart1_pins_b: uart1@1 {
 262                 pins = "PG3", "PG4";
 263                 function = "uart1";
 264         };
 265 };