arch/arm/boot/dts/stm32mp157c.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         device_type = "cpu";
  21                         reg = <0>;
  22                 };
  23
  24                 cpu1: cpu@1 {
  25                         compatible = "arm,cortex-a7";
  26                         device_type = "cpu";
  27                         reg = <1>;
  28                 };
  29         };
  30
  31         psci {
  32                 compatible = "arm,psci";
  33                 method = "smc";
  34                 cpu_off = <0x84000002>;
  35                 cpu_on = <0x84000003>;
  36         };
  37
  38         intc: interrupt-controller@a0021000 {
  39                 compatible = "arm,cortex-a7-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xa0021000 0x1000>,
  43                       <0xa0022000 0x2000>;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&intc>;
  53         };
  54
  55         clocks {
  56                 clk_hse: clk-hse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61
  62                 clk_hsi: clk-hsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <64000000>;
  66                 };
  67
  68                 clk_lse: clk-lse {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                 };
  73
  74                 clk_lsi: clk-lsi {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <32000>;
  78                 };
  79
  80                 clk_csi: clk-csi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <4000000>;
  84                 };
  85         };
  86
  87         thermal-zones {
  88                 cpu_thermal: cpu-thermal {
  89                         polling-delay-passive = <0>;
  90                         polling-delay = <0>;
  91                         thermal-sensors = <&dts>;
  92
  93                         trips {
  94                                 cpu_alert1: cpu-alert1 {
  95                                         temperature = <85000>;
  96                                         hysteresis = <0>;
  97                                         type = "passive";
  98                                 };
  99
 100                                 cpu-crit {
 101                                         temperature = <120000>;
 102                                         hysteresis = <0>;
 103                                         type = "critical";
 104                                 };
 105                         };
 106
 107                         cooling-maps {
 108                         };
 109                 };
 110         };
 111
 112         soc {
 113                 compatible = "simple-bus";
 114                 #address-cells = <1>;
 115                 #size-cells = <1>;
 116                 interrupt-parent = <&intc>;
 117                 ranges;
 118
 119                 timers2: timer@40000000 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         compatible = "st,stm32-timers";
 123                         reg = <0x40000000 0x400>;
 124                         clocks = <&rcc TIM2_K>;
 125                         clock-names = "int";
 126                         dmas = <&dmamux1 18 0x400 0x1>,
 127                                <&dmamux1 19 0x400 0x1>,
 128                                <&dmamux1 20 0x400 0x1>,
 129                                <&dmamux1 21 0x400 0x1>,
 130                                <&dmamux1 22 0x400 0x1>;
 131                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 132                         status = "disabled";
 133
 134                         pwm {
 135                                 compatible = "st,stm32-pwm";
 136                                 status = "disabled";
 137                         };
 138
 139                         timer@1 {
 140                                 compatible = "st,stm32h7-timer-trigger";
 141                                 reg = <1>;
 142                                 status = "disabled";
 143                         };
 144                 };
 145
 146                 timers3: timer@40001000 {
 147                         #address-cells = <1>;
 148                         #size-cells = <0>;
 149                         compatible = "st,stm32-timers";
 150                         reg = <0x40001000 0x400>;
 151                         clocks = <&rcc TIM3_K>;
 152                         clock-names = "int";
 153                         dmas = <&dmamux1 23 0x400 0x1>,
 154                                <&dmamux1 24 0x400 0x1>,
 155                                <&dmamux1 25 0x400 0x1>,
 156                                <&dmamux1 26 0x400 0x1>,
 157                                <&dmamux1 27 0x400 0x1>,
 158                                <&dmamux1 28 0x400 0x1>;
 159                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 160                         status = "disabled";
 161
 162                         pwm {
 163                                 compatible = "st,stm32-pwm";
 164                                 status = "disabled";
 165                         };
 166
 167                         timer@2 {
 168                                 compatible = "st,stm32h7-timer-trigger";
 169                                 reg = <2>;
 170                                 status = "disabled";
 171                         };
 172                 };
 173
 174                 timers4: timer@40002000 {
 175                         #address-cells = <1>;
 176                         #size-cells = <0>;
 177                         compatible = "st,stm32-timers";
 178                         reg = <0x40002000 0x400>;
 179                         clocks = <&rcc TIM4_K>;
 180                         clock-names = "int";
 181                         dmas = <&dmamux1 29 0x400 0x1>,
 182                                <&dmamux1 30 0x400 0x1>,
 183                                <&dmamux1 31 0x400 0x1>,
 184                                <&dmamux1 32 0x400 0x1>;
 185                         dma-names = "ch1", "ch2", "ch3", "ch4";
 186                         status = "disabled";
 187
 188                         pwm {
 189                                 compatible = "st,stm32-pwm";
 190                                 status = "disabled";
 191                         };
 192
 193                         timer@3 {
 194                                 compatible = "st,stm32h7-timer-trigger";
 195                                 reg = <3>;
 196                                 status = "disabled";
 197                         };
 198                 };
 199
 200                 timers5: timer@40003000 {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203                         compatible = "st,stm32-timers";
 204                         reg = <0x40003000 0x400>;
 205                         clocks = <&rcc TIM5_K>;
 206                         clock-names = "int";
 207                         dmas = <&dmamux1 55 0x400 0x1>,
 208                                <&dmamux1 56 0x400 0x1>,
 209                                <&dmamux1 57 0x400 0x1>,
 210                                <&dmamux1 58 0x400 0x1>,
 211                                <&dmamux1 59 0x400 0x1>,
 212                                <&dmamux1 60 0x400 0x1>;
 213                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 214                         status = "disabled";
 215
 216                         pwm {
 217                                 compatible = "st,stm32-pwm";
 218                                 status = "disabled";
 219                         };
 220
 221                         timer@4 {
 222                                 compatible = "st,stm32h7-timer-trigger";
 223                                 reg = <4>;
 224                                 status = "disabled";
 225                         };
 226                 };
 227
 228                 timers6: timer@40004000 {
 229                         #address-cells = <1>;
 230                         #size-cells = <0>;
 231                         compatible = "st,stm32-timers";
 232                         reg = <0x40004000 0x400>;
 233                         clocks = <&rcc TIM6_K>;
 234                         clock-names = "int";
 235                         dmas = <&dmamux1 69 0x400 0x1>;
 236                         dma-names = "up";
 237                         status = "disabled";
 238
 239                         timer@5 {
 240                                 compatible = "st,stm32h7-timer-trigger";
 241                                 reg = <5>;
 242                                 status = "disabled";
 243                         };
 244                 };
 245
 246                 timers7: timer@40005000 {
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         compatible = "st,stm32-timers";
 250                         reg = <0x40005000 0x400>;
 251                         clocks = <&rcc TIM7_K>;
 252                         clock-names = "int";
 253                         dmas = <&dmamux1 70 0x400 0x1>;
 254                         dma-names = "up";
 255                         status = "disabled";
 256
 257                         timer@6 {
 258                                 compatible = "st,stm32h7-timer-trigger";
 259                                 reg = <6>;
 260                                 status = "disabled";
 261                         };
 262                 };
 263
 264                 timers12: timer@40006000 {
 265                         #address-cells = <1>;
 266                         #size-cells = <0>;
 267                         compatible = "st,stm32-timers";
 268                         reg = <0x40006000 0x400>;
 269                         clocks = <&rcc TIM12_K>;
 270                         clock-names = "int";
 271                         status = "disabled";
 272
 273                         pwm {
 274                                 compatible = "st,stm32-pwm";
 275                                 status = "disabled";
 276                         };
 277
 278                         timer@11 {
 279                                 compatible = "st,stm32h7-timer-trigger";
 280                                 reg = <11>;
 281                                 status = "disabled";
 282                         };
 283                 };
 284
 285                 timers13: timer@40007000 {
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         compatible = "st,stm32-timers";
 289                         reg = <0x40007000 0x400>;
 290                         clocks = <&rcc TIM13_K>;
 291                         clock-names = "int";
 292                         status = "disabled";
 293
 294                         pwm {
 295                                 compatible = "st,stm32-pwm";
 296                                 status = "disabled";
 297                         };
 298
 299                         timer@12 {
 300                                 compatible = "st,stm32h7-timer-trigger";
 301                                 reg = <12>;
 302                                 status = "disabled";
 303                         };
 304                 };
 305
 306                 timers14: timer@40008000 {
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         compatible = "st,stm32-timers";
 310                         reg = <0x40008000 0x400>;
 311                         clocks = <&rcc TIM14_K>;
 312                         clock-names = "int";
 313                         status = "disabled";
 314
 315                         pwm {
 316                                 compatible = "st,stm32-pwm";
 317                                 status = "disabled";
 318                         };
 319
 320                         timer@13 {
 321                                 compatible = "st,stm32h7-timer-trigger";
 322                                 reg = <13>;
 323                                 status = "disabled";
 324                         };
 325                 };
 326
 327                 lptimer1: timer@40009000 {
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         compatible = "st,stm32-lptimer";
 331                         reg = <0x40009000 0x400>;
 332                         clocks = <&rcc LPTIM1_K>;
 333                         clock-names = "mux";
 334                         status = "disabled";
 335
 336                         pwm {
 337                                 compatible = "st,stm32-pwm-lp";
 338                                 #pwm-cells = <3>;
 339                                 status = "disabled";
 340                         };
 341
 342                         trigger@0 {
 343                                 compatible = "st,stm32-lptimer-trigger";
 344                                 reg = <0>;
 345                                 status = "disabled";
 346                         };
 347
 348                         counter {
 349                                 compatible = "st,stm32-lptimer-counter";
 350                                 status = "disabled";
 351                         };
 352                 };
 353
 354                 spi2: spi@4000b000 {
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         compatible = "st,stm32h7-spi";
 358                         reg = <0x4000b000 0x400>;
 359                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 360                         clocks = <&rcc SPI2_K>;
 361                         resets = <&rcc SPI2_R>;
 362                         dmas = <&dmamux1 39 0x400 0x05>,
 363                                <&dmamux1 40 0x400 0x05>;
 364                         dma-names = "rx", "tx";
 365                         status = "disabled";
 366                 };
 367
 368                 spi3: spi@4000c000 {
 369                         #address-cells = <1>;
 370                         #size-cells = <0>;
 371                         compatible = "st,stm32h7-spi";
 372                         reg = <0x4000c000 0x400>;
 373                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&rcc SPI3_K>;
 375                         resets = <&rcc SPI3_R>;
 376                         dmas = <&dmamux1 61 0x400 0x05>,
 377                                <&dmamux1 62 0x400 0x05>;
 378                         dma-names = "rx", "tx";
 379                         status = "disabled";
 380                 };
 381
 382                 spdifrx: audio-controller@4000d000 {
 383                         compatible = "st,stm32h7-spdifrx";
 384                         #sound-dai-cells = <0>;
 385                         reg = <0x4000d000 0x400>;
 386                         clocks = <&rcc SPDIF_K>;
 387                         clock-names = "kclk";
 388                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 389                         dmas = <&dmamux1 93 0x400 0x01>,
 390                                <&dmamux1 94 0x400 0x01>;
 391                         dma-names = "rx", "rx-ctrl";
 392                         status = "disabled";
 393                 };
 394
 395                 usart2: serial@4000e000 {
 396                         compatible = "st,stm32h7-uart";
 397                         reg = <0x4000e000 0x400>;
 398                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 399                         clocks = <&rcc USART2_K>;
 400                         status = "disabled";
 401                 };
 402
 403                 usart3: serial@4000f000 {
 404                         compatible = "st,stm32h7-uart";
 405                         reg = <0x4000f000 0x400>;
 406                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&rcc USART3_K>;
 408                         status = "disabled";
 409                 };
 410
 411                 uart4: serial@40010000 {
 412                         compatible = "st,stm32h7-uart";
 413                         reg = <0x40010000 0x400>;
 414                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 415                         clocks = <&rcc UART4_K>;
 416                         status = "disabled";
 417                 };
 418
 419                 uart5: serial@40011000 {
 420                         compatible = "st,stm32h7-uart";
 421                         reg = <0x40011000 0x400>;
 422                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 423                         clocks = <&rcc UART5_K>;
 424                         status = "disabled";
 425                 };
 426
 427                 i2c1: i2c@40012000 {
 428                         compatible = "st,stm32f7-i2c";
 429                         reg = <0x40012000 0x400>;
 430                         interrupt-names = "event", "error";
 431                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 432                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&rcc I2C1_K>;
 434                         resets = <&rcc I2C1_R>;
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         status = "disabled";
 438                 };
 439
 440                 i2c2: i2c@40013000 {
 441                         compatible = "st,stm32f7-i2c";
 442                         reg = <0x40013000 0x400>;
 443                         interrupt-names = "event", "error";
 444                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 445                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 446                         clocks = <&rcc I2C2_K>;
 447                         resets = <&rcc I2C2_R>;
 448                         #address-cells = <1>;
 449                         #size-cells = <0>;
 450                         status = "disabled";
 451                 };
 452
 453                 i2c3: i2c@40014000 {
 454                         compatible = "st,stm32f7-i2c";
 455                         reg = <0x40014000 0x400>;
 456                         interrupt-names = "event", "error";
 457                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 458                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 459                         clocks = <&rcc I2C3_K>;
 460                         resets = <&rcc I2C3_R>;
 461                         #address-cells = <1>;
 462                         #size-cells = <0>;
 463                         status = "disabled";
 464                 };
 465
 466                 i2c5: i2c@40015000 {
 467                         compatible = "st,stm32f7-i2c";
 468                         reg = <0x40015000 0x400>;
 469                         interrupt-names = "event", "error";
 470                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 471                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 472                         clocks = <&rcc I2C5_K>;
 473                         resets = <&rcc I2C5_R>;
 474                         #address-cells = <1>;
 475                         #size-cells = <0>;
 476                         status = "disabled";
 477                 };
 478
 479                 cec: cec@40016000 {
 480                         compatible = "st,stm32-cec";
 481                         reg = <0x40016000 0x400>;
 482                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 483                         clocks = <&rcc CEC_K>, <&clk_lse>;
 484                         clock-names = "cec", "hdmi-cec";
 485                         status = "disabled";
 486                 };
 487
 488                 dac: dac@40017000 {
 489                         compatible = "st,stm32h7-dac-core";
 490                         reg = <0x40017000 0x400>;
 491                         clocks = <&rcc DAC12>;
 492                         clock-names = "pclk";
 493                         #address-cells = <1>;
 494                         #size-cells = <0>;
 495                         status = "disabled";
 496
 497                         dac1: dac@1 {
 498                                 compatible = "st,stm32-dac";
 499                                 #io-channels-cells = <1>;
 500                                 reg = <1>;
 501                                 status = "disabled";
 502                         };
 503
 504                         dac2: dac@2 {
 505                                 compatible = "st,stm32-dac";
 506                                 #io-channels-cells = <1>;
 507                                 reg = <2>;
 508                                 status = "disabled";
 509                         };
 510                 };
 511
 512                 uart7: serial@40018000 {
 513                         compatible = "st,stm32h7-uart";
 514                         reg = <0x40018000 0x400>;
 515                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&rcc UART7_K>;
 517                         status = "disabled";
 518                 };
 519
 520                 uart8: serial@40019000 {
 521                         compatible = "st,stm32h7-uart";
 522                         reg = <0x40019000 0x400>;
 523                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 524                         clocks = <&rcc UART8_K>;
 525                         status = "disabled";
 526                 };
 527
 528                 timers1: timer@44000000 {
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         compatible = "st,stm32-timers";
 532                         reg = <0x44000000 0x400>;
 533                         clocks = <&rcc TIM1_K>;
 534                         clock-names = "int";
 535                         dmas = <&dmamux1 11 0x400 0x1>,
 536                                <&dmamux1 12 0x400 0x1>,
 537                                <&dmamux1 13 0x400 0x1>,
 538                                <&dmamux1 14 0x400 0x1>,
 539                                <&dmamux1 15 0x400 0x1>,
 540                                <&dmamux1 16 0x400 0x1>,
 541                                <&dmamux1 17 0x400 0x1>;
 542                         dma-names = "ch1", "ch2", "ch3", "ch4",
 543                                     "up", "trig", "com";
 544                         status = "disabled";
 545
 546                         pwm {
 547                                 compatible = "st,stm32-pwm";
 548                                 status = "disabled";
 549                         };
 550
 551                         timer@0 {
 552                                 compatible = "st,stm32h7-timer-trigger";
 553                                 reg = <0>;
 554                                 status = "disabled";
 555                         };
 556                 };
 557
 558                 timers8: timer@44001000 {
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         compatible = "st,stm32-timers";
 562                         reg = <0x44001000 0x400>;
 563                         clocks = <&rcc TIM8_K>;
 564                         clock-names = "int";
 565                         dmas = <&dmamux1 47 0x400 0x1>,
 566                                <&dmamux1 48 0x400 0x1>,
 567                                <&dmamux1 49 0x400 0x1>,
 568                                <&dmamux1 50 0x400 0x1>,
 569                                <&dmamux1 51 0x400 0x1>,
 570                                <&dmamux1 52 0x400 0x1>,
 571                                <&dmamux1 53 0x400 0x1>;
 572                         dma-names = "ch1", "ch2", "ch3", "ch4",
 573                                     "up", "trig", "com";
 574                         status = "disabled";
 575
 576                         pwm {
 577                                 compatible = "st,stm32-pwm";
 578                                 status = "disabled";
 579                         };
 580
 581                         timer@7 {
 582                                 compatible = "st,stm32h7-timer-trigger";
 583                                 reg = <7>;
 584                                 status = "disabled";
 585                         };
 586                 };
 587
 588                 usart6: serial@44003000 {
 589                         compatible = "st,stm32h7-uart";
 590                         reg = <0x44003000 0x400>;
 591                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 592                         clocks = <&rcc USART6_K>;
 593                         status = "disabled";
 594                 };
 595
 596                 spi1: spi@44004000 {
 597                         #address-cells = <1>;
 598                         #size-cells = <0>;
 599                         compatible = "st,stm32h7-spi";
 600                         reg = <0x44004000 0x400>;
 601                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 602                         clocks = <&rcc SPI1_K>;
 603                         resets = <&rcc SPI1_R>;
 604                         dmas = <&dmamux1 37 0x400 0x05>,
 605                                <&dmamux1 38 0x400 0x05>;
 606                         dma-names = "rx", "tx";
 607                         status = "disabled";
 608                 };
 609
 610                 spi4: spi@44005000 {
 611                         #address-cells = <1>;
 612                         #size-cells = <0>;
 613                         compatible = "st,stm32h7-spi";
 614                         reg = <0x44005000 0x400>;
 615                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 616                         clocks = <&rcc SPI4_K>;
 617                         resets = <&rcc SPI4_R>;
 618                         dmas = <&dmamux1 83 0x400 0x05>,
 619                                <&dmamux1 84 0x400 0x05>;
 620                         dma-names = "rx", "tx";
 621                         status = "disabled";
 622                 };
 623
 624                 timers15: timer@44006000 {
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         compatible = "st,stm32-timers";
 628                         reg = <0x44006000 0x400>;
 629                         clocks = <&rcc TIM15_K>;
 630                         clock-names = "int";
 631                         dmas = <&dmamux1 105 0x400 0x1>,
 632                                <&dmamux1 106 0x400 0x1>,
 633                                <&dmamux1 107 0x400 0x1>,
 634                                <&dmamux1 108 0x400 0x1>;
 635                         dma-names = "ch1", "up", "trig", "com";
 636                         status = "disabled";
 637
 638                         pwm {
 639                                 compatible = "st,stm32-pwm";
 640                                 status = "disabled";
 641                         };
 642
 643                         timer@14 {
 644                                 compatible = "st,stm32h7-timer-trigger";
 645                                 reg = <14>;
 646                                 status = "disabled";
 647                         };
 648                 };
 649
 650                 timers16: timer@44007000 {
 651                         #address-cells = <1>;
 652                         #size-cells = <0>;
 653                         compatible = "st,stm32-timers";
 654                         reg = <0x44007000 0x400>;
 655                         clocks = <&rcc TIM16_K>;
 656                         clock-names = "int";
 657                         dmas = <&dmamux1 109 0x400 0x1>,
 658                                <&dmamux1 110 0x400 0x1>;
 659                         dma-names = "ch1", "up";
 660                         status = "disabled";
 661
 662                         pwm {
 663                                 compatible = "st,stm32-pwm";
 664                                 status = "disabled";
 665                         };
 666                         timer@15 {
 667                                 compatible = "st,stm32h7-timer-trigger";
 668                                 reg = <15>;
 669                                 status = "disabled";
 670                         };
 671                 };
 672
 673                 timers17: timer@44008000 {
 674                         #address-cells = <1>;
 675                         #size-cells = <0>;
 676                         compatible = "st,stm32-timers";
 677                         reg = <0x44008000 0x400>;
 678                         clocks = <&rcc TIM17_K>;
 679                         clock-names = "int";
 680                         dmas = <&dmamux1 111 0x400 0x1>,
 681                                <&dmamux1 112 0x400 0x1>;
 682                         dma-names = "ch1", "up";
 683                         status = "disabled";
 684
 685                         pwm {
 686                                 compatible = "st,stm32-pwm";
 687                                 status = "disabled";
 688                         };
 689
 690                         timer@16 {
 691                                 compatible = "st,stm32h7-timer-trigger";
 692                                 reg = <16>;
 693                                 status = "disabled";
 694                         };
 695                 };
 696
 697                 spi5: spi@44009000 {
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                         compatible = "st,stm32h7-spi";
 701                         reg = <0x44009000 0x400>;
 702                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 703                         clocks = <&rcc SPI5_K>;
 704                         resets = <&rcc SPI5_R>;
 705                         dmas = <&dmamux1 85 0x400 0x05>,
 706                                <&dmamux1 86 0x400 0x05>;
 707                         dma-names = "rx", "tx";
 708                         status = "disabled";
 709                 };
 710
 711                 dfsdm: dfsdm@4400d000 {
 712                         compatible = "st,stm32mp1-dfsdm";
 713                         reg = <0x4400d000 0x800>;
 714                         clocks = <&rcc DFSDM_K>;
 715                         clock-names = "dfsdm";
 716                         #address-cells = <1>;
 717                         #size-cells = <0>;
 718                         status = "disabled";
 719
 720                         dfsdm0: filter@0 {
 721                                 compatible = "st,stm32-dfsdm-adc";
 722                                 #io-channel-cells = <1>;
 723                                 reg = <0>;
 724                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 725                                 dmas = <&dmamux1 101 0x400 0x01>;
 726                                 dma-names = "rx";
 727                                 status = "disabled";
 728                         };
 729
 730                         dfsdm1: filter@1 {
 731                                 compatible = "st,stm32-dfsdm-adc";
 732                                 #io-channel-cells = <1>;
 733                                 reg = <1>;
 734                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 735                                 dmas = <&dmamux1 102 0x400 0x01>;
 736                                 dma-names = "rx";
 737                                 status = "disabled";
 738                         };
 739
 740                         dfsdm2: filter@2 {
 741                                 compatible = "st,stm32-dfsdm-adc";
 742                                 #io-channel-cells = <1>;
 743                                 reg = <2>;
 744                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 745                                 dmas = <&dmamux1 103 0x400 0x01>;
 746                                 dma-names = "rx";
 747                                 status = "disabled";
 748                         };
 749
 750                         dfsdm3: filter@3 {
 751                                 compatible = "st,stm32-dfsdm-adc";
 752                                 #io-channel-cells = <1>;
 753                                 reg = <3>;
 754                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 755                                 dmas = <&dmamux1 104 0x400 0x01>;
 756                                 dma-names = "rx";
 757                                 status = "disabled";
 758                         };
 759
 760                         dfsdm4: filter@4 {
 761                                 compatible = "st,stm32-dfsdm-adc";
 762                                 #io-channel-cells = <1>;
 763                                 reg = <4>;
 764                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 765                                 dmas = <&dmamux1 91 0x400 0x01>;
 766                                 dma-names = "rx";
 767                                 status = "disabled";
 768                         };
 769
 770                         dfsdm5: filter@5 {
 771                                 compatible = "st,stm32-dfsdm-adc";
 772                                 #io-channel-cells = <1>;
 773                                 reg = <5>;
 774                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 775                                 dmas = <&dmamux1 92 0x400 0x01>;
 776                                 dma-names = "rx";
 777                                 status = "disabled";
 778                         };
 779                 };
 780
 781                 m_can1: can@4400e000 {
 782                         compatible = "bosch,m_can";
 783                         reg = <0x4400e000 0x400>, <0x44011000 0x1400>;
 784                         reg-names = "m_can", "message_ram";
 785                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 786                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 787                         interrupt-names = "int0", "int1";
 788                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 789                         clock-names = "hclk", "cclk";
 790                         bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
 791                         status = "disabled";
 792                 };
 793
 794                 m_can2: can@4400f000 {
 795                         compatible = "bosch,m_can";
 796                         reg = <0x4400f000 0x400>, <0x44011000 0x2800>;
 797                         reg-names = "m_can", "message_ram";
 798                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 799                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 800                         interrupt-names = "int0", "int1";
 801                         clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
 802                         clock-names = "hclk", "cclk";
 803                         bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
 804                         status = "disabled";
 805                 };
 806
 807                 dma1: dma@48000000 {
 808                         compatible = "st,stm32-dma";
 809                         reg = <0x48000000 0x400>;
 810                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 811                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 812                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 813                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 814                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 815                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 816                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
 817                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 818                         clocks = <&rcc DMA1>;
 819                         #dma-cells = <4>;
 820                         st,mem2mem;
 821                         dma-requests = <8>;
 822                 };
 823
 824                 dma2: dma@48001000 {
 825                         compatible = "st,stm32-dma";
 826                         reg = <0x48001000 0x400>;
 827                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 828                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 829                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 830                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 831                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 832                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 833                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 834                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 835                         clocks = <&rcc DMA2>;
 836                         #dma-cells = <4>;
 837                         st,mem2mem;
 838                         dma-requests = <8>;
 839                 };
 840
 841                 dmamux1: dma-router@48002000 {
 842                         compatible = "st,stm32h7-dmamux";
 843                         reg = <0x48002000 0x1c>;
 844                         #dma-cells = <3>;
 845                         dma-requests = <128>;
 846                         dma-masters = <&dma1 &dma2>;
 847                         dma-channels = <16>;
 848                         clocks = <&rcc DMAMUX>;
 849                 };
 850
 851                 adc: adc@48003000 {
 852                         compatible = "st,stm32mp1-adc-core";
 853                         reg = <0x48003000 0x400>;
 854                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 855                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 856                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
 857                         clock-names = "bus", "adc";
 858                         interrupt-controller;
 859                         #interrupt-cells = <1>;
 860                         #address-cells = <1>;
 861                         #size-cells = <0>;
 862                         status = "disabled";
 863
 864                         adc1: adc@0 {
 865                                 compatible = "st,stm32mp1-adc";
 866                                 #io-channel-cells = <1>;
 867                                 reg = <0x0>;
 868                                 interrupt-parent = <&adc>;
 869                                 interrupts = <0>;
 870                                 dmas = <&dmamux1 9 0x400 0x01>;
 871                                 dma-names = "rx";
 872                                 status = "disabled";
 873                         };
 874
 875                         adc2: adc@100 {
 876                                 compatible = "st,stm32mp1-adc";
 877                                 #io-channel-cells = <1>;
 878                                 reg = <0x100>;
 879                                 interrupt-parent = <&adc>;
 880                                 interrupts = <1>;
 881                                 dmas = <&dmamux1 10 0x400 0x01>;
 882                                 dma-names = "rx";
 883                                 status = "disabled";
 884                         };
 885                 };
 886
 887                 usbotg_hs: usb-otg@49000000 {
 888                         compatible = "snps,dwc2";
 889                         reg = <0x49000000 0x10000>;
 890                         clocks = <&rcc USBO_K>;
 891                         clock-names = "otg";
 892                         resets = <&rcc USBO_R>;
 893                         reset-names = "dwc2";
 894                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 895                         g-rx-fifo-size = <256>;
 896                         g-np-tx-fifo-size = <32>;
 897                         g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
 898                         dr_mode = "otg";
 899                         status = "disabled";
 900                 };
 901
 902                 ipcc: mailbox@4c001000 {
 903                         compatible = "st,stm32mp1-ipcc";
 904                         #mbox-cells = <1>;
 905                         reg = <0x4c001000 0x400>;
 906                         st,proc-id = <0>;
 907                         interrupts-extended =
 908                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 909                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 910                                 <&exti 61 1>;
 911                         interrupt-names = "rx", "tx", "wakeup";
 912                         clocks = <&rcc IPCC>;
 913                         wakeup-source;
 914                         status = "disabled";
 915                 };
 916
 917                 rcc: rcc@50000000 {
 918                         compatible = "st,stm32mp1-rcc", "syscon";
 919                         reg = <0x50000000 0x1000>;
 920                         #clock-cells = <1>;
 921                         #reset-cells = <1>;
 922                 };
 923
 924                 exti: interrupt-controller@5000d000 {
 925                         compatible = "st,stm32mp1-exti", "syscon";
 926                         interrupt-controller;
 927                         #interrupt-cells = <2>;
 928                         reg = <0x5000d000 0x400>;
 929                 };
 930
 931                 syscfg: syscon@50020000 {
 932                         compatible = "st,stm32mp157-syscfg", "syscon";
 933                         reg = <0x50020000 0x400>;
 934                         clocks = <&rcc SYSCFG>;
 935                 };
 936
 937                 lptimer2: timer@50021000 {
 938                         #address-cells = <1>;
 939                         #size-cells = <0>;
 940                         compatible = "st,stm32-lptimer";
 941                         reg = <0x50021000 0x400>;
 942                         clocks = <&rcc LPTIM2_K>;
 943                         clock-names = "mux";
 944                         status = "disabled";
 945
 946                         pwm {
 947                                 compatible = "st,stm32-pwm-lp";
 948                                 #pwm-cells = <3>;
 949                                 status = "disabled";
 950                         };
 951
 952                         trigger@1 {
 953                                 compatible = "st,stm32-lptimer-trigger";
 954                                 reg = <1>;
 955                                 status = "disabled";
 956                         };
 957
 958                         counter {
 959                                 compatible = "st,stm32-lptimer-counter";
 960                                 status = "disabled";
 961                         };
 962                 };
 963
 964                 lptimer3: timer@50022000 {
 965                         #address-cells = <1>;
 966                         #size-cells = <0>;
 967                         compatible = "st,stm32-lptimer";
 968                         reg = <0x50022000 0x400>;
 969                         clocks = <&rcc LPTIM3_K>;
 970                         clock-names = "mux";
 971                         status = "disabled";
 972
 973                         pwm {
 974                                 compatible = "st,stm32-pwm-lp";
 975                                 #pwm-cells = <3>;
 976                                 status = "disabled";
 977                         };
 978
 979                         trigger@2 {
 980                                 compatible = "st,stm32-lptimer-trigger";
 981                                 reg = <2>;
 982                                 status = "disabled";
 983                         };
 984                 };
 985
 986                 lptimer4: timer@50023000 {
 987                         compatible = "st,stm32-lptimer";
 988                         reg = <0x50023000 0x400>;
 989                         clocks = <&rcc LPTIM4_K>;
 990                         clock-names = "mux";
 991                         status = "disabled";
 992
 993                         pwm {
 994                                 compatible = "st,stm32-pwm-lp";
 995                                 #pwm-cells = <3>;
 996                                 status = "disabled";
 997                         };
 998                 };
 999
1000                 lptimer5: timer@50024000 {
1001                         compatible = "st,stm32-lptimer";
1002                         reg = <0x50024000 0x400>;
1003                         clocks = <&rcc LPTIM5_K>;
1004                         clock-names = "mux";
1005                         status = "disabled";
1006
1007                         pwm {
1008                                 compatible = "st,stm32-pwm-lp";
1009                                 #pwm-cells = <3>;
1010                                 status = "disabled";
1011                         };
1012                 };
1013
1014                 vrefbuf: vrefbuf@50025000 {
1015                         compatible = "st,stm32-vrefbuf";
1016                         reg = <0x50025000 0x8>;
1017                         regulator-min-microvolt = <1500000>;
1018                         regulator-max-microvolt = <2500000>;
1019                         clocks = <&rcc VREF>;
1020                         status = "disabled";
1021                 };
1022
1023                 dts: thermal@50028000 {
1024                         compatible = "st,stm32-thermal";
1025                         reg = <0x50028000 0x100>;
1026                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1027                         clocks = <&rcc TMPSENS>;
1028                         clock-names = "pclk";
1029                         #thermal-sensor-cells = <0>;
1030                         status = "disabled";
1031                 };
1032
1033                 cryp1: cryp@54001000 {
1034                         compatible = "st,stm32mp1-cryp";
1035                         reg = <0x54001000 0x400>;
1036                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1037                         clocks = <&rcc CRYP1>;
1038                         resets = <&rcc CRYP1_R>;
1039                         status = "disabled";
1040                 };
1041
1042                 hash1: hash@54002000 {
1043                         compatible = "st,stm32f756-hash";
1044                         reg = <0x54002000 0x400>;
1045                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1046                         clocks = <&rcc HASH1>;
1047                         resets = <&rcc HASH1_R>;
1048                         dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1049                         dma-names = "in";
1050                         dma-maxburst = <2>;
1051                         status = "disabled";
1052                 };
1053
1054                 rng1: rng@54003000 {
1055                         compatible = "st,stm32-rng";
1056                         reg = <0x54003000 0x400>;
1057                         clocks = <&rcc RNG1_K>;
1058                         resets = <&rcc RNG1_R>;
1059                         status = "disabled";
1060                 };
1061
1062                 mdma1: dma@58000000 {
1063                         compatible = "st,stm32h7-mdma";
1064                         reg = <0x58000000 0x1000>;
1065                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1066                         clocks = <&rcc MDMA>;
1067                         #dma-cells = <5>;
1068                         dma-channels = <32>;
1069                         dma-requests = <48>;
1070                 };
1071
1072                 qspi: spi@58003000 {
1073                         compatible = "st,stm32f469-qspi";
1074                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1075                         reg-names = "qspi", "qspi_mm";
1076                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1077                         clocks = <&rcc QSPI_K>;
1078                         resets = <&rcc QSPI_R>;
1079                         status = "disabled";
1080                 };
1081
1082                 sdmmc1: sdmmc@58005000 {
1083                         compatible = "arm,pl18x", "arm,primecell";
1084                         arm,primecell-periphid = <0x10153180>;
1085                         reg = <0x58005000 0x1000>;
1086                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1087                         interrupt-names = "cmd_irq";
1088                         clocks = <&rcc SDMMC1_K>;
1089                         clock-names = "apb_pclk";
1090                         resets = <&rcc SDMMC1_R>;
1091                         cap-sd-highspeed;
1092                         cap-mmc-highspeed;
1093                         max-frequency = <120000000>;
1094                 };
1095
1096                 crc1: crc@58009000 {
1097                         compatible = "st,stm32f7-crc";
1098                         reg = <0x58009000 0x400>;
1099                         clocks = <&rcc CRC1>;
1100                         status = "disabled";
1101                 };
1102
1103                 stmmac_axi_config_0: stmmac-axi-config {
1104                         snps,wr_osr_lmt = <0x7>;
1105                         snps,rd_osr_lmt = <0x7>;
1106                         snps,blen = <0 0 0 0 16 8 4>;
1107                 };
1108
1109                 ethernet0: ethernet@5800a000 {
1110                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1111                         reg = <0x5800a000 0x2000>;
1112                         reg-names = "stmmaceth";
1113                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1114                         interrupt-names = "macirq";
1115                         clock-names = "stmmaceth",
1116                                       "mac-clk-tx",
1117                                       "mac-clk-rx",
1118                                       "ethstp",
1119                                       "syscfg-clk";
1120                         clocks = <&rcc ETHMAC>,
1121                                  <&rcc ETHTX>,
1122                                  <&rcc ETHRX>,
1123                                  <&rcc ETHSTP>,
1124                                  <&rcc SYSCFG>;
1125                         st,syscon = <&syscfg 0x4>;
1126                         snps,mixed-burst;
1127                         snps,pbl = <2>;
1128                         snps,axi-config = <&stmmac_axi_config_0>;
1129                         snps,tso;
1130                         status = "disabled";
1131                 };
1132
1133                 usbh_ohci: usbh-ohci@5800c000 {
1134                         compatible = "generic-ohci";
1135                         reg = <0x5800c000 0x1000>;
1136                         clocks = <&rcc USBH>;
1137                         resets = <&rcc USBH_R>;
1138                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1139                         status = "disabled";
1140                 };
1141
1142                 usbh_ehci: usbh-ehci@5800d000 {
1143                         compatible = "generic-ehci";
1144                         reg = <0x5800d000 0x1000>;
1145                         clocks = <&rcc USBH>;
1146                         resets = <&rcc USBH_R>;
1147                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1148                         companion = <&usbh_ohci>;
1149                         status = "disabled";
1150                 };
1151
1152                 dsi: dsi@5a000000 {
1153                         compatible = "st,stm32-dsi";
1154                         reg = <0x5a000000 0x800>;
1155                         clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
1156                         clock-names = "pclk", "ref", "px_clk";
1157                         resets = <&rcc DSI_R>;
1158                         reset-names = "apb";
1159                         status = "disabled";
1160                 };
1161
1162                 ltdc: display-controller@5a001000 {
1163                         compatible = "st,stm32-ltdc";
1164                         reg = <0x5a001000 0x400>;
1165                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1166                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1167                         clocks = <&rcc LTDC_PX>;
1168                         clock-names = "lcd";
1169                         resets = <&rcc LTDC_R>;
1170                         status = "disabled";
1171                 };
1172
1173                 iwdg2: watchdog@5a002000 {
1174                         compatible = "st,stm32mp1-iwdg";
1175                         reg = <0x5a002000 0x400>;
1176                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1177                         clock-names = "pclk", "lsi";
1178                         status = "disabled";
1179                 };
1180
1181                 usbphyc: usbphyc@5a006000 {
1182                         #address-cells = <1>;
1183                         #size-cells = <0>;
1184                         compatible = "st,stm32mp1-usbphyc";
1185                         reg = <0x5a006000 0x1000>;
1186                         clocks = <&rcc USBPHY_K>;
1187                         resets = <&rcc USBPHY_R>;
1188                         status = "disabled";
1189
1190                         usbphyc_port0: usb-phy@0 {
1191                                 #phy-cells = <0>;
1192                                 reg = <0>;
1193                         };
1194
1195                         usbphyc_port1: usb-phy@1 {
1196                                 #phy-cells = <1>;
1197                                 reg = <1>;
1198                         };
1199                 };
1200
1201                 usart1: serial@5c000000 {
1202                         compatible = "st,stm32h7-uart";
1203                         reg = <0x5c000000 0x400>;
1204                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1205                         clocks = <&rcc USART1_K>;
1206                         status = "disabled";
1207                 };
1208
1209                 spi6: spi@5c001000 {
1210                         #address-cells = <1>;
1211                         #size-cells = <0>;
1212                         compatible = "st,stm32h7-spi";
1213                         reg = <0x5c001000 0x400>;
1214                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1215                         clocks = <&rcc SPI6_K>;
1216                         resets = <&rcc SPI6_R>;
1217                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1218                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1219                         dma-names = "rx", "tx";
1220                         status = "disabled";
1221                 };
1222
1223                 i2c4: i2c@5c002000 {
1224                         compatible = "st,stm32f7-i2c";
1225                         reg = <0x5c002000 0x400>;
1226                         interrupt-names = "event", "error";
1227                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1228                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1229                         clocks = <&rcc I2C4_K>;
1230                         resets = <&rcc I2C4_R>;
1231                         #address-cells = <1>;
1232                         #size-cells = <0>;
1233                         status = "disabled";
1234                 };
1235
1236                 rtc: rtc@5c004000 {
1237                         compatible = "st,stm32mp1-rtc";
1238                         reg = <0x5c004000 0x400>;
1239                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1240                         clock-names = "pclk", "rtc_ck";
1241                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1242                         status = "disabled";
1243                 };
1244
1245                 bsec: nvmem@5c005000 {
1246                         compatible = "st,stm32mp15-bsec";
1247                         reg = <0x5c005000 0x400>;
1248                         #address-cells = <1>;
1249                         #size-cells = <1>;
1250                         ts_cal1: calib@5c {
1251                                 reg = <0x5c 0x2>;
1252                         };
1253                         ts_cal2: calib@5e {
1254                                 reg = <0x5e 0x2>;
1255                         };
1256                 };
1257
1258                 i2c6: i2c@5c009000 {
1259                         compatible = "st,stm32f7-i2c";
1260                         reg = <0x5c009000 0x400>;
1261                         interrupt-names = "event", "error";
1262                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1263                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1264                         clocks = <&rcc I2C6_K>;
1265                         resets = <&rcc I2C6_R>;
1266                         #address-cells = <1>;
1267                         #size-cells = <0>;
1268                         status = "disabled";
1269                 };
1270         };
1271 };