1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/pinctrl/stm32-pinfunc.h>
10 pinctrl: pin-controller@50002000 {
13 compatible = "st,stm32mp157-pinctrl";
14 ranges = <0 0x50002000 0xa400>;
15 interrupt-parent = <&exti>;
16 st,syscfg = <&exti 0x60 0xff>;
19 gpioa: gpio@50002000 {
23 #interrupt-cells = <2>;
25 clocks = <&rcc GPIOA>;
26 st,bank-name = "GPIOA";
28 gpio-ranges = <&pinctrl 0 0 16>;
32 gpiob: gpio@50003000 {
36 #interrupt-cells = <2>;
38 clocks = <&rcc GPIOB>;
39 st,bank-name = "GPIOB";
41 gpio-ranges = <&pinctrl 0 16 16>;
45 gpioc: gpio@50004000 {
49 #interrupt-cells = <2>;
51 clocks = <&rcc GPIOC>;
52 st,bank-name = "GPIOC";
54 gpio-ranges = <&pinctrl 0 32 16>;
58 gpiod: gpio@50005000 {
62 #interrupt-cells = <2>;
64 clocks = <&rcc GPIOD>;
65 st,bank-name = "GPIOD";
67 gpio-ranges = <&pinctrl 0 48 16>;
71 gpioe: gpio@50006000 {
75 #interrupt-cells = <2>;
77 clocks = <&rcc GPIOE>;
78 st,bank-name = "GPIOE";
80 gpio-ranges = <&pinctrl 0 64 16>;
84 gpiof: gpio@50007000 {
88 #interrupt-cells = <2>;
90 clocks = <&rcc GPIOF>;
91 st,bank-name = "GPIOF";
93 gpio-ranges = <&pinctrl 0 80 16>;
97 gpiog: gpio@50008000 {
100 interrupt-controller;
101 #interrupt-cells = <2>;
102 reg = <0x6000 0x400>;
103 clocks = <&rcc GPIOG>;
104 st,bank-name = "GPIOG";
106 gpio-ranges = <&pinctrl 0 96 16>;
110 gpioh: gpio@50009000 {
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 reg = <0x7000 0x400>;
116 clocks = <&rcc GPIOH>;
117 st,bank-name = "GPIOH";
119 gpio-ranges = <&pinctrl 0 112 16>;
123 gpioi: gpio@5000a000 {
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 reg = <0x8000 0x400>;
129 clocks = <&rcc GPIOI>;
130 st,bank-name = "GPIOI";
132 gpio-ranges = <&pinctrl 0 128 16>;
136 gpioj: gpio@5000b000 {
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 reg = <0x9000 0x400>;
142 clocks = <&rcc GPIOJ>;
143 st,bank-name = "GPIOJ";
145 gpio-ranges = <&pinctrl 0 144 16>;
149 gpiok: gpio@5000c000 {
152 interrupt-controller;
153 #interrupt-cells = <2>;
154 reg = <0xa000 0x400>;
155 clocks = <&rcc GPIOK>;
156 st,bank-name = "GPIOK";
158 gpio-ranges = <&pinctrl 0 160 8>;
164 pinmux = <STM32_PINMUX('A', 15, AF4)>;
171 cec_pins_sleep_a: cec-sleep-0 {
173 pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */
179 pinmux = <STM32_PINMUX('B', 6, AF5)>;
186 cec_pins_sleep_b: cec-sleep-1 {
188 pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */
192 dcmi_pins_a: dcmi-0 {
194 pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */
195 <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */
196 <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */
197 <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */
198 <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */
199 <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */
200 <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */
201 <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */
202 <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */
203 <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */
204 <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */
205 <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */
206 <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */
207 <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */
208 <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */
213 dcmi_sleep_pins_a: dcmi-sleep-0 {
215 pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */
216 <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */
217 <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */
218 <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */
219 <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */
220 <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */
221 <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */
222 <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */
223 <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */
224 <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */
225 <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */
226 <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */
227 <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */
228 <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */
229 <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */
233 ethernet0_rgmii_pins_a: rgmii-0 {
235 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
236 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
237 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
238 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
239 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
240 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
241 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
242 <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
243 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
249 pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
250 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
251 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
252 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
253 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
254 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
259 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
261 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
262 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
263 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
264 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
265 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
266 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
267 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
268 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
269 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
270 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
271 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
272 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
273 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
274 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
275 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
279 i2c1_pins_a: i2c1-0 {
281 pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */
282 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
289 i2c1_pins_sleep_a: i2c1-1 {
291 pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */
292 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
296 i2c1_pins_b: i2c1-2 {
298 pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */
299 <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */
306 i2c1_pins_sleep_b: i2c1-3 {
308 pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */
309 <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */
313 i2c2_pins_a: i2c2-0 {
315 pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
316 <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
323 i2c2_pins_sleep_a: i2c2-1 {
325 pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */
326 <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
330 i2c2_pins_b1: i2c2-2 {
332 pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
339 i2c2_pins_sleep_b1: i2c2-3 {
341 pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */
345 i2c5_pins_a: i2c5-0 {
347 pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */
348 <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */
355 i2c5_pins_sleep_a: i2c5-1 {
357 pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */
358 <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */
363 i2s2_pins_a: i2s2-0 {
365 pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */
366 <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */
367 <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */
374 i2s2_pins_sleep_a: i2s2-1 {
376 pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */
377 <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */
378 <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */
382 ltdc_pins_a: ltdc-a-0 {
384 pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */
385 <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */
386 <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */
387 <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */
388 <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */
389 <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */
390 <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */
391 <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */
392 <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */
393 <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */
394 <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */
395 <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */
396 <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */
397 <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */
398 <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */
399 <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */
400 <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */
401 <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */
402 <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */
403 <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */
404 <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */
405 <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */
406 <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */
407 <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */
408 <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */
409 <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */
410 <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */
411 <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */
418 ltdc_pins_sleep_a: ltdc-a-1 {
420 pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */
421 <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */
422 <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */
423 <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */
424 <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */
425 <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */
426 <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */
427 <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */
428 <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */
429 <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */
430 <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */
431 <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */
432 <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */
433 <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */
434 <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */
435 <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */
436 <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */
437 <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */
438 <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */
439 <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */
440 <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */
441 <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */
442 <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */
443 <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */
444 <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */
445 <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */
446 <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */
447 <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */
451 ltdc_pins_b: ltdc-b-0 {
453 pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */
454 <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */
455 <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */
456 <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */
457 <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */
458 <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */
459 <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */
460 <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */
461 <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */
462 <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */
463 <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */
464 <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */
465 <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */
466 <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */
467 <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */
468 <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */
469 <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */
470 <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */
471 <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */
472 <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */
473 <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */
474 <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */
475 <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */
476 <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */
477 <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */
478 <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */
479 <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */
480 <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */
487 ltdc_pins_sleep_b: ltdc-b-1 {
489 pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */
490 <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */
491 <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */
492 <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */
493 <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */
494 <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */
495 <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */
496 <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */
497 <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */
498 <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */
499 <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */
500 <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */
501 <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */
502 <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */
503 <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */
504 <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */
505 <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */
506 <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */
507 <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */
508 <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */
509 <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */
510 <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */
511 <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */
512 <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */
513 <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */
514 <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */
515 <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */
516 <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */
520 m_can1_pins_a: m-can1-0 {
522 pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
528 pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */
533 m_can1_sleep_pins_a: m_can1-sleep@0 {
535 pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */
536 <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */
540 pwm2_pins_a: pwm2-0 {
542 pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */
549 pwm8_pins_a: pwm8-0 {
551 pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */
558 pwm12_pins_a: pwm12-0 {
560 pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */
567 qspi_clk_pins_a: qspi-clk-0 {
569 pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
576 qspi_clk_sleep_pins_a: qspi-clk-sleep-0 {
578 pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */
582 qspi_bk1_pins_a: qspi-bk1-0 {
584 pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */
585 <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */
586 <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */
587 <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */
593 pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */
600 qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 {
602 pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */
603 <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */
604 <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */
605 <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */
606 <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */
610 qspi_bk2_pins_a: qspi-bk2-0 {
612 pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */
613 <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */
614 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
615 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
621 pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */
628 qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 {
630 pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */
631 <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */
632 <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */
633 <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */
634 <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */
638 sai2a_pins_a: sai2a-0 {
640 pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */
641 <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */
642 <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */
643 <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */
650 sai2a_sleep_pins_a: sai2a-1 {
652 pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */
653 <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */
654 <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */
655 <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */
659 sai2b_pins_a: sai2b-0 {
661 pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */
662 <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */
663 <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */
669 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
674 sai2b_sleep_pins_a: sai2b-1 {
676 pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */
677 <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */
678 <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */
679 <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */
683 sai2b_pins_b: sai2b-2 {
685 pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
690 sai2b_sleep_pins_b: sai2b-3 {
692 pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
696 sai4a_pins_a: sai4a-0 {
698 pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */
705 sai4a_sleep_pins_a: sai4a-1 {
707 pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */
711 sdmmc1_b4_pins_a: sdmmc1-b4-0 {
713 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
714 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
715 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
716 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
717 <STM32_PINMUX('C', 12, AF12)>, /* SDMMC1_CK */
718 <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
725 sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 {
727 pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
728 <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
729 <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
730 <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
731 <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
737 pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
744 sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 {
746 pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */
747 <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */
748 <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */
749 <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */
750 <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */
751 <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */
755 sdmmc1_dir_pins_a: sdmmc1-dir-0 {
757 pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */
758 <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */
759 <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */
765 pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */
770 sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 {
772 pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */
773 <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */
774 <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */
775 <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */
779 spdifrx_pins_a: spdifrx-0 {
781 pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */
786 spdifrx_sleep_pins_a: spdifrx-1 {
788 pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */
792 uart4_pins_a: uart4-0 {
794 pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
800 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
805 uart4_pins_b: uart4-1 {
807 pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */
813 pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
818 uart7_pins_a: uart7-0 {
820 pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART4_TX */
826 pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART4_RX */
827 <STM32_PINMUX('E', 10, AF7)>, /* UART4_CTS */
828 <STM32_PINMUX('E', 9, AF7)>; /* UART4_RTS */
834 pinctrl_z: pin-controller-z@54004000 {
835 #address-cells = <1>;
837 compatible = "st,stm32mp157-z-pinctrl";
838 ranges = <0 0x54004000 0x400>;
840 interrupt-parent = <&exti>;
841 st,syscfg = <&exti 0x60 0xff>;
843 gpioz: gpio@54004000 {
846 interrupt-controller;
847 #interrupt-cells = <2>;
849 clocks = <&rcc GPIOZ>;
850 st,bank-name = "GPIOZ";
851 st,bank-ioport = <11>;
853 gpio-ranges = <&pinctrl_z 0 400 8>;
857 i2c2_pins_b2: i2c2-0 {
859 pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */
866 i2c2_pins_sleep_b2: i2c2-1 {
868 pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */
872 i2c4_pins_a: i2c4-0 {
874 pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
875 <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
882 i2c4_pins_sleep_a: i2c4-1 {
884 pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */
885 <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */
889 spi1_pins_a: spi1-0 {
891 pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */
892 <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */
899 pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */