arch/arm/boot/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                 };
  24         };
  25
  26         arm-pmu {
  27                 compatible = "arm,cortex-a7-pmu";
  28                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  29                 interrupt-affinity = <&cpu0>;
  30                 interrupt-parent = <&intc>;
  31         };
  32
  33         psci {
  34                 compatible = "arm,psci-1.0";
  35                 method = "smc";
  36         };
  37
  38         intc: interrupt-controller@a0021000 {
  39                 compatible = "arm,cortex-a7-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xa0021000 0x1000>,
  43                       <0xa0022000 0x2000>;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&intc>;
  53         };
  54
  55         clocks {
  56                 clk_hse: clk-hse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61
  62                 clk_hsi: clk-hsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <64000000>;
  66                 };
  67
  68                 clk_lse: clk-lse {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                 };
  73
  74                 clk_lsi: clk-lsi {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <32000>;
  78                 };
  79
  80                 clk_csi: clk-csi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <4000000>;
  84                 };
  85         };
  86
  87         thermal-zones {
  88                 cpu_thermal: cpu-thermal {
  89                         polling-delay-passive = <0>;
  90                         polling-delay = <0>;
  91                         thermal-sensors = <&dts>;
  92
  93                         trips {
  94                                 cpu_alert1: cpu-alert1 {
  95                                         temperature = <85000>;
  96                                         hysteresis = <0>;
  97                                         type = "passive";
  98                                 };
  99
 100                                 cpu-crit {
 101                                         temperature = <120000>;
 102                                         hysteresis = <0>;
 103                                         type = "critical";
 104                                 };
 105                         };
 106
 107                         cooling-maps {
 108                         };
 109                 };
 110         };
 111
 112         booster: regulator-booster {
 113                 compatible = "st,stm32mp1-booster";
 114                 st,syscfg = <&syscfg>;
 115                 status = "disabled";
 116         };
 117
 118         soc {
 119                 compatible = "simple-bus";
 120                 #address-cells = <1>;
 121                 #size-cells = <1>;
 122                 interrupt-parent = <&intc>;
 123                 ranges;
 124
 125                 timers2: timer@40000000 {
 126                         #address-cells = <1>;
 127                         #size-cells = <0>;
 128                         compatible = "st,stm32-timers";
 129                         reg = <0x40000000 0x400>;
 130                         clocks = <&rcc TIM2_K>;
 131                         clock-names = "int";
 132                         dmas = <&dmamux1 18 0x400 0x1>,
 133                                <&dmamux1 19 0x400 0x1>,
 134                                <&dmamux1 20 0x400 0x1>,
 135                                <&dmamux1 21 0x400 0x1>,
 136                                <&dmamux1 22 0x400 0x1>;
 137                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 138                         status = "disabled";
 139
 140                         pwm {
 141                                 compatible = "st,stm32-pwm";
 142                                 #pwm-cells = <3>;
 143                                 status = "disabled";
 144                         };
 145
 146                         timer@1 {
 147                                 compatible = "st,stm32h7-timer-trigger";
 148                                 reg = <1>;
 149                                 status = "disabled";
 150                         };
 151
 152                         counter {
 153                                 compatible = "st,stm32-timer-counter";
 154                                 status = "disabled";
 155                         };
 156                 };
 157
 158                 timers3: timer@40001000 {
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161                         compatible = "st,stm32-timers";
 162                         reg = <0x40001000 0x400>;
 163                         clocks = <&rcc TIM3_K>;
 164                         clock-names = "int";
 165                         dmas = <&dmamux1 23 0x400 0x1>,
 166                                <&dmamux1 24 0x400 0x1>,
 167                                <&dmamux1 25 0x400 0x1>,
 168                                <&dmamux1 26 0x400 0x1>,
 169                                <&dmamux1 27 0x400 0x1>,
 170                                <&dmamux1 28 0x400 0x1>;
 171                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 172                         status = "disabled";
 173
 174                         pwm {
 175                                 compatible = "st,stm32-pwm";
 176                                 #pwm-cells = <3>;
 177                                 status = "disabled";
 178                         };
 179
 180                         timer@2 {
 181                                 compatible = "st,stm32h7-timer-trigger";
 182                                 reg = <2>;
 183                                 status = "disabled";
 184                         };
 185
 186                         counter {
 187                                 compatible = "st,stm32-timer-counter";
 188                                 status = "disabled";
 189                         };
 190                 };
 191
 192                 timers4: timer@40002000 {
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195                         compatible = "st,stm32-timers";
 196                         reg = <0x40002000 0x400>;
 197                         clocks = <&rcc TIM4_K>;
 198                         clock-names = "int";
 199                         dmas = <&dmamux1 29 0x400 0x1>,
 200                                <&dmamux1 30 0x400 0x1>,
 201                                <&dmamux1 31 0x400 0x1>,
 202                                <&dmamux1 32 0x400 0x1>;
 203                         dma-names = "ch1", "ch2", "ch3", "ch4";
 204                         status = "disabled";
 205
 206                         pwm {
 207                                 compatible = "st,stm32-pwm";
 208                                 #pwm-cells = <3>;
 209                                 status = "disabled";
 210                         };
 211
 212                         timer@3 {
 213                                 compatible = "st,stm32h7-timer-trigger";
 214                                 reg = <3>;
 215                                 status = "disabled";
 216                         };
 217
 218                         counter {
 219                                 compatible = "st,stm32-timer-counter";
 220                                 status = "disabled";
 221                         };
 222                 };
 223
 224                 timers5: timer@40003000 {
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         compatible = "st,stm32-timers";
 228                         reg = <0x40003000 0x400>;
 229                         clocks = <&rcc TIM5_K>;
 230                         clock-names = "int";
 231                         dmas = <&dmamux1 55 0x400 0x1>,
 232                                <&dmamux1 56 0x400 0x1>,
 233                                <&dmamux1 57 0x400 0x1>,
 234                                <&dmamux1 58 0x400 0x1>,
 235                                <&dmamux1 59 0x400 0x1>,
 236                                <&dmamux1 60 0x400 0x1>;
 237                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 238                         status = "disabled";
 239
 240                         pwm {
 241                                 compatible = "st,stm32-pwm";
 242                                 #pwm-cells = <3>;
 243                                 status = "disabled";
 244                         };
 245
 246                         timer@4 {
 247                                 compatible = "st,stm32h7-timer-trigger";
 248                                 reg = <4>;
 249                                 status = "disabled";
 250                         };
 251
 252                         counter {
 253                                 compatible = "st,stm32-timer-counter";
 254                                 status = "disabled";
 255                         };
 256                 };
 257
 258                 timers6: timer@40004000 {
 259                         #address-cells = <1>;
 260                         #size-cells = <0>;
 261                         compatible = "st,stm32-timers";
 262                         reg = <0x40004000 0x400>;
 263                         clocks = <&rcc TIM6_K>;
 264                         clock-names = "int";
 265                         dmas = <&dmamux1 69 0x400 0x1>;
 266                         dma-names = "up";
 267                         status = "disabled";
 268
 269                         timer@5 {
 270                                 compatible = "st,stm32h7-timer-trigger";
 271                                 reg = <5>;
 272                                 status = "disabled";
 273                         };
 274                 };
 275
 276                 timers7: timer@40005000 {
 277                         #address-cells = <1>;
 278                         #size-cells = <0>;
 279                         compatible = "st,stm32-timers";
 280                         reg = <0x40005000 0x400>;
 281                         clocks = <&rcc TIM7_K>;
 282                         clock-names = "int";
 283                         dmas = <&dmamux1 70 0x400 0x1>;
 284                         dma-names = "up";
 285                         status = "disabled";
 286
 287                         timer@6 {
 288                                 compatible = "st,stm32h7-timer-trigger";
 289                                 reg = <6>;
 290                                 status = "disabled";
 291                         };
 292                 };
 293
 294                 timers12: timer@40006000 {
 295                         #address-cells = <1>;
 296                         #size-cells = <0>;
 297                         compatible = "st,stm32-timers";
 298                         reg = <0x40006000 0x400>;
 299                         clocks = <&rcc TIM12_K>;
 300                         clock-names = "int";
 301                         status = "disabled";
 302
 303                         pwm {
 304                                 compatible = "st,stm32-pwm";
 305                                 #pwm-cells = <3>;
 306                                 status = "disabled";
 307                         };
 308
 309                         timer@11 {
 310                                 compatible = "st,stm32h7-timer-trigger";
 311                                 reg = <11>;
 312                                 status = "disabled";
 313                         };
 314                 };
 315
 316                 timers13: timer@40007000 {
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         compatible = "st,stm32-timers";
 320                         reg = <0x40007000 0x400>;
 321                         clocks = <&rcc TIM13_K>;
 322                         clock-names = "int";
 323                         status = "disabled";
 324
 325                         pwm {
 326                                 compatible = "st,stm32-pwm";
 327                                 #pwm-cells = <3>;
 328                                 status = "disabled";
 329                         };
 330
 331                         timer@12 {
 332                                 compatible = "st,stm32h7-timer-trigger";
 333                                 reg = <12>;
 334                                 status = "disabled";
 335                         };
 336                 };
 337
 338                 timers14: timer@40008000 {
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         compatible = "st,stm32-timers";
 342                         reg = <0x40008000 0x400>;
 343                         clocks = <&rcc TIM14_K>;
 344                         clock-names = "int";
 345                         status = "disabled";
 346
 347                         pwm {
 348                                 compatible = "st,stm32-pwm";
 349                                 #pwm-cells = <3>;
 350                                 status = "disabled";
 351                         };
 352
 353                         timer@13 {
 354                                 compatible = "st,stm32h7-timer-trigger";
 355                                 reg = <13>;
 356                                 status = "disabled";
 357                         };
 358                 };
 359
 360                 lptimer1: timer@40009000 {
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         compatible = "st,stm32-lptimer";
 364                         reg = <0x40009000 0x400>;
 365                         interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&rcc LPTIM1_K>;
 367                         clock-names = "mux";
 368                         wakeup-source;
 369                         status = "disabled";
 370
 371                         pwm {
 372                                 compatible = "st,stm32-pwm-lp";
 373                                 #pwm-cells = <3>;
 374                                 status = "disabled";
 375                         };
 376
 377                         trigger@0 {
 378                                 compatible = "st,stm32-lptimer-trigger";
 379                                 reg = <0>;
 380                                 status = "disabled";
 381                         };
 382
 383                         counter {
 384                                 compatible = "st,stm32-lptimer-counter";
 385                                 status = "disabled";
 386                         };
 387                 };
 388
 389                 spi2: spi@4000b000 {
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                         compatible = "st,stm32h7-spi";
 393                         reg = <0x4000b000 0x400>;
 394                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 395                         clocks = <&rcc SPI2_K>;
 396                         resets = <&rcc SPI2_R>;
 397                         dmas = <&dmamux1 39 0x400 0x05>,
 398                                <&dmamux1 40 0x400 0x05>;
 399                         dma-names = "rx", "tx";
 400                         status = "disabled";
 401                 };
 402
 403                 i2s2: audio-controller@4000b000 {
 404                         compatible = "st,stm32h7-i2s";
 405                         #sound-dai-cells = <0>;
 406                         reg = <0x4000b000 0x400>;
 407                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 408                         dmas = <&dmamux1 39 0x400 0x01>,
 409                                <&dmamux1 40 0x400 0x01>;
 410                         dma-names = "rx", "tx";
 411                         status = "disabled";
 412                 };
 413
 414                 spi3: spi@4000c000 {
 415                         #address-cells = <1>;
 416                         #size-cells = <0>;
 417                         compatible = "st,stm32h7-spi";
 418                         reg = <0x4000c000 0x400>;
 419                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 420                         clocks = <&rcc SPI3_K>;
 421                         resets = <&rcc SPI3_R>;
 422                         dmas = <&dmamux1 61 0x400 0x05>,
 423                                <&dmamux1 62 0x400 0x05>;
 424                         dma-names = "rx", "tx";
 425                         status = "disabled";
 426                 };
 427
 428                 i2s3: audio-controller@4000c000 {
 429                         compatible = "st,stm32h7-i2s";
 430                         #sound-dai-cells = <0>;
 431                         reg = <0x4000c000 0x400>;
 432                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 433                         dmas = <&dmamux1 61 0x400 0x01>,
 434                                <&dmamux1 62 0x400 0x01>;
 435                         dma-names = "rx", "tx";
 436                         status = "disabled";
 437                 };
 438
 439                 spdifrx: audio-controller@4000d000 {
 440                         compatible = "st,stm32h7-spdifrx";
 441                         #sound-dai-cells = <0>;
 442                         reg = <0x4000d000 0x400>;
 443                         clocks = <&rcc SPDIF_K>;
 444                         clock-names = "kclk";
 445                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 446                         dmas = <&dmamux1 93 0x400 0x01>,
 447                                <&dmamux1 94 0x400 0x01>;
 448                         dma-names = "rx", "rx-ctrl";
 449                         status = "disabled";
 450                 };
 451
 452                 usart2: serial@4000e000 {
 453                         compatible = "st,stm32h7-uart";
 454                         reg = <0x4000e000 0x400>;
 455                         interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&rcc USART2_K>;
 457                         wakeup-source;
 458                         dmas = <&dmamux1 43 0x400 0x15>,
 459                                <&dmamux1 44 0x400 0x11>;
 460                         dma-names = "rx", "tx";
 461                         status = "disabled";
 462                 };
 463
 464                 usart3: serial@4000f000 {
 465                         compatible = "st,stm32h7-uart";
 466                         reg = <0x4000f000 0x400>;
 467                         interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
 468                         clocks = <&rcc USART3_K>;
 469                         wakeup-source;
 470                         dmas = <&dmamux1 45 0x400 0x15>,
 471                                <&dmamux1 46 0x400 0x11>;
 472                         dma-names = "rx", "tx";
 473                         status = "disabled";
 474                 };
 475
 476                 uart4: serial@40010000 {
 477                         compatible = "st,stm32h7-uart";
 478                         reg = <0x40010000 0x400>;
 479                         interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
 480                         clocks = <&rcc UART4_K>;
 481                         wakeup-source;
 482                         dmas = <&dmamux1 63 0x400 0x15>,
 483                                <&dmamux1 64 0x400 0x11>;
 484                         dma-names = "rx", "tx";
 485                         status = "disabled";
 486                 };
 487
 488                 uart5: serial@40011000 {
 489                         compatible = "st,stm32h7-uart";
 490                         reg = <0x40011000 0x400>;
 491                         interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
 492                         clocks = <&rcc UART5_K>;
 493                         wakeup-source;
 494                         dmas = <&dmamux1 65 0x400 0x15>,
 495                                <&dmamux1 66 0x400 0x11>;
 496                         dma-names = "rx", "tx";
 497                         status = "disabled";
 498                 };
 499
 500                 i2c1: i2c@40012000 {
 501                         compatible = "st,stm32mp15-i2c";
 502                         reg = <0x40012000 0x400>;
 503                         interrupt-names = "event", "error";
 504                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 505                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 506                         clocks = <&rcc I2C1_K>;
 507                         resets = <&rcc I2C1_R>;
 508                         #address-cells = <1>;
 509                         #size-cells = <0>;
 510                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 511                         wakeup-source;
 512                         i2c-analog-filter;
 513                         status = "disabled";
 514                 };
 515
 516                 i2c2: i2c@40013000 {
 517                         compatible = "st,stm32mp15-i2c";
 518                         reg = <0x40013000 0x400>;
 519                         interrupt-names = "event", "error";
 520                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 521                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 522                         clocks = <&rcc I2C2_K>;
 523                         resets = <&rcc I2C2_R>;
 524                         #address-cells = <1>;
 525                         #size-cells = <0>;
 526                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 527                         wakeup-source;
 528                         i2c-analog-filter;
 529                         status = "disabled";
 530                 };
 531
 532                 i2c3: i2c@40014000 {
 533                         compatible = "st,stm32mp15-i2c";
 534                         reg = <0x40014000 0x400>;
 535                         interrupt-names = "event", "error";
 536                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 537                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 538                         clocks = <&rcc I2C3_K>;
 539                         resets = <&rcc I2C3_R>;
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 543                         wakeup-source;
 544                         i2c-analog-filter;
 545                         status = "disabled";
 546                 };
 547
 548                 i2c5: i2c@40015000 {
 549                         compatible = "st,stm32mp15-i2c";
 550                         reg = <0x40015000 0x400>;
 551                         interrupt-names = "event", "error";
 552                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 553                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&rcc I2C5_K>;
 555                         resets = <&rcc I2C5_R>;
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 559                         wakeup-source;
 560                         i2c-analog-filter;
 561                         status = "disabled";
 562                 };
 563
 564                 cec: cec@40016000 {
 565                         compatible = "st,stm32-cec";
 566                         reg = <0x40016000 0x400>;
 567                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 568                         clocks = <&rcc CEC_K>, <&rcc CEC>;
 569                         clock-names = "cec", "hdmi-cec";
 570                         status = "disabled";
 571                 };
 572
 573                 dac: dac@40017000 {
 574                         compatible = "st,stm32h7-dac-core";
 575                         reg = <0x40017000 0x400>;
 576                         clocks = <&rcc DAC12>;
 577                         clock-names = "pclk";
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         status = "disabled";
 581
 582                         dac1: dac@1 {
 583                                 compatible = "st,stm32-dac";
 584                                 #io-channel-cells = <1>;
 585                                 reg = <1>;
 586                                 status = "disabled";
 587                         };
 588
 589                         dac2: dac@2 {
 590                                 compatible = "st,stm32-dac";
 591                                 #io-channel-cells = <1>;
 592                                 reg = <2>;
 593                                 status = "disabled";
 594                         };
 595                 };
 596
 597                 uart7: serial@40018000 {
 598                         compatible = "st,stm32h7-uart";
 599                         reg = <0x40018000 0x400>;
 600                         interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
 601                         clocks = <&rcc UART7_K>;
 602                         wakeup-source;
 603                         dmas = <&dmamux1 79 0x400 0x15>,
 604                                <&dmamux1 80 0x400 0x11>;
 605                         dma-names = "rx", "tx";
 606                         status = "disabled";
 607                 };
 608
 609                 uart8: serial@40019000 {
 610                         compatible = "st,stm32h7-uart";
 611                         reg = <0x40019000 0x400>;
 612                         interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&rcc UART8_K>;
 614                         wakeup-source;
 615                         dmas = <&dmamux1 81 0x400 0x15>,
 616                                <&dmamux1 82 0x400 0x11>;
 617                         dma-names = "rx", "tx";
 618                         status = "disabled";
 619                 };
 620
 621                 timers1: timer@44000000 {
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         compatible = "st,stm32-timers";
 625                         reg = <0x44000000 0x400>;
 626                         clocks = <&rcc TIM1_K>;
 627                         clock-names = "int";
 628                         dmas = <&dmamux1 11 0x400 0x1>,
 629                                <&dmamux1 12 0x400 0x1>,
 630                                <&dmamux1 13 0x400 0x1>,
 631                                <&dmamux1 14 0x400 0x1>,
 632                                <&dmamux1 15 0x400 0x1>,
 633                                <&dmamux1 16 0x400 0x1>,
 634                                <&dmamux1 17 0x400 0x1>;
 635                         dma-names = "ch1", "ch2", "ch3", "ch4",
 636                                     "up", "trig", "com";
 637                         status = "disabled";
 638
 639                         pwm {
 640                                 compatible = "st,stm32-pwm";
 641                                 #pwm-cells = <3>;
 642                                 status = "disabled";
 643                         };
 644
 645                         timer@0 {
 646                                 compatible = "st,stm32h7-timer-trigger";
 647                                 reg = <0>;
 648                                 status = "disabled";
 649                         };
 650
 651                         counter {
 652                                 compatible = "st,stm32-timer-counter";
 653                                 status = "disabled";
 654                         };
 655                 };
 656
 657                 timers8: timer@44001000 {
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                         compatible = "st,stm32-timers";
 661                         reg = <0x44001000 0x400>;
 662                         clocks = <&rcc TIM8_K>;
 663                         clock-names = "int";
 664                         dmas = <&dmamux1 47 0x400 0x1>,
 665                                <&dmamux1 48 0x400 0x1>,
 666                                <&dmamux1 49 0x400 0x1>,
 667                                <&dmamux1 50 0x400 0x1>,
 668                                <&dmamux1 51 0x400 0x1>,
 669                                <&dmamux1 52 0x400 0x1>,
 670                                <&dmamux1 53 0x400 0x1>;
 671                         dma-names = "ch1", "ch2", "ch3", "ch4",
 672                                     "up", "trig", "com";
 673                         status = "disabled";
 674
 675                         pwm {
 676                                 compatible = "st,stm32-pwm";
 677                                 #pwm-cells = <3>;
 678                                 status = "disabled";
 679                         };
 680
 681                         timer@7 {
 682                                 compatible = "st,stm32h7-timer-trigger";
 683                                 reg = <7>;
 684                                 status = "disabled";
 685                         };
 686
 687                         counter {
 688                                 compatible = "st,stm32-timer-counter";
 689                                 status = "disabled";
 690                         };
 691                 };
 692
 693                 usart6: serial@44003000 {
 694                         compatible = "st,stm32h7-uart";
 695                         reg = <0x44003000 0x400>;
 696                         interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
 697                         clocks = <&rcc USART6_K>;
 698                         wakeup-source;
 699                         dmas = <&dmamux1 71 0x400 0x15>,
 700                                <&dmamux1 72 0x400 0x11>;
 701                         dma-names = "rx", "tx";
 702                         status = "disabled";
 703                 };
 704
 705                 spi1: spi@44004000 {
 706                         #address-cells = <1>;
 707                         #size-cells = <0>;
 708                         compatible = "st,stm32h7-spi";
 709                         reg = <0x44004000 0x400>;
 710                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 711                         clocks = <&rcc SPI1_K>;
 712                         resets = <&rcc SPI1_R>;
 713                         dmas = <&dmamux1 37 0x400 0x05>,
 714                                <&dmamux1 38 0x400 0x05>;
 715                         dma-names = "rx", "tx";
 716                         status = "disabled";
 717                 };
 718
 719                 i2s1: audio-controller@44004000 {
 720                         compatible = "st,stm32h7-i2s";
 721                         #sound-dai-cells = <0>;
 722                         reg = <0x44004000 0x400>;
 723                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 724                         dmas = <&dmamux1 37 0x400 0x01>,
 725                                <&dmamux1 38 0x400 0x01>;
 726                         dma-names = "rx", "tx";
 727                         status = "disabled";
 728                 };
 729
 730                 spi4: spi@44005000 {
 731                         #address-cells = <1>;
 732                         #size-cells = <0>;
 733                         compatible = "st,stm32h7-spi";
 734                         reg = <0x44005000 0x400>;
 735                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 736                         clocks = <&rcc SPI4_K>;
 737                         resets = <&rcc SPI4_R>;
 738                         dmas = <&dmamux1 83 0x400 0x05>,
 739                                <&dmamux1 84 0x400 0x05>;
 740                         dma-names = "rx", "tx";
 741                         status = "disabled";
 742                 };
 743
 744                 timers15: timer@44006000 {
 745                         #address-cells = <1>;
 746                         #size-cells = <0>;
 747                         compatible = "st,stm32-timers";
 748                         reg = <0x44006000 0x400>;
 749                         clocks = <&rcc TIM15_K>;
 750                         clock-names = "int";
 751                         dmas = <&dmamux1 105 0x400 0x1>,
 752                                <&dmamux1 106 0x400 0x1>,
 753                                <&dmamux1 107 0x400 0x1>,
 754                                <&dmamux1 108 0x400 0x1>;
 755                         dma-names = "ch1", "up", "trig", "com";
 756                         status = "disabled";
 757
 758                         pwm {
 759                                 compatible = "st,stm32-pwm";
 760                                 #pwm-cells = <3>;
 761                                 status = "disabled";
 762                         };
 763
 764                         timer@14 {
 765                                 compatible = "st,stm32h7-timer-trigger";
 766                                 reg = <14>;
 767                                 status = "disabled";
 768                         };
 769                 };
 770
 771                 timers16: timer@44007000 {
 772                         #address-cells = <1>;
 773                         #size-cells = <0>;
 774                         compatible = "st,stm32-timers";
 775                         reg = <0x44007000 0x400>;
 776                         clocks = <&rcc TIM16_K>;
 777                         clock-names = "int";
 778                         dmas = <&dmamux1 109 0x400 0x1>,
 779                                <&dmamux1 110 0x400 0x1>;
 780                         dma-names = "ch1", "up";
 781                         status = "disabled";
 782
 783                         pwm {
 784                                 compatible = "st,stm32-pwm";
 785                                 #pwm-cells = <3>;
 786                                 status = "disabled";
 787                         };
 788                         timer@15 {
 789                                 compatible = "st,stm32h7-timer-trigger";
 790                                 reg = <15>;
 791                                 status = "disabled";
 792                         };
 793                 };
 794
 795                 timers17: timer@44008000 {
 796                         #address-cells = <1>;
 797                         #size-cells = <0>;
 798                         compatible = "st,stm32-timers";
 799                         reg = <0x44008000 0x400>;
 800                         clocks = <&rcc TIM17_K>;
 801                         clock-names = "int";
 802                         dmas = <&dmamux1 111 0x400 0x1>,
 803                                <&dmamux1 112 0x400 0x1>;
 804                         dma-names = "ch1", "up";
 805                         status = "disabled";
 806
 807                         pwm {
 808                                 compatible = "st,stm32-pwm";
 809                                 #pwm-cells = <3>;
 810                                 status = "disabled";
 811                         };
 812
 813                         timer@16 {
 814                                 compatible = "st,stm32h7-timer-trigger";
 815                                 reg = <16>;
 816                                 status = "disabled";
 817                         };
 818                 };
 819
 820                 spi5: spi@44009000 {
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                         compatible = "st,stm32h7-spi";
 824                         reg = <0x44009000 0x400>;
 825                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 826                         clocks = <&rcc SPI5_K>;
 827                         resets = <&rcc SPI5_R>;
 828                         dmas = <&dmamux1 85 0x400 0x05>,
 829                                <&dmamux1 86 0x400 0x05>;
 830                         dma-names = "rx", "tx";
 831                         status = "disabled";
 832                 };
 833
 834                 sai1: sai@4400a000 {
 835                         compatible = "st,stm32h7-sai";
 836                         #address-cells = <1>;
 837                         #size-cells = <1>;
 838                         ranges = <0 0x4400a000 0x400>;
 839                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 840                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 841                         resets = <&rcc SAI1_R>;
 842                         status = "disabled";
 843
 844                         sai1a: audio-controller@4400a004 {
 845                                 #sound-dai-cells = <0>;
 846
 847                                 compatible = "st,stm32-sai-sub-a";
 848                                 reg = <0x4 0x20>;
 849                                 clocks = <&rcc SAI1_K>;
 850                                 clock-names = "sai_ck";
 851                                 dmas = <&dmamux1 87 0x400 0x01>;
 852                                 status = "disabled";
 853                         };
 854
 855                         sai1b: audio-controller@4400a024 {
 856                                 #sound-dai-cells = <0>;
 857                                 compatible = "st,stm32-sai-sub-b";
 858                                 reg = <0x24 0x20>;
 859                                 clocks = <&rcc SAI1_K>;
 860                                 clock-names = "sai_ck";
 861                                 dmas = <&dmamux1 88 0x400 0x01>;
 862                                 status = "disabled";
 863                         };
 864                 };
 865
 866                 sai2: sai@4400b000 {
 867                         compatible = "st,stm32h7-sai";
 868                         #address-cells = <1>;
 869                         #size-cells = <1>;
 870                         ranges = <0 0x4400b000 0x400>;
 871                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 872                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 873                         resets = <&rcc SAI2_R>;
 874                         status = "disabled";
 875
 876                         sai2a: audio-controller@4400b004 {
 877                                 #sound-dai-cells = <0>;
 878                                 compatible = "st,stm32-sai-sub-a";
 879                                 reg = <0x4 0x20>;
 880                                 clocks = <&rcc SAI2_K>;
 881                                 clock-names = "sai_ck";
 882                                 dmas = <&dmamux1 89 0x400 0x01>;
 883                                 status = "disabled";
 884                         };
 885
 886                         sai2b: audio-controller@4400b024 {
 887                                 #sound-dai-cells = <0>;
 888                                 compatible = "st,stm32-sai-sub-b";
 889                                 reg = <0x24 0x20>;
 890                                 clocks = <&rcc SAI2_K>;
 891                                 clock-names = "sai_ck";
 892                                 dmas = <&dmamux1 90 0x400 0x01>;
 893                                 status = "disabled";
 894                         };
 895                 };
 896
 897                 sai3: sai@4400c000 {
 898                         compatible = "st,stm32h7-sai";
 899                         #address-cells = <1>;
 900                         #size-cells = <1>;
 901                         ranges = <0 0x4400c000 0x400>;
 902                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 903                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 904                         resets = <&rcc SAI3_R>;
 905                         status = "disabled";
 906
 907                         sai3a: audio-controller@4400c004 {
 908                                 #sound-dai-cells = <0>;
 909                                 compatible = "st,stm32-sai-sub-a";
 910                                 reg = <0x04 0x20>;
 911                                 clocks = <&rcc SAI3_K>;
 912                                 clock-names = "sai_ck";
 913                                 dmas = <&dmamux1 113 0x400 0x01>;
 914                                 status = "disabled";
 915                         };
 916
 917                         sai3b: audio-controller@4400c024 {
 918                                 #sound-dai-cells = <0>;
 919                                 compatible = "st,stm32-sai-sub-b";
 920                                 reg = <0x24 0x20>;
 921                                 clocks = <&rcc SAI3_K>;
 922                                 clock-names = "sai_ck";
 923                                 dmas = <&dmamux1 114 0x400 0x01>;
 924                                 status = "disabled";
 925                         };
 926                 };
 927
 928                 dfsdm: dfsdm@4400d000 {
 929                         compatible = "st,stm32mp1-dfsdm";
 930                         reg = <0x4400d000 0x800>;
 931                         clocks = <&rcc DFSDM_K>;
 932                         clock-names = "dfsdm";
 933                         #address-cells = <1>;
 934                         #size-cells = <0>;
 935                         status = "disabled";
 936
 937                         dfsdm0: filter@0 {
 938                                 compatible = "st,stm32-dfsdm-adc";
 939                                 #io-channel-cells = <1>;
 940                                 reg = <0>;
 941                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 942                                 dmas = <&dmamux1 101 0x400 0x01>;
 943                                 dma-names = "rx";
 944                                 status = "disabled";
 945                         };
 946
 947                         dfsdm1: filter@1 {
 948                                 compatible = "st,stm32-dfsdm-adc";
 949                                 #io-channel-cells = <1>;
 950                                 reg = <1>;
 951                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 952                                 dmas = <&dmamux1 102 0x400 0x01>;
 953                                 dma-names = "rx";
 954                                 status = "disabled";
 955                         };
 956
 957                         dfsdm2: filter@2 {
 958                                 compatible = "st,stm32-dfsdm-adc";
 959                                 #io-channel-cells = <1>;
 960                                 reg = <2>;
 961                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 962                                 dmas = <&dmamux1 103 0x400 0x01>;
 963                                 dma-names = "rx";
 964                                 status = "disabled";
 965                         };
 966
 967                         dfsdm3: filter@3 {
 968                                 compatible = "st,stm32-dfsdm-adc";
 969                                 #io-channel-cells = <1>;
 970                                 reg = <3>;
 971                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 972                                 dmas = <&dmamux1 104 0x400 0x01>;
 973                                 dma-names = "rx";
 974                                 status = "disabled";
 975                         };
 976
 977                         dfsdm4: filter@4 {
 978                                 compatible = "st,stm32-dfsdm-adc";
 979                                 #io-channel-cells = <1>;
 980                                 reg = <4>;
 981                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 982                                 dmas = <&dmamux1 91 0x400 0x01>;
 983                                 dma-names = "rx";
 984                                 status = "disabled";
 985                         };
 986
 987                         dfsdm5: filter@5 {
 988                                 compatible = "st,stm32-dfsdm-adc";
 989                                 #io-channel-cells = <1>;
 990                                 reg = <5>;
 991                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 992                                 dmas = <&dmamux1 92 0x400 0x01>;
 993                                 dma-names = "rx";
 994                                 status = "disabled";
 995                         };
 996                 };
 997
 998                 dma1: dma-controller@48000000 {
 999                         compatible = "st,stm32-dma";
1000                         reg = <0x48000000 0x400>;
1001                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1002                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1003                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1004                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1005                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1006                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1007                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1008                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1009                         clocks = <&rcc DMA1>;
1010                         resets = <&rcc DMA1_R>;
1011                         #dma-cells = <4>;
1012                         st,mem2mem;
1013                         dma-requests = <8>;
1014                 };
1015
1016                 dma2: dma-controller@48001000 {
1017                         compatible = "st,stm32-dma";
1018                         reg = <0x48001000 0x400>;
1019                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1020                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1021                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1022                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1023                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1024                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1025                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1026                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1027                         clocks = <&rcc DMA2>;
1028                         resets = <&rcc DMA2_R>;
1029                         #dma-cells = <4>;
1030                         st,mem2mem;
1031                         dma-requests = <8>;
1032                 };
1033
1034                 dmamux1: dma-router@48002000 {
1035                         compatible = "st,stm32h7-dmamux";
1036                         reg = <0x48002000 0x40>;
1037                         #dma-cells = <3>;
1038                         dma-requests = <128>;
1039                         dma-masters = <&dma1 &dma2>;
1040                         dma-channels = <16>;
1041                         clocks = <&rcc DMAMUX>;
1042                         resets = <&rcc DMAMUX_R>;
1043                 };
1044
1045                 adc: adc@48003000 {
1046                         compatible = "st,stm32mp1-adc-core";
1047                         reg = <0x48003000 0x400>;
1048                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1049                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1050                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1051                         clock-names = "bus", "adc";
1052                         interrupt-controller;
1053                         st,syscfg = <&syscfg>;
1054                         #interrupt-cells = <1>;
1055                         #address-cells = <1>;
1056                         #size-cells = <0>;
1057                         status = "disabled";
1058
1059                         adc1: adc@0 {
1060                                 compatible = "st,stm32mp1-adc";
1061                                 #io-channel-cells = <1>;
1062                                 reg = <0x0>;
1063                                 interrupt-parent = <&adc>;
1064                                 interrupts = <0>;
1065                                 dmas = <&dmamux1 9 0x400 0x01>;
1066                                 dma-names = "rx";
1067                                 status = "disabled";
1068                         };
1069
1070                         adc2: adc@100 {
1071                                 compatible = "st,stm32mp1-adc";
1072                                 #io-channel-cells = <1>;
1073                                 reg = <0x100>;
1074                                 interrupt-parent = <&adc>;
1075                                 interrupts = <1>;
1076                                 dmas = <&dmamux1 10 0x400 0x01>;
1077                                 dma-names = "rx";
1078                                 status = "disabled";
1079                         };
1080                 };
1081
1082                 sdmmc3: mmc@48004000 {
1083                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1084                         arm,primecell-periphid = <0x00253180>;
1085                         reg = <0x48004000 0x400>;
1086                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1087                         interrupt-names = "cmd_irq";
1088                         clocks = <&rcc SDMMC3_K>;
1089                         clock-names = "apb_pclk";
1090                         resets = <&rcc SDMMC3_R>;
1091                         cap-sd-highspeed;
1092                         cap-mmc-highspeed;
1093                         max-frequency = <120000000>;
1094                         status = "disabled";
1095                 };
1096
1097                 usbotg_hs: usb-otg@49000000 {
1098                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1099                         reg = <0x49000000 0x10000>;
1100                         clocks = <&rcc USBO_K>;
1101                         clock-names = "otg";
1102                         resets = <&rcc USBO_R>;
1103                         reset-names = "dwc2";
1104                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1105                         g-rx-fifo-size = <512>;
1106                         g-np-tx-fifo-size = <32>;
1107                         g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1108                         dr_mode = "otg";
1109                         otg-rev = <0x200>;
1110                         usb33d-supply = <&usb33>;
1111                         status = "disabled";
1112                 };
1113
1114                 ipcc: mailbox@4c001000 {
1115                         compatible = "st,stm32mp1-ipcc";
1116                         #mbox-cells = <1>;
1117                         reg = <0x4c001000 0x400>;
1118                         st,proc-id = <0>;
1119                         interrupts-extended =
1120                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1121                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1122                                 <&exti 61 1>;
1123                         interrupt-names = "rx", "tx", "wakeup";
1124                         clocks = <&rcc IPCC>;
1125                         wakeup-source;
1126                         status = "disabled";
1127                 };
1128
1129                 dcmi: dcmi@4c006000 {
1130                         compatible = "st,stm32-dcmi";
1131                         reg = <0x4c006000 0x400>;
1132                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1133                         resets = <&rcc CAMITF_R>;
1134                         clocks = <&rcc DCMI>;
1135                         clock-names = "mclk";
1136                         dmas = <&dmamux1 75 0x400 0x01>;
1137                         dma-names = "tx";
1138                         status = "disabled";
1139                 };
1140
1141                 rcc: rcc@50000000 {
1142                         compatible = "st,stm32mp1-rcc", "syscon";
1143                         reg = <0x50000000 0x1000>;
1144                         #clock-cells = <1>;
1145                         #reset-cells = <1>;
1146                 };
1147
1148                 pwr_regulators: pwr@50001000 {
1149                         compatible = "st,stm32mp1,pwr-reg";
1150                         reg = <0x50001000 0x10>;
1151
1152                         reg11: reg11 {
1153                                 regulator-name = "reg11";
1154                                 regulator-min-microvolt = <1100000>;
1155                                 regulator-max-microvolt = <1100000>;
1156                         };
1157
1158                         reg18: reg18 {
1159                                 regulator-name = "reg18";
1160                                 regulator-min-microvolt = <1800000>;
1161                                 regulator-max-microvolt = <1800000>;
1162                         };
1163
1164                         usb33: usb33 {
1165                                 regulator-name = "usb33";
1166                                 regulator-min-microvolt = <3300000>;
1167                                 regulator-max-microvolt = <3300000>;
1168                         };
1169                 };
1170
1171                 pwr_mcu: pwr_mcu@50001014 {
1172                         compatible = "st,stm32mp151-pwr-mcu", "syscon";
1173                         reg = <0x50001014 0x4>;
1174                 };
1175
1176                 exti: interrupt-controller@5000d000 {
1177                         compatible = "st,stm32mp1-exti", "syscon";
1178                         interrupt-controller;
1179                         #interrupt-cells = <2>;
1180                         reg = <0x5000d000 0x400>;
1181                 };
1182
1183                 syscfg: syscon@50020000 {
1184                         compatible = "st,stm32mp157-syscfg", "syscon";
1185                         reg = <0x50020000 0x400>;
1186                         clocks = <&rcc SYSCFG>;
1187                 };
1188
1189                 lptimer2: timer@50021000 {
1190                         #address-cells = <1>;
1191                         #size-cells = <0>;
1192                         compatible = "st,stm32-lptimer";
1193                         reg = <0x50021000 0x400>;
1194                         interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1195                         clocks = <&rcc LPTIM2_K>;
1196                         clock-names = "mux";
1197                         wakeup-source;
1198                         status = "disabled";
1199
1200                         pwm {
1201                                 compatible = "st,stm32-pwm-lp";
1202                                 #pwm-cells = <3>;
1203                                 status = "disabled";
1204                         };
1205
1206                         trigger@1 {
1207                                 compatible = "st,stm32-lptimer-trigger";
1208                                 reg = <1>;
1209                                 status = "disabled";
1210                         };
1211
1212                         counter {
1213                                 compatible = "st,stm32-lptimer-counter";
1214                                 status = "disabled";
1215                         };
1216                 };
1217
1218                 lptimer3: timer@50022000 {
1219                         #address-cells = <1>;
1220                         #size-cells = <0>;
1221                         compatible = "st,stm32-lptimer";
1222                         reg = <0x50022000 0x400>;
1223                         interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1224                         clocks = <&rcc LPTIM3_K>;
1225                         clock-names = "mux";
1226                         wakeup-source;
1227                         status = "disabled";
1228
1229                         pwm {
1230                                 compatible = "st,stm32-pwm-lp";
1231                                 #pwm-cells = <3>;
1232                                 status = "disabled";
1233                         };
1234
1235                         trigger@2 {
1236                                 compatible = "st,stm32-lptimer-trigger";
1237                                 reg = <2>;
1238                                 status = "disabled";
1239                         };
1240                 };
1241
1242                 lptimer4: timer@50023000 {
1243                         compatible = "st,stm32-lptimer";
1244                         reg = <0x50023000 0x400>;
1245                         interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1246                         clocks = <&rcc LPTIM4_K>;
1247                         clock-names = "mux";
1248                         wakeup-source;
1249                         status = "disabled";
1250
1251                         pwm {
1252                                 compatible = "st,stm32-pwm-lp";
1253                                 #pwm-cells = <3>;
1254                                 status = "disabled";
1255                         };
1256                 };
1257
1258                 lptimer5: timer@50024000 {
1259                         compatible = "st,stm32-lptimer";
1260                         reg = <0x50024000 0x400>;
1261                         interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1262                         clocks = <&rcc LPTIM5_K>;
1263                         clock-names = "mux";
1264                         wakeup-source;
1265                         status = "disabled";
1266
1267                         pwm {
1268                                 compatible = "st,stm32-pwm-lp";
1269                                 #pwm-cells = <3>;
1270                                 status = "disabled";
1271                         };
1272                 };
1273
1274                 vrefbuf: vrefbuf@50025000 {
1275                         compatible = "st,stm32-vrefbuf";
1276                         reg = <0x50025000 0x8>;
1277                         regulator-min-microvolt = <1500000>;
1278                         regulator-max-microvolt = <2500000>;
1279                         clocks = <&rcc VREF>;
1280                         status = "disabled";
1281                 };
1282
1283                 sai4: sai@50027000 {
1284                         compatible = "st,stm32h7-sai";
1285                         #address-cells = <1>;
1286                         #size-cells = <1>;
1287                         ranges = <0 0x50027000 0x400>;
1288                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1289                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1290                         resets = <&rcc SAI4_R>;
1291                         status = "disabled";
1292
1293                         sai4a: audio-controller@50027004 {
1294                                 #sound-dai-cells = <0>;
1295                                 compatible = "st,stm32-sai-sub-a";
1296                                 reg = <0x04 0x20>;
1297                                 clocks = <&rcc SAI4_K>;
1298                                 clock-names = "sai_ck";
1299                                 dmas = <&dmamux1 99 0x400 0x01>;
1300                                 status = "disabled";
1301                         };
1302
1303                         sai4b: audio-controller@50027024 {
1304                                 #sound-dai-cells = <0>;
1305                                 compatible = "st,stm32-sai-sub-b";
1306                                 reg = <0x24 0x20>;
1307                                 clocks = <&rcc SAI4_K>;
1308                                 clock-names = "sai_ck";
1309                                 dmas = <&dmamux1 100 0x400 0x01>;
1310                                 status = "disabled";
1311                         };
1312                 };
1313
1314                 dts: thermal@50028000 {
1315                         compatible = "st,stm32-thermal";
1316                         reg = <0x50028000 0x100>;
1317                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1318                         clocks = <&rcc TMPSENS>;
1319                         clock-names = "pclk";
1320                         #thermal-sensor-cells = <0>;
1321                         status = "disabled";
1322                 };
1323
1324                 hash1: hash@54002000 {
1325                         compatible = "st,stm32f756-hash";
1326                         reg = <0x54002000 0x400>;
1327                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1328                         clocks = <&rcc HASH1>;
1329                         resets = <&rcc HASH1_R>;
1330                         dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1331                         dma-names = "in";
1332                         dma-maxburst = <2>;
1333                         status = "disabled";
1334                 };
1335
1336                 rng1: rng@54003000 {
1337                         compatible = "st,stm32-rng";
1338                         reg = <0x54003000 0x400>;
1339                         clocks = <&rcc RNG1_K>;
1340                         resets = <&rcc RNG1_R>;
1341                         status = "disabled";
1342                 };
1343
1344                 mdma1: dma-controller@58000000 {
1345                         compatible = "st,stm32h7-mdma";
1346                         reg = <0x58000000 0x1000>;
1347                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1348                         clocks = <&rcc MDMA>;
1349                         resets = <&rcc MDMA_R>;
1350                         #dma-cells = <5>;
1351                         dma-channels = <32>;
1352                         dma-requests = <48>;
1353                 };
1354
1355                 fmc: memory-controller@58002000 {
1356                         #address-cells = <2>;
1357                         #size-cells = <1>;
1358                         compatible = "st,stm32mp1-fmc2-ebi";
1359                         reg = <0x58002000 0x1000>;
1360                         clocks = <&rcc FMC_K>;
1361                         resets = <&rcc FMC_R>;
1362                         status = "disabled";
1363
1364                         ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1365                                  <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1366                                  <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1367                                  <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1368                                  <4 0 0x80000000 0x10000000>; /* NAND */
1369
1370                         nand-controller@4,0 {
1371                                 #address-cells = <1>;
1372                                 #size-cells = <0>;
1373                                 compatible = "st,stm32mp1-fmc2-nfc";
1374                                 reg = <4 0x00000000 0x1000>,
1375                                       <4 0x08010000 0x1000>,
1376                                       <4 0x08020000 0x1000>,
1377                                       <4 0x01000000 0x1000>,
1378                                       <4 0x09010000 0x1000>,
1379                                       <4 0x09020000 0x1000>;
1380                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1381                                 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1382                                        <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1383                                        <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1384                                 dma-names = "tx", "rx", "ecc";
1385                                 status = "disabled";
1386                         };
1387                 };
1388
1389                 qspi: spi@58003000 {
1390                         compatible = "st,stm32f469-qspi";
1391                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1392                         reg-names = "qspi", "qspi_mm";
1393                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1394                         dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1395                                <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1396                         dma-names = "tx", "rx";
1397                         clocks = <&rcc QSPI_K>;
1398                         resets = <&rcc QSPI_R>;
1399                         #address-cells = <1>;
1400                         #size-cells = <0>;
1401                         status = "disabled";
1402                 };
1403
1404                 sdmmc1: mmc@58005000 {
1405                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1406                         arm,primecell-periphid = <0x00253180>;
1407                         reg = <0x58005000 0x1000>;
1408                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1409                         interrupt-names = "cmd_irq";
1410                         clocks = <&rcc SDMMC1_K>;
1411                         clock-names = "apb_pclk";
1412                         resets = <&rcc SDMMC1_R>;
1413                         cap-sd-highspeed;
1414                         cap-mmc-highspeed;
1415                         max-frequency = <120000000>;
1416                         status = "disabled";
1417                 };
1418
1419                 sdmmc2: mmc@58007000 {
1420                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1421                         arm,primecell-periphid = <0x00253180>;
1422                         reg = <0x58007000 0x1000>;
1423                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1424                         interrupt-names = "cmd_irq";
1425                         clocks = <&rcc SDMMC2_K>;
1426                         clock-names = "apb_pclk";
1427                         resets = <&rcc SDMMC2_R>;
1428                         cap-sd-highspeed;
1429                         cap-mmc-highspeed;
1430                         max-frequency = <120000000>;
1431                         status = "disabled";
1432                 };
1433
1434                 crc1: crc@58009000 {
1435                         compatible = "st,stm32f7-crc";
1436                         reg = <0x58009000 0x400>;
1437                         clocks = <&rcc CRC1>;
1438                         status = "disabled";
1439                 };
1440
1441                 ethernet0: ethernet@5800a000 {
1442                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1443                         reg = <0x5800a000 0x2000>;
1444                         reg-names = "stmmaceth";
1445                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1446                         interrupt-names = "macirq";
1447                         clock-names = "stmmaceth",
1448                                       "mac-clk-tx",
1449                                       "mac-clk-rx",
1450                                       "eth-ck",
1451                                       "ptp_ref",
1452                                       "ethstp";
1453                         clocks = <&rcc ETHMAC>,
1454                                  <&rcc ETHTX>,
1455                                  <&rcc ETHRX>,
1456                                  <&rcc ETHCK_K>,
1457                                  <&rcc ETHPTP_K>,
1458                                  <&rcc ETHSTP>;
1459                         st,syscon = <&syscfg 0x4>;
1460                         snps,mixed-burst;
1461                         snps,pbl = <2>;
1462                         snps,en-tx-lpi-clockgating;
1463                         snps,axi-config = <&stmmac_axi_config_0>;
1464                         snps,tso;
1465                         status = "disabled";
1466
1467                         stmmac_axi_config_0: stmmac-axi-config {
1468                                 snps,wr_osr_lmt = <0x7>;
1469                                 snps,rd_osr_lmt = <0x7>;
1470                                 snps,blen = <0 0 0 0 16 8 4>;
1471                         };
1472                 };
1473
1474                 usbh_ohci: usb@5800c000 {
1475                         compatible = "generic-ohci";
1476                         reg = <0x5800c000 0x1000>;
1477                         clocks = <&usbphyc>, <&rcc USBH>;
1478                         resets = <&rcc USBH_R>;
1479                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1480                         status = "disabled";
1481                 };
1482
1483                 usbh_ehci: usb@5800d000 {
1484                         compatible = "generic-ehci";
1485                         reg = <0x5800d000 0x1000>;
1486                         clocks = <&usbphyc>, <&rcc USBH>;
1487                         resets = <&rcc USBH_R>;
1488                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1489                         companion = <&usbh_ohci>;
1490                         status = "disabled";
1491                 };
1492
1493                 ltdc: display-controller@5a001000 {
1494                         compatible = "st,stm32-ltdc";
1495                         reg = <0x5a001000 0x400>;
1496                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1497                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1498                         clocks = <&rcc LTDC_PX>;
1499                         clock-names = "lcd";
1500                         resets = <&rcc LTDC_R>;
1501                         status = "disabled";
1502
1503                         port {
1504                                 #address-cells = <1>;
1505                                 #size-cells = <0>;
1506                         };
1507                 };
1508
1509                 iwdg2: watchdog@5a002000 {
1510                         compatible = "st,stm32mp1-iwdg";
1511                         reg = <0x5a002000 0x400>;
1512                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1513                         clock-names = "pclk", "lsi";
1514                         status = "disabled";
1515                 };
1516
1517                 usbphyc: usbphyc@5a006000 {
1518                         #address-cells = <1>;
1519                         #size-cells = <0>;
1520                         #clock-cells = <0>;
1521                         compatible = "st,stm32mp1-usbphyc";
1522                         reg = <0x5a006000 0x1000>;
1523                         clocks = <&rcc USBPHY_K>;
1524                         resets = <&rcc USBPHY_R>;
1525                         vdda1v1-supply = <&reg11>;
1526                         vdda1v8-supply = <&reg18>;
1527                         status = "disabled";
1528
1529                         usbphyc_port0: usb-phy@0 {
1530                                 #phy-cells = <0>;
1531                                 reg = <0>;
1532                         };
1533
1534                         usbphyc_port1: usb-phy@1 {
1535                                 #phy-cells = <1>;
1536                                 reg = <1>;
1537                         };
1538                 };
1539
1540                 usart1: serial@5c000000 {
1541                         compatible = "st,stm32h7-uart";
1542                         reg = <0x5c000000 0x400>;
1543                         interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1544                         clocks = <&rcc USART1_K>;
1545                         wakeup-source;
1546                         status = "disabled";
1547                 };
1548
1549                 spi6: spi@5c001000 {
1550                         #address-cells = <1>;
1551                         #size-cells = <0>;
1552                         compatible = "st,stm32h7-spi";
1553                         reg = <0x5c001000 0x400>;
1554                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1555                         clocks = <&rcc SPI6_K>;
1556                         resets = <&rcc SPI6_R>;
1557                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1558                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1559                         dma-names = "rx", "tx";
1560                         status = "disabled";
1561                 };
1562
1563                 i2c4: i2c@5c002000 {
1564                         compatible = "st,stm32mp15-i2c";
1565                         reg = <0x5c002000 0x400>;
1566                         interrupt-names = "event", "error";
1567                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1568                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1569                         clocks = <&rcc I2C4_K>;
1570                         resets = <&rcc I2C4_R>;
1571                         #address-cells = <1>;
1572                         #size-cells = <0>;
1573                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
1574                         wakeup-source;
1575                         i2c-analog-filter;
1576                         status = "disabled";
1577                 };
1578
1579                 rtc: rtc@5c004000 {
1580                         compatible = "st,stm32mp1-rtc";
1581                         reg = <0x5c004000 0x400>;
1582                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1583                         clock-names = "pclk", "rtc_ck";
1584                         interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1585                         status = "disabled";
1586                 };
1587
1588                 bsec: efuse@5c005000 {
1589                         compatible = "st,stm32mp15-bsec";
1590                         reg = <0x5c005000 0x400>;
1591                         #address-cells = <1>;
1592                         #size-cells = <1>;
1593                         ts_cal1: calib@5c {
1594                                 reg = <0x5c 0x2>;
1595                         };
1596                         ts_cal2: calib@5e {
1597                                 reg = <0x5e 0x2>;
1598                         };
1599                 };
1600
1601                 i2c6: i2c@5c009000 {
1602                         compatible = "st,stm32mp15-i2c";
1603                         reg = <0x5c009000 0x400>;
1604                         interrupt-names = "event", "error";
1605                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1606                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1607                         clocks = <&rcc I2C6_K>;
1608                         resets = <&rcc I2C6_R>;
1609                         #address-cells = <1>;
1610                         #size-cells = <0>;
1611                         st,syscfg-fmp = <&syscfg 0x4 0x20>;
1612                         wakeup-source;
1613                         i2c-analog-filter;
1614                         status = "disabled";
1615                 };
1616
1617                 tamp: tamp@5c00a000 {
1618                         compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1619                         reg = <0x5c00a000 0x400>;
1620                 };
1621
1622                 /*
1623                  * Break node order to solve dependency probe issue between
1624                  * pinctrl and exti.
1625                  */
1626                 pinctrl: pinctrl@50002000 {
1627                         #address-cells = <1>;
1628                         #size-cells = <1>;
1629                         compatible = "st,stm32mp157-pinctrl";
1630                         ranges = <0 0x50002000 0xa400>;
1631                         interrupt-parent = <&exti>;
1632                         st,syscfg = <&exti 0x60 0xff>;
1633                         pins-are-numbered;
1634
1635                         gpioa: gpio@50002000 {
1636                                 gpio-controller;
1637                                 #gpio-cells = <2>;
1638                                 interrupt-controller;
1639                                 #interrupt-cells = <2>;
1640                                 reg = <0x0 0x400>;
1641                                 clocks = <&rcc GPIOA>;
1642                                 st,bank-name = "GPIOA";
1643                                 status = "disabled";
1644                         };
1645
1646                         gpiob: gpio@50003000 {
1647                                 gpio-controller;
1648                                 #gpio-cells = <2>;
1649                                 interrupt-controller;
1650                                 #interrupt-cells = <2>;
1651                                 reg = <0x1000 0x400>;
1652                                 clocks = <&rcc GPIOB>;
1653                                 st,bank-name = "GPIOB";
1654                                 status = "disabled";
1655                         };
1656
1657                         gpioc: gpio@50004000 {
1658                                 gpio-controller;
1659                                 #gpio-cells = <2>;
1660                                 interrupt-controller;
1661                                 #interrupt-cells = <2>;
1662                                 reg = <0x2000 0x400>;
1663                                 clocks = <&rcc GPIOC>;
1664                                 st,bank-name = "GPIOC";
1665                                 status = "disabled";
1666                         };
1667
1668                         gpiod: gpio@50005000 {
1669                                 gpio-controller;
1670                                 #gpio-cells = <2>;
1671                                 interrupt-controller;
1672                                 #interrupt-cells = <2>;
1673                                 reg = <0x3000 0x400>;
1674                                 clocks = <&rcc GPIOD>;
1675                                 st,bank-name = "GPIOD";
1676                                 status = "disabled";
1677                         };
1678
1679                         gpioe: gpio@50006000 {
1680                                 gpio-controller;
1681                                 #gpio-cells = <2>;
1682                                 interrupt-controller;
1683                                 #interrupt-cells = <2>;
1684                                 reg = <0x4000 0x400>;
1685                                 clocks = <&rcc GPIOE>;
1686                                 st,bank-name = "GPIOE";
1687                                 status = "disabled";
1688                         };
1689
1690                         gpiof: gpio@50007000 {
1691                                 gpio-controller;
1692                                 #gpio-cells = <2>;
1693                                 interrupt-controller;
1694                                 #interrupt-cells = <2>;
1695                                 reg = <0x5000 0x400>;
1696                                 clocks = <&rcc GPIOF>;
1697                                 st,bank-name = "GPIOF";
1698                                 status = "disabled";
1699                         };
1700
1701                         gpiog: gpio@50008000 {
1702                                 gpio-controller;
1703                                 #gpio-cells = <2>;
1704                                 interrupt-controller;
1705                                 #interrupt-cells = <2>;
1706                                 reg = <0x6000 0x400>;
1707                                 clocks = <&rcc GPIOG>;
1708                                 st,bank-name = "GPIOG";
1709                                 status = "disabled";
1710                         };
1711
1712                         gpioh: gpio@50009000 {
1713                                 gpio-controller;
1714                                 #gpio-cells = <2>;
1715                                 interrupt-controller;
1716                                 #interrupt-cells = <2>;
1717                                 reg = <0x7000 0x400>;
1718                                 clocks = <&rcc GPIOH>;
1719                                 st,bank-name = "GPIOH";
1720                                 status = "disabled";
1721                         };
1722
1723                         gpioi: gpio@5000a000 {
1724                                 gpio-controller;
1725                                 #gpio-cells = <2>;
1726                                 interrupt-controller;
1727                                 #interrupt-cells = <2>;
1728                                 reg = <0x8000 0x400>;
1729                                 clocks = <&rcc GPIOI>;
1730                                 st,bank-name = "GPIOI";
1731                                 status = "disabled";
1732                         };
1733
1734                         gpioj: gpio@5000b000 {
1735                                 gpio-controller;
1736                                 #gpio-cells = <2>;
1737                                 interrupt-controller;
1738                                 #interrupt-cells = <2>;
1739                                 reg = <0x9000 0x400>;
1740                                 clocks = <&rcc GPIOJ>;
1741                                 st,bank-name = "GPIOJ";
1742                                 status = "disabled";
1743                         };
1744
1745                         gpiok: gpio@5000c000 {
1746                                 gpio-controller;
1747                                 #gpio-cells = <2>;
1748                                 interrupt-controller;
1749                                 #interrupt-cells = <2>;
1750                                 reg = <0xa000 0x400>;
1751                                 clocks = <&rcc GPIOK>;
1752                                 st,bank-name = "GPIOK";
1753                                 status = "disabled";
1754                         };
1755                 };
1756
1757                 pinctrl_z: pinctrl@54004000 {
1758                         #address-cells = <1>;
1759                         #size-cells = <1>;
1760                         compatible = "st,stm32mp157-z-pinctrl";
1761                         ranges = <0 0x54004000 0x400>;
1762                         pins-are-numbered;
1763                         interrupt-parent = <&exti>;
1764                         st,syscfg = <&exti 0x60 0xff>;
1765
1766                         gpioz: gpio@54004000 {
1767                                 gpio-controller;
1768                                 #gpio-cells = <2>;
1769                                 interrupt-controller;
1770                                 #interrupt-cells = <2>;
1771                                 reg = <0 0x400>;
1772                                 clocks = <&rcc GPIOZ>;
1773                                 st,bank-name = "GPIOZ";
1774                                 st,bank-ioport = <11>;
1775                                 status = "disabled";
1776                         };
1777                 };
1778         };
1779
1780         mlahb: ahb {
1781                 compatible = "st,mlahb", "simple-bus";
1782                 #address-cells = <1>;
1783                 #size-cells = <1>;
1784                 ranges;
1785                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1786                              <0x10000000 0x10000000 0x60000>,
1787                              <0x30000000 0x30000000 0x60000>;
1788
1789                 m4_rproc: m4@10000000 {
1790                         compatible = "st,stm32mp1-m4";
1791                         reg = <0x10000000 0x40000>,
1792                               <0x30000000 0x40000>,
1793                               <0x38000000 0x10000>;
1794                         resets = <&rcc MCU_R>;
1795                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1796                         st,syscfg-tz = <&rcc 0x000 0x1>;
1797                         st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1798                         st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1799                         st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1800                         status = "disabled";
1801                 };
1802         };
1803 };