1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
27 compatible = "arm,cortex-a7-pmu";
28 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
29 interrupt-affinity = <&cpu0>;
30 interrupt-parent = <&intc>;
34 compatible = "arm,psci-1.0";
38 intc: interrupt-controller@a0021000 {
39 compatible = "arm,cortex-a7-gic";
40 #interrupt-cells = <3>;
42 reg = <0xa0021000 0x1000>,
47 compatible = "arm,armv7-timer";
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
52 interrupt-parent = <&intc>;
58 compatible = "fixed-clock";
59 clock-frequency = <24000000>;
64 compatible = "fixed-clock";
65 clock-frequency = <64000000>;
70 compatible = "fixed-clock";
71 clock-frequency = <32768>;
76 compatible = "fixed-clock";
77 clock-frequency = <32000>;
82 compatible = "fixed-clock";
83 clock-frequency = <4000000>;
88 cpu_thermal: cpu-thermal {
89 polling-delay-passive = <0>;
91 thermal-sensors = <&dts>;
94 cpu_alert1: cpu-alert1 {
95 temperature = <85000>;
101 temperature = <120000>;
112 booster: regulator-booster {
113 compatible = "st,stm32mp1-booster";
114 st,syscfg = <&syscfg>;
119 compatible = "simple-bus";
120 #address-cells = <1>;
122 interrupt-parent = <&intc>;
125 timers2: timer@40000000 {
126 #address-cells = <1>;
128 compatible = "st,stm32-timers";
129 reg = <0x40000000 0x400>;
130 clocks = <&rcc TIM2_K>;
132 dmas = <&dmamux1 18 0x400 0x1>,
133 <&dmamux1 19 0x400 0x1>,
134 <&dmamux1 20 0x400 0x1>,
135 <&dmamux1 21 0x400 0x1>,
136 <&dmamux1 22 0x400 0x1>;
137 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
141 compatible = "st,stm32-pwm";
147 compatible = "st,stm32h7-timer-trigger";
153 compatible = "st,stm32-timer-counter";
158 timers3: timer@40001000 {
159 #address-cells = <1>;
161 compatible = "st,stm32-timers";
162 reg = <0x40001000 0x400>;
163 clocks = <&rcc TIM3_K>;
165 dmas = <&dmamux1 23 0x400 0x1>,
166 <&dmamux1 24 0x400 0x1>,
167 <&dmamux1 25 0x400 0x1>,
168 <&dmamux1 26 0x400 0x1>,
169 <&dmamux1 27 0x400 0x1>,
170 <&dmamux1 28 0x400 0x1>;
171 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
175 compatible = "st,stm32-pwm";
181 compatible = "st,stm32h7-timer-trigger";
187 compatible = "st,stm32-timer-counter";
192 timers4: timer@40002000 {
193 #address-cells = <1>;
195 compatible = "st,stm32-timers";
196 reg = <0x40002000 0x400>;
197 clocks = <&rcc TIM4_K>;
199 dmas = <&dmamux1 29 0x400 0x1>,
200 <&dmamux1 30 0x400 0x1>,
201 <&dmamux1 31 0x400 0x1>,
202 <&dmamux1 32 0x400 0x1>;
203 dma-names = "ch1", "ch2", "ch3", "ch4";
207 compatible = "st,stm32-pwm";
213 compatible = "st,stm32h7-timer-trigger";
219 compatible = "st,stm32-timer-counter";
224 timers5: timer@40003000 {
225 #address-cells = <1>;
227 compatible = "st,stm32-timers";
228 reg = <0x40003000 0x400>;
229 clocks = <&rcc TIM5_K>;
231 dmas = <&dmamux1 55 0x400 0x1>,
232 <&dmamux1 56 0x400 0x1>,
233 <&dmamux1 57 0x400 0x1>,
234 <&dmamux1 58 0x400 0x1>,
235 <&dmamux1 59 0x400 0x1>,
236 <&dmamux1 60 0x400 0x1>;
237 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
241 compatible = "st,stm32-pwm";
247 compatible = "st,stm32h7-timer-trigger";
253 compatible = "st,stm32-timer-counter";
258 timers6: timer@40004000 {
259 #address-cells = <1>;
261 compatible = "st,stm32-timers";
262 reg = <0x40004000 0x400>;
263 clocks = <&rcc TIM6_K>;
265 dmas = <&dmamux1 69 0x400 0x1>;
270 compatible = "st,stm32h7-timer-trigger";
276 timers7: timer@40005000 {
277 #address-cells = <1>;
279 compatible = "st,stm32-timers";
280 reg = <0x40005000 0x400>;
281 clocks = <&rcc TIM7_K>;
283 dmas = <&dmamux1 70 0x400 0x1>;
288 compatible = "st,stm32h7-timer-trigger";
294 timers12: timer@40006000 {
295 #address-cells = <1>;
297 compatible = "st,stm32-timers";
298 reg = <0x40006000 0x400>;
299 clocks = <&rcc TIM12_K>;
304 compatible = "st,stm32-pwm";
310 compatible = "st,stm32h7-timer-trigger";
316 timers13: timer@40007000 {
317 #address-cells = <1>;
319 compatible = "st,stm32-timers";
320 reg = <0x40007000 0x400>;
321 clocks = <&rcc TIM13_K>;
326 compatible = "st,stm32-pwm";
332 compatible = "st,stm32h7-timer-trigger";
338 timers14: timer@40008000 {
339 #address-cells = <1>;
341 compatible = "st,stm32-timers";
342 reg = <0x40008000 0x400>;
343 clocks = <&rcc TIM14_K>;
348 compatible = "st,stm32-pwm";
354 compatible = "st,stm32h7-timer-trigger";
360 lptimer1: timer@40009000 {
361 #address-cells = <1>;
363 compatible = "st,stm32-lptimer";
364 reg = <0x40009000 0x400>;
365 interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
366 clocks = <&rcc LPTIM1_K>;
372 compatible = "st,stm32-pwm-lp";
378 compatible = "st,stm32-lptimer-trigger";
384 compatible = "st,stm32-lptimer-counter";
390 #address-cells = <1>;
392 compatible = "st,stm32h7-spi";
393 reg = <0x4000b000 0x400>;
394 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&rcc SPI2_K>;
396 resets = <&rcc SPI2_R>;
397 dmas = <&dmamux1 39 0x400 0x05>,
398 <&dmamux1 40 0x400 0x05>;
399 dma-names = "rx", "tx";
403 i2s2: audio-controller@4000b000 {
404 compatible = "st,stm32h7-i2s";
405 #sound-dai-cells = <0>;
406 reg = <0x4000b000 0x400>;
407 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
408 dmas = <&dmamux1 39 0x400 0x01>,
409 <&dmamux1 40 0x400 0x01>;
410 dma-names = "rx", "tx";
415 #address-cells = <1>;
417 compatible = "st,stm32h7-spi";
418 reg = <0x4000c000 0x400>;
419 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&rcc SPI3_K>;
421 resets = <&rcc SPI3_R>;
422 dmas = <&dmamux1 61 0x400 0x05>,
423 <&dmamux1 62 0x400 0x05>;
424 dma-names = "rx", "tx";
428 i2s3: audio-controller@4000c000 {
429 compatible = "st,stm32h7-i2s";
430 #sound-dai-cells = <0>;
431 reg = <0x4000c000 0x400>;
432 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
433 dmas = <&dmamux1 61 0x400 0x01>,
434 <&dmamux1 62 0x400 0x01>;
435 dma-names = "rx", "tx";
439 spdifrx: audio-controller@4000d000 {
440 compatible = "st,stm32h7-spdifrx";
441 #sound-dai-cells = <0>;
442 reg = <0x4000d000 0x400>;
443 clocks = <&rcc SPDIF_K>;
444 clock-names = "kclk";
445 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
446 dmas = <&dmamux1 93 0x400 0x01>,
447 <&dmamux1 94 0x400 0x01>;
448 dma-names = "rx", "rx-ctrl";
452 usart2: serial@4000e000 {
453 compatible = "st,stm32h7-uart";
454 reg = <0x4000e000 0x400>;
455 interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&rcc USART2_K>;
458 dmas = <&dmamux1 43 0x400 0x15>,
459 <&dmamux1 44 0x400 0x11>;
460 dma-names = "rx", "tx";
464 usart3: serial@4000f000 {
465 compatible = "st,stm32h7-uart";
466 reg = <0x4000f000 0x400>;
467 interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&rcc USART3_K>;
470 dmas = <&dmamux1 45 0x400 0x15>,
471 <&dmamux1 46 0x400 0x11>;
472 dma-names = "rx", "tx";
476 uart4: serial@40010000 {
477 compatible = "st,stm32h7-uart";
478 reg = <0x40010000 0x400>;
479 interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
480 clocks = <&rcc UART4_K>;
482 dmas = <&dmamux1 63 0x400 0x15>,
483 <&dmamux1 64 0x400 0x11>;
484 dma-names = "rx", "tx";
488 uart5: serial@40011000 {
489 compatible = "st,stm32h7-uart";
490 reg = <0x40011000 0x400>;
491 interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
492 clocks = <&rcc UART5_K>;
494 dmas = <&dmamux1 65 0x400 0x15>,
495 <&dmamux1 66 0x400 0x11>;
496 dma-names = "rx", "tx";
501 compatible = "st,stm32mp15-i2c";
502 reg = <0x40012000 0x400>;
503 interrupt-names = "event", "error";
504 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&rcc I2C1_K>;
507 resets = <&rcc I2C1_R>;
508 #address-cells = <1>;
510 st,syscfg-fmp = <&syscfg 0x4 0x1>;
517 compatible = "st,stm32mp15-i2c";
518 reg = <0x40013000 0x400>;
519 interrupt-names = "event", "error";
520 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&rcc I2C2_K>;
523 resets = <&rcc I2C2_R>;
524 #address-cells = <1>;
526 st,syscfg-fmp = <&syscfg 0x4 0x2>;
533 compatible = "st,stm32mp15-i2c";
534 reg = <0x40014000 0x400>;
535 interrupt-names = "event", "error";
536 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&rcc I2C3_K>;
539 resets = <&rcc I2C3_R>;
540 #address-cells = <1>;
542 st,syscfg-fmp = <&syscfg 0x4 0x4>;
549 compatible = "st,stm32mp15-i2c";
550 reg = <0x40015000 0x400>;
551 interrupt-names = "event", "error";
552 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&rcc I2C5_K>;
555 resets = <&rcc I2C5_R>;
556 #address-cells = <1>;
558 st,syscfg-fmp = <&syscfg 0x4 0x10>;
565 compatible = "st,stm32-cec";
566 reg = <0x40016000 0x400>;
567 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&rcc CEC_K>, <&rcc CEC>;
569 clock-names = "cec", "hdmi-cec";
574 compatible = "st,stm32h7-dac-core";
575 reg = <0x40017000 0x400>;
576 clocks = <&rcc DAC12>;
577 clock-names = "pclk";
578 #address-cells = <1>;
583 compatible = "st,stm32-dac";
584 #io-channel-cells = <1>;
590 compatible = "st,stm32-dac";
591 #io-channel-cells = <1>;
597 uart7: serial@40018000 {
598 compatible = "st,stm32h7-uart";
599 reg = <0x40018000 0x400>;
600 interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&rcc UART7_K>;
603 dmas = <&dmamux1 79 0x400 0x15>,
604 <&dmamux1 80 0x400 0x11>;
605 dma-names = "rx", "tx";
609 uart8: serial@40019000 {
610 compatible = "st,stm32h7-uart";
611 reg = <0x40019000 0x400>;
612 interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&rcc UART8_K>;
615 dmas = <&dmamux1 81 0x400 0x15>,
616 <&dmamux1 82 0x400 0x11>;
617 dma-names = "rx", "tx";
621 timers1: timer@44000000 {
622 #address-cells = <1>;
624 compatible = "st,stm32-timers";
625 reg = <0x44000000 0x400>;
626 clocks = <&rcc TIM1_K>;
628 dmas = <&dmamux1 11 0x400 0x1>,
629 <&dmamux1 12 0x400 0x1>,
630 <&dmamux1 13 0x400 0x1>,
631 <&dmamux1 14 0x400 0x1>,
632 <&dmamux1 15 0x400 0x1>,
633 <&dmamux1 16 0x400 0x1>,
634 <&dmamux1 17 0x400 0x1>;
635 dma-names = "ch1", "ch2", "ch3", "ch4",
640 compatible = "st,stm32-pwm";
646 compatible = "st,stm32h7-timer-trigger";
652 compatible = "st,stm32-timer-counter";
657 timers8: timer@44001000 {
658 #address-cells = <1>;
660 compatible = "st,stm32-timers";
661 reg = <0x44001000 0x400>;
662 clocks = <&rcc TIM8_K>;
664 dmas = <&dmamux1 47 0x400 0x1>,
665 <&dmamux1 48 0x400 0x1>,
666 <&dmamux1 49 0x400 0x1>,
667 <&dmamux1 50 0x400 0x1>,
668 <&dmamux1 51 0x400 0x1>,
669 <&dmamux1 52 0x400 0x1>,
670 <&dmamux1 53 0x400 0x1>;
671 dma-names = "ch1", "ch2", "ch3", "ch4",
676 compatible = "st,stm32-pwm";
682 compatible = "st,stm32h7-timer-trigger";
688 compatible = "st,stm32-timer-counter";
693 usart6: serial@44003000 {
694 compatible = "st,stm32h7-uart";
695 reg = <0x44003000 0x400>;
696 interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&rcc USART6_K>;
699 dmas = <&dmamux1 71 0x400 0x15>,
700 <&dmamux1 72 0x400 0x11>;
701 dma-names = "rx", "tx";
706 #address-cells = <1>;
708 compatible = "st,stm32h7-spi";
709 reg = <0x44004000 0x400>;
710 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&rcc SPI1_K>;
712 resets = <&rcc SPI1_R>;
713 dmas = <&dmamux1 37 0x400 0x05>,
714 <&dmamux1 38 0x400 0x05>;
715 dma-names = "rx", "tx";
719 i2s1: audio-controller@44004000 {
720 compatible = "st,stm32h7-i2s";
721 #sound-dai-cells = <0>;
722 reg = <0x44004000 0x400>;
723 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
724 dmas = <&dmamux1 37 0x400 0x01>,
725 <&dmamux1 38 0x400 0x01>;
726 dma-names = "rx", "tx";
731 #address-cells = <1>;
733 compatible = "st,stm32h7-spi";
734 reg = <0x44005000 0x400>;
735 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&rcc SPI4_K>;
737 resets = <&rcc SPI4_R>;
738 dmas = <&dmamux1 83 0x400 0x05>,
739 <&dmamux1 84 0x400 0x05>;
740 dma-names = "rx", "tx";
744 timers15: timer@44006000 {
745 #address-cells = <1>;
747 compatible = "st,stm32-timers";
748 reg = <0x44006000 0x400>;
749 clocks = <&rcc TIM15_K>;
751 dmas = <&dmamux1 105 0x400 0x1>,
752 <&dmamux1 106 0x400 0x1>,
753 <&dmamux1 107 0x400 0x1>,
754 <&dmamux1 108 0x400 0x1>;
755 dma-names = "ch1", "up", "trig", "com";
759 compatible = "st,stm32-pwm";
765 compatible = "st,stm32h7-timer-trigger";
771 timers16: timer@44007000 {
772 #address-cells = <1>;
774 compatible = "st,stm32-timers";
775 reg = <0x44007000 0x400>;
776 clocks = <&rcc TIM16_K>;
778 dmas = <&dmamux1 109 0x400 0x1>,
779 <&dmamux1 110 0x400 0x1>;
780 dma-names = "ch1", "up";
784 compatible = "st,stm32-pwm";
789 compatible = "st,stm32h7-timer-trigger";
795 timers17: timer@44008000 {
796 #address-cells = <1>;
798 compatible = "st,stm32-timers";
799 reg = <0x44008000 0x400>;
800 clocks = <&rcc TIM17_K>;
802 dmas = <&dmamux1 111 0x400 0x1>,
803 <&dmamux1 112 0x400 0x1>;
804 dma-names = "ch1", "up";
808 compatible = "st,stm32-pwm";
814 compatible = "st,stm32h7-timer-trigger";
821 #address-cells = <1>;
823 compatible = "st,stm32h7-spi";
824 reg = <0x44009000 0x400>;
825 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&rcc SPI5_K>;
827 resets = <&rcc SPI5_R>;
828 dmas = <&dmamux1 85 0x400 0x05>,
829 <&dmamux1 86 0x400 0x05>;
830 dma-names = "rx", "tx";
835 compatible = "st,stm32h7-sai";
836 #address-cells = <1>;
838 ranges = <0 0x4400a000 0x400>;
839 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
840 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
841 resets = <&rcc SAI1_R>;
844 sai1a: audio-controller@4400a004 {
845 #sound-dai-cells = <0>;
847 compatible = "st,stm32-sai-sub-a";
849 clocks = <&rcc SAI1_K>;
850 clock-names = "sai_ck";
851 dmas = <&dmamux1 87 0x400 0x01>;
855 sai1b: audio-controller@4400a024 {
856 #sound-dai-cells = <0>;
857 compatible = "st,stm32-sai-sub-b";
859 clocks = <&rcc SAI1_K>;
860 clock-names = "sai_ck";
861 dmas = <&dmamux1 88 0x400 0x01>;
867 compatible = "st,stm32h7-sai";
868 #address-cells = <1>;
870 ranges = <0 0x4400b000 0x400>;
871 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
872 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
873 resets = <&rcc SAI2_R>;
876 sai2a: audio-controller@4400b004 {
877 #sound-dai-cells = <0>;
878 compatible = "st,stm32-sai-sub-a";
880 clocks = <&rcc SAI2_K>;
881 clock-names = "sai_ck";
882 dmas = <&dmamux1 89 0x400 0x01>;
886 sai2b: audio-controller@4400b024 {
887 #sound-dai-cells = <0>;
888 compatible = "st,stm32-sai-sub-b";
890 clocks = <&rcc SAI2_K>;
891 clock-names = "sai_ck";
892 dmas = <&dmamux1 90 0x400 0x01>;
898 compatible = "st,stm32h7-sai";
899 #address-cells = <1>;
901 ranges = <0 0x4400c000 0x400>;
902 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
903 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
904 resets = <&rcc SAI3_R>;
907 sai3a: audio-controller@4400c004 {
908 #sound-dai-cells = <0>;
909 compatible = "st,stm32-sai-sub-a";
911 clocks = <&rcc SAI3_K>;
912 clock-names = "sai_ck";
913 dmas = <&dmamux1 113 0x400 0x01>;
917 sai3b: audio-controller@4400c024 {
918 #sound-dai-cells = <0>;
919 compatible = "st,stm32-sai-sub-b";
921 clocks = <&rcc SAI3_K>;
922 clock-names = "sai_ck";
923 dmas = <&dmamux1 114 0x400 0x01>;
928 dfsdm: dfsdm@4400d000 {
929 compatible = "st,stm32mp1-dfsdm";
930 reg = <0x4400d000 0x800>;
931 clocks = <&rcc DFSDM_K>;
932 clock-names = "dfsdm";
933 #address-cells = <1>;
938 compatible = "st,stm32-dfsdm-adc";
939 #io-channel-cells = <1>;
941 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
942 dmas = <&dmamux1 101 0x400 0x01>;
948 compatible = "st,stm32-dfsdm-adc";
949 #io-channel-cells = <1>;
951 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
952 dmas = <&dmamux1 102 0x400 0x01>;
958 compatible = "st,stm32-dfsdm-adc";
959 #io-channel-cells = <1>;
961 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
962 dmas = <&dmamux1 103 0x400 0x01>;
968 compatible = "st,stm32-dfsdm-adc";
969 #io-channel-cells = <1>;
971 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
972 dmas = <&dmamux1 104 0x400 0x01>;
978 compatible = "st,stm32-dfsdm-adc";
979 #io-channel-cells = <1>;
981 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
982 dmas = <&dmamux1 91 0x400 0x01>;
988 compatible = "st,stm32-dfsdm-adc";
989 #io-channel-cells = <1>;
991 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
992 dmas = <&dmamux1 92 0x400 0x01>;
998 dma1: dma-controller@48000000 {
999 compatible = "st,stm32-dma";
1000 reg = <0x48000000 0x400>;
1001 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1002 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1003 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1004 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1005 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1006 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1007 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&rcc DMA1>;
1010 resets = <&rcc DMA1_R>;
1016 dma2: dma-controller@48001000 {
1017 compatible = "st,stm32-dma";
1018 reg = <0x48001000 0x400>;
1019 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1020 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1021 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1022 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1023 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1024 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1027 clocks = <&rcc DMA2>;
1028 resets = <&rcc DMA2_R>;
1034 dmamux1: dma-router@48002000 {
1035 compatible = "st,stm32h7-dmamux";
1036 reg = <0x48002000 0x40>;
1038 dma-requests = <128>;
1039 dma-masters = <&dma1 &dma2>;
1040 dma-channels = <16>;
1041 clocks = <&rcc DMAMUX>;
1042 resets = <&rcc DMAMUX_R>;
1046 compatible = "st,stm32mp1-adc-core";
1047 reg = <0x48003000 0x400>;
1048 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1049 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1051 clock-names = "bus", "adc";
1052 interrupt-controller;
1053 st,syscfg = <&syscfg>;
1054 #interrupt-cells = <1>;
1055 #address-cells = <1>;
1057 status = "disabled";
1060 compatible = "st,stm32mp1-adc";
1061 #io-channel-cells = <1>;
1063 interrupt-parent = <&adc>;
1065 dmas = <&dmamux1 9 0x400 0x01>;
1067 status = "disabled";
1071 compatible = "st,stm32mp1-adc";
1072 #io-channel-cells = <1>;
1074 interrupt-parent = <&adc>;
1076 dmas = <&dmamux1 10 0x400 0x01>;
1078 status = "disabled";
1082 sdmmc3: mmc@48004000 {
1083 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1084 arm,primecell-periphid = <0x00253180>;
1085 reg = <0x48004000 0x400>;
1086 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1087 interrupt-names = "cmd_irq";
1088 clocks = <&rcc SDMMC3_K>;
1089 clock-names = "apb_pclk";
1090 resets = <&rcc SDMMC3_R>;
1093 max-frequency = <120000000>;
1094 status = "disabled";
1097 usbotg_hs: usb-otg@49000000 {
1098 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1099 reg = <0x49000000 0x10000>;
1100 clocks = <&rcc USBO_K>;
1101 clock-names = "otg";
1102 resets = <&rcc USBO_R>;
1103 reset-names = "dwc2";
1104 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1105 g-rx-fifo-size = <512>;
1106 g-np-tx-fifo-size = <32>;
1107 g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1110 usb33d-supply = <&usb33>;
1111 status = "disabled";
1114 ipcc: mailbox@4c001000 {
1115 compatible = "st,stm32mp1-ipcc";
1117 reg = <0x4c001000 0x400>;
1119 interrupts-extended =
1121 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1122 interrupt-names = "rx", "tx";
1123 clocks = <&rcc IPCC>;
1125 status = "disabled";
1128 dcmi: dcmi@4c006000 {
1129 compatible = "st,stm32-dcmi";
1130 reg = <0x4c006000 0x400>;
1131 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1132 resets = <&rcc CAMITF_R>;
1133 clocks = <&rcc DCMI>;
1134 clock-names = "mclk";
1135 dmas = <&dmamux1 75 0x400 0x01>;
1137 status = "disabled";
1141 compatible = "st,stm32mp1-rcc", "syscon";
1142 reg = <0x50000000 0x1000>;
1147 pwr_regulators: pwr@50001000 {
1148 compatible = "st,stm32mp1,pwr-reg";
1149 reg = <0x50001000 0x10>;
1152 regulator-name = "reg11";
1153 regulator-min-microvolt = <1100000>;
1154 regulator-max-microvolt = <1100000>;
1158 regulator-name = "reg18";
1159 regulator-min-microvolt = <1800000>;
1160 regulator-max-microvolt = <1800000>;
1164 regulator-name = "usb33";
1165 regulator-min-microvolt = <3300000>;
1166 regulator-max-microvolt = <3300000>;
1170 pwr_mcu: pwr_mcu@50001014 {
1171 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1172 reg = <0x50001014 0x4>;
1175 exti: interrupt-controller@5000d000 {
1176 compatible = "st,stm32mp1-exti", "syscon";
1177 interrupt-controller;
1178 #interrupt-cells = <2>;
1179 reg = <0x5000d000 0x400>;
1182 syscfg: syscon@50020000 {
1183 compatible = "st,stm32mp157-syscfg", "syscon";
1184 reg = <0x50020000 0x400>;
1185 clocks = <&rcc SYSCFG>;
1188 lptimer2: timer@50021000 {
1189 #address-cells = <1>;
1191 compatible = "st,stm32-lptimer";
1192 reg = <0x50021000 0x400>;
1193 interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&rcc LPTIM2_K>;
1195 clock-names = "mux";
1197 status = "disabled";
1200 compatible = "st,stm32-pwm-lp";
1202 status = "disabled";
1206 compatible = "st,stm32-lptimer-trigger";
1208 status = "disabled";
1212 compatible = "st,stm32-lptimer-counter";
1213 status = "disabled";
1217 lptimer3: timer@50022000 {
1218 #address-cells = <1>;
1220 compatible = "st,stm32-lptimer";
1221 reg = <0x50022000 0x400>;
1222 interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1223 clocks = <&rcc LPTIM3_K>;
1224 clock-names = "mux";
1226 status = "disabled";
1229 compatible = "st,stm32-pwm-lp";
1231 status = "disabled";
1235 compatible = "st,stm32-lptimer-trigger";
1237 status = "disabled";
1241 lptimer4: timer@50023000 {
1242 compatible = "st,stm32-lptimer";
1243 reg = <0x50023000 0x400>;
1244 interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&rcc LPTIM4_K>;
1246 clock-names = "mux";
1248 status = "disabled";
1251 compatible = "st,stm32-pwm-lp";
1253 status = "disabled";
1257 lptimer5: timer@50024000 {
1258 compatible = "st,stm32-lptimer";
1259 reg = <0x50024000 0x400>;
1260 interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1261 clocks = <&rcc LPTIM5_K>;
1262 clock-names = "mux";
1264 status = "disabled";
1267 compatible = "st,stm32-pwm-lp";
1269 status = "disabled";
1273 vrefbuf: vrefbuf@50025000 {
1274 compatible = "st,stm32-vrefbuf";
1275 reg = <0x50025000 0x8>;
1276 regulator-min-microvolt = <1500000>;
1277 regulator-max-microvolt = <2500000>;
1278 clocks = <&rcc VREF>;
1279 status = "disabled";
1282 sai4: sai@50027000 {
1283 compatible = "st,stm32h7-sai";
1284 #address-cells = <1>;
1286 ranges = <0 0x50027000 0x400>;
1287 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1288 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1289 resets = <&rcc SAI4_R>;
1290 status = "disabled";
1292 sai4a: audio-controller@50027004 {
1293 #sound-dai-cells = <0>;
1294 compatible = "st,stm32-sai-sub-a";
1296 clocks = <&rcc SAI4_K>;
1297 clock-names = "sai_ck";
1298 dmas = <&dmamux1 99 0x400 0x01>;
1299 status = "disabled";
1302 sai4b: audio-controller@50027024 {
1303 #sound-dai-cells = <0>;
1304 compatible = "st,stm32-sai-sub-b";
1306 clocks = <&rcc SAI4_K>;
1307 clock-names = "sai_ck";
1308 dmas = <&dmamux1 100 0x400 0x01>;
1309 status = "disabled";
1313 dts: thermal@50028000 {
1314 compatible = "st,stm32-thermal";
1315 reg = <0x50028000 0x100>;
1316 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1317 clocks = <&rcc TMPSENS>;
1318 clock-names = "pclk";
1319 #thermal-sensor-cells = <0>;
1320 status = "disabled";
1323 hash1: hash@54002000 {
1324 compatible = "st,stm32f756-hash";
1325 reg = <0x54002000 0x400>;
1326 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1327 clocks = <&rcc HASH1>;
1328 resets = <&rcc HASH1_R>;
1329 dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1332 status = "disabled";
1335 rng1: rng@54003000 {
1336 compatible = "st,stm32-rng";
1337 reg = <0x54003000 0x400>;
1338 clocks = <&rcc RNG1_K>;
1339 resets = <&rcc RNG1_R>;
1340 status = "disabled";
1343 mdma1: dma-controller@58000000 {
1344 compatible = "st,stm32h7-mdma";
1345 reg = <0x58000000 0x1000>;
1346 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1347 clocks = <&rcc MDMA>;
1348 resets = <&rcc MDMA_R>;
1350 dma-channels = <32>;
1351 dma-requests = <48>;
1354 fmc: memory-controller@58002000 {
1355 #address-cells = <2>;
1357 compatible = "st,stm32mp1-fmc2-ebi";
1358 reg = <0x58002000 0x1000>;
1359 clocks = <&rcc FMC_K>;
1360 resets = <&rcc FMC_R>;
1361 status = "disabled";
1363 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1364 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1365 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1366 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1367 <4 0 0x80000000 0x10000000>; /* NAND */
1369 nand-controller@4,0 {
1370 #address-cells = <1>;
1372 compatible = "st,stm32mp1-fmc2-nfc";
1373 reg = <4 0x00000000 0x1000>,
1374 <4 0x08010000 0x1000>,
1375 <4 0x08020000 0x1000>,
1376 <4 0x01000000 0x1000>,
1377 <4 0x09010000 0x1000>,
1378 <4 0x09020000 0x1000>;
1379 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1380 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1381 <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1382 <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1383 dma-names = "tx", "rx", "ecc";
1384 status = "disabled";
1388 qspi: spi@58003000 {
1389 compatible = "st,stm32f469-qspi";
1390 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1391 reg-names = "qspi", "qspi_mm";
1392 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1393 dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1394 <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1395 dma-names = "tx", "rx";
1396 clocks = <&rcc QSPI_K>;
1397 resets = <&rcc QSPI_R>;
1398 #address-cells = <1>;
1400 status = "disabled";
1403 sdmmc1: mmc@58005000 {
1404 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1405 arm,primecell-periphid = <0x00253180>;
1406 reg = <0x58005000 0x1000>;
1407 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1408 interrupt-names = "cmd_irq";
1409 clocks = <&rcc SDMMC1_K>;
1410 clock-names = "apb_pclk";
1411 resets = <&rcc SDMMC1_R>;
1414 max-frequency = <120000000>;
1415 status = "disabled";
1418 sdmmc2: mmc@58007000 {
1419 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1420 arm,primecell-periphid = <0x00253180>;
1421 reg = <0x58007000 0x1000>;
1422 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1423 interrupt-names = "cmd_irq";
1424 clocks = <&rcc SDMMC2_K>;
1425 clock-names = "apb_pclk";
1426 resets = <&rcc SDMMC2_R>;
1429 max-frequency = <120000000>;
1430 status = "disabled";
1433 crc1: crc@58009000 {
1434 compatible = "st,stm32f7-crc";
1435 reg = <0x58009000 0x400>;
1436 clocks = <&rcc CRC1>;
1437 status = "disabled";
1440 ethernet0: ethernet@5800a000 {
1441 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1442 reg = <0x5800a000 0x2000>;
1443 reg-names = "stmmaceth";
1444 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1445 interrupt-names = "macirq";
1446 clock-names = "stmmaceth",
1452 clocks = <&rcc ETHMAC>,
1458 st,syscon = <&syscfg 0x4>;
1461 snps,en-tx-lpi-clockgating;
1462 snps,axi-config = <&stmmac_axi_config_0>;
1464 status = "disabled";
1466 stmmac_axi_config_0: stmmac-axi-config {
1467 snps,wr_osr_lmt = <0x7>;
1468 snps,rd_osr_lmt = <0x7>;
1469 snps,blen = <0 0 0 0 16 8 4>;
1473 usbh_ohci: usb@5800c000 {
1474 compatible = "generic-ohci";
1475 reg = <0x5800c000 0x1000>;
1476 clocks = <&usbphyc>, <&rcc USBH>;
1477 resets = <&rcc USBH_R>;
1478 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1479 status = "disabled";
1482 usbh_ehci: usb@5800d000 {
1483 compatible = "generic-ehci";
1484 reg = <0x5800d000 0x1000>;
1485 clocks = <&usbphyc>, <&rcc USBH>;
1486 resets = <&rcc USBH_R>;
1487 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1488 companion = <&usbh_ohci>;
1489 status = "disabled";
1492 ltdc: display-controller@5a001000 {
1493 compatible = "st,stm32-ltdc";
1494 reg = <0x5a001000 0x400>;
1495 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1497 clocks = <&rcc LTDC_PX>;
1498 clock-names = "lcd";
1499 resets = <&rcc LTDC_R>;
1500 status = "disabled";
1503 #address-cells = <1>;
1508 iwdg2: watchdog@5a002000 {
1509 compatible = "st,stm32mp1-iwdg";
1510 reg = <0x5a002000 0x400>;
1511 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1512 clock-names = "pclk", "lsi";
1513 status = "disabled";
1516 usbphyc: usbphyc@5a006000 {
1517 #address-cells = <1>;
1520 compatible = "st,stm32mp1-usbphyc";
1521 reg = <0x5a006000 0x1000>;
1522 clocks = <&rcc USBPHY_K>;
1523 resets = <&rcc USBPHY_R>;
1524 vdda1v1-supply = <®11>;
1525 vdda1v8-supply = <®18>;
1526 status = "disabled";
1528 usbphyc_port0: usb-phy@0 {
1533 usbphyc_port1: usb-phy@1 {
1539 usart1: serial@5c000000 {
1540 compatible = "st,stm32h7-uart";
1541 reg = <0x5c000000 0x400>;
1542 interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1543 clocks = <&rcc USART1_K>;
1545 status = "disabled";
1548 spi6: spi@5c001000 {
1549 #address-cells = <1>;
1551 compatible = "st,stm32h7-spi";
1552 reg = <0x5c001000 0x400>;
1553 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1554 clocks = <&rcc SPI6_K>;
1555 resets = <&rcc SPI6_R>;
1556 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1557 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1558 dma-names = "rx", "tx";
1559 status = "disabled";
1562 i2c4: i2c@5c002000 {
1563 compatible = "st,stm32mp15-i2c";
1564 reg = <0x5c002000 0x400>;
1565 interrupt-names = "event", "error";
1566 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1567 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1568 clocks = <&rcc I2C4_K>;
1569 resets = <&rcc I2C4_R>;
1570 #address-cells = <1>;
1572 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1575 status = "disabled";
1579 compatible = "st,stm32mp1-rtc";
1580 reg = <0x5c004000 0x400>;
1581 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1582 clock-names = "pclk", "rtc_ck";
1583 interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1584 status = "disabled";
1587 bsec: efuse@5c005000 {
1588 compatible = "st,stm32mp15-bsec";
1589 reg = <0x5c005000 0x400>;
1590 #address-cells = <1>;
1600 i2c6: i2c@5c009000 {
1601 compatible = "st,stm32mp15-i2c";
1602 reg = <0x5c009000 0x400>;
1603 interrupt-names = "event", "error";
1604 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1605 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1606 clocks = <&rcc I2C6_K>;
1607 resets = <&rcc I2C6_R>;
1608 #address-cells = <1>;
1610 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1613 status = "disabled";
1616 tamp: tamp@5c00a000 {
1617 compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1618 reg = <0x5c00a000 0x400>;
1622 * Break node order to solve dependency probe issue between
1625 pinctrl: pinctrl@50002000 {
1626 #address-cells = <1>;
1628 compatible = "st,stm32mp157-pinctrl";
1629 ranges = <0 0x50002000 0xa400>;
1630 interrupt-parent = <&exti>;
1631 st,syscfg = <&exti 0x60 0xff>;
1634 gpioa: gpio@50002000 {
1637 interrupt-controller;
1638 #interrupt-cells = <2>;
1640 clocks = <&rcc GPIOA>;
1641 st,bank-name = "GPIOA";
1642 status = "disabled";
1645 gpiob: gpio@50003000 {
1648 interrupt-controller;
1649 #interrupt-cells = <2>;
1650 reg = <0x1000 0x400>;
1651 clocks = <&rcc GPIOB>;
1652 st,bank-name = "GPIOB";
1653 status = "disabled";
1656 gpioc: gpio@50004000 {
1659 interrupt-controller;
1660 #interrupt-cells = <2>;
1661 reg = <0x2000 0x400>;
1662 clocks = <&rcc GPIOC>;
1663 st,bank-name = "GPIOC";
1664 status = "disabled";
1667 gpiod: gpio@50005000 {
1670 interrupt-controller;
1671 #interrupt-cells = <2>;
1672 reg = <0x3000 0x400>;
1673 clocks = <&rcc GPIOD>;
1674 st,bank-name = "GPIOD";
1675 status = "disabled";
1678 gpioe: gpio@50006000 {
1681 interrupt-controller;
1682 #interrupt-cells = <2>;
1683 reg = <0x4000 0x400>;
1684 clocks = <&rcc GPIOE>;
1685 st,bank-name = "GPIOE";
1686 status = "disabled";
1689 gpiof: gpio@50007000 {
1692 interrupt-controller;
1693 #interrupt-cells = <2>;
1694 reg = <0x5000 0x400>;
1695 clocks = <&rcc GPIOF>;
1696 st,bank-name = "GPIOF";
1697 status = "disabled";
1700 gpiog: gpio@50008000 {
1703 interrupt-controller;
1704 #interrupt-cells = <2>;
1705 reg = <0x6000 0x400>;
1706 clocks = <&rcc GPIOG>;
1707 st,bank-name = "GPIOG";
1708 status = "disabled";
1711 gpioh: gpio@50009000 {
1714 interrupt-controller;
1715 #interrupt-cells = <2>;
1716 reg = <0x7000 0x400>;
1717 clocks = <&rcc GPIOH>;
1718 st,bank-name = "GPIOH";
1719 status = "disabled";
1722 gpioi: gpio@5000a000 {
1725 interrupt-controller;
1726 #interrupt-cells = <2>;
1727 reg = <0x8000 0x400>;
1728 clocks = <&rcc GPIOI>;
1729 st,bank-name = "GPIOI";
1730 status = "disabled";
1733 gpioj: gpio@5000b000 {
1736 interrupt-controller;
1737 #interrupt-cells = <2>;
1738 reg = <0x9000 0x400>;
1739 clocks = <&rcc GPIOJ>;
1740 st,bank-name = "GPIOJ";
1741 status = "disabled";
1744 gpiok: gpio@5000c000 {
1747 interrupt-controller;
1748 #interrupt-cells = <2>;
1749 reg = <0xa000 0x400>;
1750 clocks = <&rcc GPIOK>;
1751 st,bank-name = "GPIOK";
1752 status = "disabled";
1756 pinctrl_z: pinctrl@54004000 {
1757 #address-cells = <1>;
1759 compatible = "st,stm32mp157-z-pinctrl";
1760 ranges = <0 0x54004000 0x400>;
1762 interrupt-parent = <&exti>;
1763 st,syscfg = <&exti 0x60 0xff>;
1765 gpioz: gpio@54004000 {
1768 interrupt-controller;
1769 #interrupt-cells = <2>;
1771 clocks = <&rcc GPIOZ>;
1772 st,bank-name = "GPIOZ";
1773 st,bank-ioport = <11>;
1774 status = "disabled";
1780 compatible = "st,mlahb", "simple-bus";
1781 #address-cells = <1>;
1784 dma-ranges = <0x00000000 0x38000000 0x10000>,
1785 <0x10000000 0x10000000 0x60000>,
1786 <0x30000000 0x30000000 0x60000>;
1788 m4_rproc: m4@10000000 {
1789 compatible = "st,stm32mp1-m4";
1790 reg = <0x10000000 0x40000>,
1791 <0x30000000 0x40000>,
1792 <0x38000000 0x10000>;
1793 resets = <&rcc MCU_R>;
1794 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1795 st,syscfg-tz = <&rcc 0x000 0x1>;
1796 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1797 st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1798 st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1799 status = "disabled";