arch/arm/boot/dts/stm32mp151.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
   4  * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
   5  */
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/clock/stm32mp1-clks.h>
   8 #include <dt-bindings/reset/stm32mp1-resets.h>
   9
  10 / {
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13
  14         cpus {
  15                 #address-cells = <1>;
  16                 #size-cells = <0>;
  17
  18                 cpu0: cpu@0 {
  19                         compatible = "arm,cortex-a7";
  20                         clock-frequency = <650000000>;
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                 };
  24         };
  25
  26         arm-pmu {
  27                 compatible = "arm,cortex-a7-pmu";
  28                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
  29                 interrupt-affinity = <&cpu0>;
  30                 interrupt-parent = <&intc>;
  31         };
  32
  33         psci {
  34                 compatible = "arm,psci-1.0";
  35                 method = "smc";
  36         };
  37
  38         intc: interrupt-controller@a0021000 {
  39                 compatible = "arm,cortex-a7-gic";
  40                 #interrupt-cells = <3>;
  41                 interrupt-controller;
  42                 reg = <0xa0021000 0x1000>,
  43                       <0xa0022000 0x2000>;
  44         };
  45
  46         timer {
  47                 compatible = "arm,armv7-timer";
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
  51                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
  52                 interrupt-parent = <&intc>;
  53         };
  54
  55         clocks {
  56                 clk_hse: clk-hse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <24000000>;
  60                 };
  61
  62                 clk_hsi: clk-hsi {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <64000000>;
  66                 };
  67
  68                 clk_lse: clk-lse {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32768>;
  72                 };
  73
  74                 clk_lsi: clk-lsi {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <32000>;
  78                 };
  79
  80                 clk_csi: clk-csi {
  81                         #clock-cells = <0>;
  82                         compatible = "fixed-clock";
  83                         clock-frequency = <4000000>;
  84                 };
  85         };
  86
  87         thermal-zones {
  88                 cpu_thermal: cpu-thermal {
  89                         polling-delay-passive = <0>;
  90                         polling-delay = <0>;
  91                         thermal-sensors = <&dts>;
  92
  93                         trips {
  94                                 cpu_alert1: cpu-alert1 {
  95                                         temperature = <85000>;
  96                                         hysteresis = <0>;
  97                                         type = "passive";
  98                                 };
  99
 100                                 cpu-crit {
 101                                         temperature = <120000>;
 102                                         hysteresis = <0>;
 103                                         type = "critical";
 104                                 };
 105                         };
 106
 107                         cooling-maps {
 108                         };
 109                 };
 110         };
 111
 112         booster: regulator-booster {
 113                 compatible = "st,stm32mp1-booster";
 114                 st,syscfg = <&syscfg>;
 115                 status = "disabled";
 116         };
 117
 118         firmware {
 119                 optee: optee {
 120                         compatible = "linaro,optee-tz";
 121                         method = "smc";
 122                         status = "disabled";
 123                 };
 124
 125                 scmi: scmi {
 126                         compatible = "linaro,scmi-optee";
 127                         #address-cells = <1>;
 128                         #size-cells = <0>;
 129                         linaro,optee-channel-id = <0>;
 130                         shmem = <&scmi_shm>;
 131                         status = "disabled";
 132
 133                         scmi_clk: protocol@14 {
 134                                 reg = <0x14>;
 135                                 #clock-cells = <1>;
 136                         };
 137
 138                         scmi_reset: protocol@16 {
 139                                 reg = <0x16>;
 140                                 #reset-cells = <1>;
 141                         };
 142                 };
 143         };
 144
 145         soc {
 146                 compatible = "simple-bus";
 147                 #address-cells = <1>;
 148                 #size-cells = <1>;
 149                 interrupt-parent = <&intc>;
 150                 ranges;
 151
 152                 scmi_sram: sram@2ffff000 {
 153                         compatible = "mmio-sram";
 154                         reg = <0x2ffff000 0x1000>;
 155                         #address-cells = <1>;
 156                         #size-cells = <1>;
 157                         ranges = <0 0x2ffff000 0x1000>;
 158
 159                         scmi_shm: scmi-sram@0 {
 160                                 compatible = "arm,scmi-shmem";
 161                                 reg = <0 0x80>;
 162                                 status = "disabled";
 163                         };
 164                 };
 165
 166                 timers2: timer@40000000 {
 167                         #address-cells = <1>;
 168                         #size-cells = <0>;
 169                         compatible = "st,stm32-timers";
 170                         reg = <0x40000000 0x400>;
 171                         clocks = <&rcc TIM2_K>;
 172                         clock-names = "int";
 173                         dmas = <&dmamux1 18 0x400 0x1>,
 174                                <&dmamux1 19 0x400 0x1>,
 175                                <&dmamux1 20 0x400 0x1>,
 176                                <&dmamux1 21 0x400 0x1>,
 177                                <&dmamux1 22 0x400 0x1>;
 178                         dma-names = "ch1", "ch2", "ch3", "ch4", "up";
 179                         status = "disabled";
 180
 181                         pwm {
 182                                 compatible = "st,stm32-pwm";
 183                                 #pwm-cells = <3>;
 184                                 status = "disabled";
 185                         };
 186
 187                         timer@1 {
 188                                 compatible = "st,stm32h7-timer-trigger";
 189                                 reg = <1>;
 190                                 status = "disabled";
 191                         };
 192
 193                         counter {
 194                                 compatible = "st,stm32-timer-counter";
 195                                 status = "disabled";
 196                         };
 197                 };
 198
 199                 timers3: timer@40001000 {
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         compatible = "st,stm32-timers";
 203                         reg = <0x40001000 0x400>;
 204                         clocks = <&rcc TIM3_K>;
 205                         clock-names = "int";
 206                         dmas = <&dmamux1 23 0x400 0x1>,
 207                                <&dmamux1 24 0x400 0x1>,
 208                                <&dmamux1 25 0x400 0x1>,
 209                                <&dmamux1 26 0x400 0x1>,
 210                                <&dmamux1 27 0x400 0x1>,
 211                                <&dmamux1 28 0x400 0x1>;
 212                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 213                         status = "disabled";
 214
 215                         pwm {
 216                                 compatible = "st,stm32-pwm";
 217                                 #pwm-cells = <3>;
 218                                 status = "disabled";
 219                         };
 220
 221                         timer@2 {
 222                                 compatible = "st,stm32h7-timer-trigger";
 223                                 reg = <2>;
 224                                 status = "disabled";
 225                         };
 226
 227                         counter {
 228                                 compatible = "st,stm32-timer-counter";
 229                                 status = "disabled";
 230                         };
 231                 };
 232
 233                 timers4: timer@40002000 {
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236                         compatible = "st,stm32-timers";
 237                         reg = <0x40002000 0x400>;
 238                         clocks = <&rcc TIM4_K>;
 239                         clock-names = "int";
 240                         dmas = <&dmamux1 29 0x400 0x1>,
 241                                <&dmamux1 30 0x400 0x1>,
 242                                <&dmamux1 31 0x400 0x1>,
 243                                <&dmamux1 32 0x400 0x1>;
 244                         dma-names = "ch1", "ch2", "ch3", "ch4";
 245                         status = "disabled";
 246
 247                         pwm {
 248                                 compatible = "st,stm32-pwm";
 249                                 #pwm-cells = <3>;
 250                                 status = "disabled";
 251                         };
 252
 253                         timer@3 {
 254                                 compatible = "st,stm32h7-timer-trigger";
 255                                 reg = <3>;
 256                                 status = "disabled";
 257                         };
 258
 259                         counter {
 260                                 compatible = "st,stm32-timer-counter";
 261                                 status = "disabled";
 262                         };
 263                 };
 264
 265                 timers5: timer@40003000 {
 266                         #address-cells = <1>;
 267                         #size-cells = <0>;
 268                         compatible = "st,stm32-timers";
 269                         reg = <0x40003000 0x400>;
 270                         clocks = <&rcc TIM5_K>;
 271                         clock-names = "int";
 272                         dmas = <&dmamux1 55 0x400 0x1>,
 273                                <&dmamux1 56 0x400 0x1>,
 274                                <&dmamux1 57 0x400 0x1>,
 275                                <&dmamux1 58 0x400 0x1>,
 276                                <&dmamux1 59 0x400 0x1>,
 277                                <&dmamux1 60 0x400 0x1>;
 278                         dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
 279                         status = "disabled";
 280
 281                         pwm {
 282                                 compatible = "st,stm32-pwm";
 283                                 #pwm-cells = <3>;
 284                                 status = "disabled";
 285                         };
 286
 287                         timer@4 {
 288                                 compatible = "st,stm32h7-timer-trigger";
 289                                 reg = <4>;
 290                                 status = "disabled";
 291                         };
 292
 293                         counter {
 294                                 compatible = "st,stm32-timer-counter";
 295                                 status = "disabled";
 296                         };
 297                 };
 298
 299                 timers6: timer@40004000 {
 300                         #address-cells = <1>;
 301                         #size-cells = <0>;
 302                         compatible = "st,stm32-timers";
 303                         reg = <0x40004000 0x400>;
 304                         clocks = <&rcc TIM6_K>;
 305                         clock-names = "int";
 306                         dmas = <&dmamux1 69 0x400 0x1>;
 307                         dma-names = "up";
 308                         status = "disabled";
 309
 310                         timer@5 {
 311                                 compatible = "st,stm32h7-timer-trigger";
 312                                 reg = <5>;
 313                                 status = "disabled";
 314                         };
 315                 };
 316
 317                 timers7: timer@40005000 {
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                         compatible = "st,stm32-timers";
 321                         reg = <0x40005000 0x400>;
 322                         clocks = <&rcc TIM7_K>;
 323                         clock-names = "int";
 324                         dmas = <&dmamux1 70 0x400 0x1>;
 325                         dma-names = "up";
 326                         status = "disabled";
 327
 328                         timer@6 {
 329                                 compatible = "st,stm32h7-timer-trigger";
 330                                 reg = <6>;
 331                                 status = "disabled";
 332                         };
 333                 };
 334
 335                 timers12: timer@40006000 {
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338                         compatible = "st,stm32-timers";
 339                         reg = <0x40006000 0x400>;
 340                         clocks = <&rcc TIM12_K>;
 341                         clock-names = "int";
 342                         status = "disabled";
 343
 344                         pwm {
 345                                 compatible = "st,stm32-pwm";
 346                                 #pwm-cells = <3>;
 347                                 status = "disabled";
 348                         };
 349
 350                         timer@11 {
 351                                 compatible = "st,stm32h7-timer-trigger";
 352                                 reg = <11>;
 353                                 status = "disabled";
 354                         };
 355                 };
 356
 357                 timers13: timer@40007000 {
 358                         #address-cells = <1>;
 359                         #size-cells = <0>;
 360                         compatible = "st,stm32-timers";
 361                         reg = <0x40007000 0x400>;
 362                         clocks = <&rcc TIM13_K>;
 363                         clock-names = "int";
 364                         status = "disabled";
 365
 366                         pwm {
 367                                 compatible = "st,stm32-pwm";
 368                                 #pwm-cells = <3>;
 369                                 status = "disabled";
 370                         };
 371
 372                         timer@12 {
 373                                 compatible = "st,stm32h7-timer-trigger";
 374                                 reg = <12>;
 375                                 status = "disabled";
 376                         };
 377                 };
 378
 379                 timers14: timer@40008000 {
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         compatible = "st,stm32-timers";
 383                         reg = <0x40008000 0x400>;
 384                         clocks = <&rcc TIM14_K>;
 385                         clock-names = "int";
 386                         status = "disabled";
 387
 388                         pwm {
 389                                 compatible = "st,stm32-pwm";
 390                                 #pwm-cells = <3>;
 391                                 status = "disabled";
 392                         };
 393
 394                         timer@13 {
 395                                 compatible = "st,stm32h7-timer-trigger";
 396                                 reg = <13>;
 397                                 status = "disabled";
 398                         };
 399                 };
 400
 401                 lptimer1: timer@40009000 {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404                         compatible = "st,stm32-lptimer";
 405                         reg = <0x40009000 0x400>;
 406                         interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
 407                         clocks = <&rcc LPTIM1_K>;
 408                         clock-names = "mux";
 409                         wakeup-source;
 410                         status = "disabled";
 411
 412                         pwm {
 413                                 compatible = "st,stm32-pwm-lp";
 414                                 #pwm-cells = <3>;
 415                                 status = "disabled";
 416                         };
 417
 418                         trigger@0 {
 419                                 compatible = "st,stm32-lptimer-trigger";
 420                                 reg = <0>;
 421                                 status = "disabled";
 422                         };
 423
 424                         counter {
 425                                 compatible = "st,stm32-lptimer-counter";
 426                                 status = "disabled";
 427                         };
 428                 };
 429
 430                 spi2: spi@4000b000 {
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         compatible = "st,stm32h7-spi";
 434                         reg = <0x4000b000 0x400>;
 435                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&rcc SPI2_K>;
 437                         resets = <&rcc SPI2_R>;
 438                         dmas = <&dmamux1 39 0x400 0x05>,
 439                                <&dmamux1 40 0x400 0x05>;
 440                         dma-names = "rx", "tx";
 441                         status = "disabled";
 442                 };
 443
 444                 i2s2: audio-controller@4000b000 {
 445                         compatible = "st,stm32h7-i2s";
 446                         #sound-dai-cells = <0>;
 447                         reg = <0x4000b000 0x400>;
 448                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 449                         dmas = <&dmamux1 39 0x400 0x01>,
 450                                <&dmamux1 40 0x400 0x01>;
 451                         dma-names = "rx", "tx";
 452                         status = "disabled";
 453                 };
 454
 455                 spi3: spi@4000c000 {
 456                         #address-cells = <1>;
 457                         #size-cells = <0>;
 458                         compatible = "st,stm32h7-spi";
 459                         reg = <0x4000c000 0x400>;
 460                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 461                         clocks = <&rcc SPI3_K>;
 462                         resets = <&rcc SPI3_R>;
 463                         dmas = <&dmamux1 61 0x400 0x05>,
 464                                <&dmamux1 62 0x400 0x05>;
 465                         dma-names = "rx", "tx";
 466                         status = "disabled";
 467                 };
 468
 469                 i2s3: audio-controller@4000c000 {
 470                         compatible = "st,stm32h7-i2s";
 471                         #sound-dai-cells = <0>;
 472                         reg = <0x4000c000 0x400>;
 473                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 474                         dmas = <&dmamux1 61 0x400 0x01>,
 475                                <&dmamux1 62 0x400 0x01>;
 476                         dma-names = "rx", "tx";
 477                         status = "disabled";
 478                 };
 479
 480                 spdifrx: audio-controller@4000d000 {
 481                         compatible = "st,stm32h7-spdifrx";
 482                         #sound-dai-cells = <0>;
 483                         reg = <0x4000d000 0x400>;
 484                         clocks = <&rcc SPDIF_K>;
 485                         clock-names = "kclk";
 486                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 487                         dmas = <&dmamux1 93 0x400 0x01>,
 488                                <&dmamux1 94 0x400 0x01>;
 489                         dma-names = "rx", "rx-ctrl";
 490                         status = "disabled";
 491                 };
 492
 493                 usart2: serial@4000e000 {
 494                         compatible = "st,stm32h7-uart";
 495                         reg = <0x4000e000 0x400>;
 496                         interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&rcc USART2_K>;
 498                         wakeup-source;
 499                         dmas = <&dmamux1 43 0x400 0x15>,
 500                                <&dmamux1 44 0x400 0x11>;
 501                         dma-names = "rx", "tx";
 502                         status = "disabled";
 503                 };
 504
 505                 usart3: serial@4000f000 {
 506                         compatible = "st,stm32h7-uart";
 507                         reg = <0x4000f000 0x400>;
 508                         interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
 509                         clocks = <&rcc USART3_K>;
 510                         wakeup-source;
 511                         dmas = <&dmamux1 45 0x400 0x15>,
 512                                <&dmamux1 46 0x400 0x11>;
 513                         dma-names = "rx", "tx";
 514                         status = "disabled";
 515                 };
 516
 517                 uart4: serial@40010000 {
 518                         compatible = "st,stm32h7-uart";
 519                         reg = <0x40010000 0x400>;
 520                         interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
 521                         clocks = <&rcc UART4_K>;
 522                         wakeup-source;
 523                         dmas = <&dmamux1 63 0x400 0x15>,
 524                                <&dmamux1 64 0x400 0x11>;
 525                         dma-names = "rx", "tx";
 526                         status = "disabled";
 527                 };
 528
 529                 uart5: serial@40011000 {
 530                         compatible = "st,stm32h7-uart";
 531                         reg = <0x40011000 0x400>;
 532                         interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
 533                         clocks = <&rcc UART5_K>;
 534                         wakeup-source;
 535                         dmas = <&dmamux1 65 0x400 0x15>,
 536                                <&dmamux1 66 0x400 0x11>;
 537                         dma-names = "rx", "tx";
 538                         status = "disabled";
 539                 };
 540
 541                 i2c1: i2c@40012000 {
 542                         compatible = "st,stm32mp15-i2c";
 543                         reg = <0x40012000 0x400>;
 544                         interrupt-names = "event", "error";
 545                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 546                                      <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&rcc I2C1_K>;
 548                         resets = <&rcc I2C1_R>;
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551                         st,syscfg-fmp = <&syscfg 0x4 0x1>;
 552                         wakeup-source;
 553                         i2c-analog-filter;
 554                         status = "disabled";
 555                 };
 556
 557                 i2c2: i2c@40013000 {
 558                         compatible = "st,stm32mp15-i2c";
 559                         reg = <0x40013000 0x400>;
 560                         interrupt-names = "event", "error";
 561                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
 562                                      <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 563                         clocks = <&rcc I2C2_K>;
 564                         resets = <&rcc I2C2_R>;
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         st,syscfg-fmp = <&syscfg 0x4 0x2>;
 568                         wakeup-source;
 569                         i2c-analog-filter;
 570                         status = "disabled";
 571                 };
 572
 573                 i2c3: i2c@40014000 {
 574                         compatible = "st,stm32mp15-i2c";
 575                         reg = <0x40014000 0x400>;
 576                         interrupt-names = "event", "error";
 577                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 578                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 579                         clocks = <&rcc I2C3_K>;
 580                         resets = <&rcc I2C3_R>;
 581                         #address-cells = <1>;
 582                         #size-cells = <0>;
 583                         st,syscfg-fmp = <&syscfg 0x4 0x4>;
 584                         wakeup-source;
 585                         i2c-analog-filter;
 586                         status = "disabled";
 587                 };
 588
 589                 i2c5: i2c@40015000 {
 590                         compatible = "st,stm32mp15-i2c";
 591                         reg = <0x40015000 0x400>;
 592                         interrupt-names = "event", "error";
 593                         interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 595                         clocks = <&rcc I2C5_K>;
 596                         resets = <&rcc I2C5_R>;
 597                         #address-cells = <1>;
 598                         #size-cells = <0>;
 599                         st,syscfg-fmp = <&syscfg 0x4 0x10>;
 600                         wakeup-source;
 601                         i2c-analog-filter;
 602                         status = "disabled";
 603                 };
 604
 605                 cec: cec@40016000 {
 606                         compatible = "st,stm32-cec";
 607                         reg = <0x40016000 0x400>;
 608                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 609                         clocks = <&rcc CEC_K>, <&clk_lse>;
 610                         clock-names = "cec", "hdmi-cec";
 611                         status = "disabled";
 612                 };
 613
 614                 dac: dac@40017000 {
 615                         compatible = "st,stm32h7-dac-core";
 616                         reg = <0x40017000 0x400>;
 617                         clocks = <&rcc DAC12>;
 618                         clock-names = "pclk";
 619                         #address-cells = <1>;
 620                         #size-cells = <0>;
 621                         status = "disabled";
 622
 623                         dac1: dac@1 {
 624                                 compatible = "st,stm32-dac";
 625                                 #io-channel-cells = <1>;
 626                                 reg = <1>;
 627                                 status = "disabled";
 628                         };
 629
 630                         dac2: dac@2 {
 631                                 compatible = "st,stm32-dac";
 632                                 #io-channel-cells = <1>;
 633                                 reg = <2>;
 634                                 status = "disabled";
 635                         };
 636                 };
 637
 638                 uart7: serial@40018000 {
 639                         compatible = "st,stm32h7-uart";
 640                         reg = <0x40018000 0x400>;
 641                         interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
 642                         clocks = <&rcc UART7_K>;
 643                         wakeup-source;
 644                         dmas = <&dmamux1 79 0x400 0x15>,
 645                                <&dmamux1 80 0x400 0x11>;
 646                         dma-names = "rx", "tx";
 647                         status = "disabled";
 648                 };
 649
 650                 uart8: serial@40019000 {
 651                         compatible = "st,stm32h7-uart";
 652                         reg = <0x40019000 0x400>;
 653                         interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
 654                         clocks = <&rcc UART8_K>;
 655                         wakeup-source;
 656                         dmas = <&dmamux1 81 0x400 0x15>,
 657                                <&dmamux1 82 0x400 0x11>;
 658                         dma-names = "rx", "tx";
 659                         status = "disabled";
 660                 };
 661
 662                 timers1: timer@44000000 {
 663                         #address-cells = <1>;
 664                         #size-cells = <0>;
 665                         compatible = "st,stm32-timers";
 666                         reg = <0x44000000 0x400>;
 667                         clocks = <&rcc TIM1_K>;
 668                         clock-names = "int";
 669                         dmas = <&dmamux1 11 0x400 0x1>,
 670                                <&dmamux1 12 0x400 0x1>,
 671                                <&dmamux1 13 0x400 0x1>,
 672                                <&dmamux1 14 0x400 0x1>,
 673                                <&dmamux1 15 0x400 0x1>,
 674                                <&dmamux1 16 0x400 0x1>,
 675                                <&dmamux1 17 0x400 0x1>;
 676                         dma-names = "ch1", "ch2", "ch3", "ch4",
 677                                     "up", "trig", "com";
 678                         status = "disabled";
 679
 680                         pwm {
 681                                 compatible = "st,stm32-pwm";
 682                                 #pwm-cells = <3>;
 683                                 status = "disabled";
 684                         };
 685
 686                         timer@0 {
 687                                 compatible = "st,stm32h7-timer-trigger";
 688                                 reg = <0>;
 689                                 status = "disabled";
 690                         };
 691
 692                         counter {
 693                                 compatible = "st,stm32-timer-counter";
 694                                 status = "disabled";
 695                         };
 696                 };
 697
 698                 timers8: timer@44001000 {
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                         compatible = "st,stm32-timers";
 702                         reg = <0x44001000 0x400>;
 703                         clocks = <&rcc TIM8_K>;
 704                         clock-names = "int";
 705                         dmas = <&dmamux1 47 0x400 0x1>,
 706                                <&dmamux1 48 0x400 0x1>,
 707                                <&dmamux1 49 0x400 0x1>,
 708                                <&dmamux1 50 0x400 0x1>,
 709                                <&dmamux1 51 0x400 0x1>,
 710                                <&dmamux1 52 0x400 0x1>,
 711                                <&dmamux1 53 0x400 0x1>;
 712                         dma-names = "ch1", "ch2", "ch3", "ch4",
 713                                     "up", "trig", "com";
 714                         status = "disabled";
 715
 716                         pwm {
 717                                 compatible = "st,stm32-pwm";
 718                                 #pwm-cells = <3>;
 719                                 status = "disabled";
 720                         };
 721
 722                         timer@7 {
 723                                 compatible = "st,stm32h7-timer-trigger";
 724                                 reg = <7>;
 725                                 status = "disabled";
 726                         };
 727
 728                         counter {
 729                                 compatible = "st,stm32-timer-counter";
 730                                 status = "disabled";
 731                         };
 732                 };
 733
 734                 usart6: serial@44003000 {
 735                         compatible = "st,stm32h7-uart";
 736                         reg = <0x44003000 0x400>;
 737                         interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
 738                         clocks = <&rcc USART6_K>;
 739                         wakeup-source;
 740                         dmas = <&dmamux1 71 0x400 0x15>,
 741                                <&dmamux1 72 0x400 0x11>;
 742                         dma-names = "rx", "tx";
 743                         status = "disabled";
 744                 };
 745
 746                 spi1: spi@44004000 {
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749                         compatible = "st,stm32h7-spi";
 750                         reg = <0x44004000 0x400>;
 751                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 752                         clocks = <&rcc SPI1_K>;
 753                         resets = <&rcc SPI1_R>;
 754                         dmas = <&dmamux1 37 0x400 0x05>,
 755                                <&dmamux1 38 0x400 0x05>;
 756                         dma-names = "rx", "tx";
 757                         status = "disabled";
 758                 };
 759
 760                 i2s1: audio-controller@44004000 {
 761                         compatible = "st,stm32h7-i2s";
 762                         #sound-dai-cells = <0>;
 763                         reg = <0x44004000 0x400>;
 764                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 765                         dmas = <&dmamux1 37 0x400 0x01>,
 766                                <&dmamux1 38 0x400 0x01>;
 767                         dma-names = "rx", "tx";
 768                         status = "disabled";
 769                 };
 770
 771                 spi4: spi@44005000 {
 772                         #address-cells = <1>;
 773                         #size-cells = <0>;
 774                         compatible = "st,stm32h7-spi";
 775                         reg = <0x44005000 0x400>;
 776                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 777                         clocks = <&rcc SPI4_K>;
 778                         resets = <&rcc SPI4_R>;
 779                         dmas = <&dmamux1 83 0x400 0x05>,
 780                                <&dmamux1 84 0x400 0x05>;
 781                         dma-names = "rx", "tx";
 782                         status = "disabled";
 783                 };
 784
 785                 timers15: timer@44006000 {
 786                         #address-cells = <1>;
 787                         #size-cells = <0>;
 788                         compatible = "st,stm32-timers";
 789                         reg = <0x44006000 0x400>;
 790                         clocks = <&rcc TIM15_K>;
 791                         clock-names = "int";
 792                         dmas = <&dmamux1 105 0x400 0x1>,
 793                                <&dmamux1 106 0x400 0x1>,
 794                                <&dmamux1 107 0x400 0x1>,
 795                                <&dmamux1 108 0x400 0x1>;
 796                         dma-names = "ch1", "up", "trig", "com";
 797                         status = "disabled";
 798
 799                         pwm {
 800                                 compatible = "st,stm32-pwm";
 801                                 #pwm-cells = <3>;
 802                                 status = "disabled";
 803                         };
 804
 805                         timer@14 {
 806                                 compatible = "st,stm32h7-timer-trigger";
 807                                 reg = <14>;
 808                                 status = "disabled";
 809                         };
 810                 };
 811
 812                 timers16: timer@44007000 {
 813                         #address-cells = <1>;
 814                         #size-cells = <0>;
 815                         compatible = "st,stm32-timers";
 816                         reg = <0x44007000 0x400>;
 817                         clocks = <&rcc TIM16_K>;
 818                         clock-names = "int";
 819                         dmas = <&dmamux1 109 0x400 0x1>,
 820                                <&dmamux1 110 0x400 0x1>;
 821                         dma-names = "ch1", "up";
 822                         status = "disabled";
 823
 824                         pwm {
 825                                 compatible = "st,stm32-pwm";
 826                                 #pwm-cells = <3>;
 827                                 status = "disabled";
 828                         };
 829                         timer@15 {
 830                                 compatible = "st,stm32h7-timer-trigger";
 831                                 reg = <15>;
 832                                 status = "disabled";
 833                         };
 834                 };
 835
 836                 timers17: timer@44008000 {
 837                         #address-cells = <1>;
 838                         #size-cells = <0>;
 839                         compatible = "st,stm32-timers";
 840                         reg = <0x44008000 0x400>;
 841                         clocks = <&rcc TIM17_K>;
 842                         clock-names = "int";
 843                         dmas = <&dmamux1 111 0x400 0x1>,
 844                                <&dmamux1 112 0x400 0x1>;
 845                         dma-names = "ch1", "up";
 846                         status = "disabled";
 847
 848                         pwm {
 849                                 compatible = "st,stm32-pwm";
 850                                 #pwm-cells = <3>;
 851                                 status = "disabled";
 852                         };
 853
 854                         timer@16 {
 855                                 compatible = "st,stm32h7-timer-trigger";
 856                                 reg = <16>;
 857                                 status = "disabled";
 858                         };
 859                 };
 860
 861                 spi5: spi@44009000 {
 862                         #address-cells = <1>;
 863                         #size-cells = <0>;
 864                         compatible = "st,stm32h7-spi";
 865                         reg = <0x44009000 0x400>;
 866                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 867                         clocks = <&rcc SPI5_K>;
 868                         resets = <&rcc SPI5_R>;
 869                         dmas = <&dmamux1 85 0x400 0x05>,
 870                                <&dmamux1 86 0x400 0x05>;
 871                         dma-names = "rx", "tx";
 872                         status = "disabled";
 873                 };
 874
 875                 sai1: sai@4400a000 {
 876                         compatible = "st,stm32h7-sai";
 877                         #address-cells = <1>;
 878                         #size-cells = <1>;
 879                         ranges = <0 0x4400a000 0x400>;
 880                         reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
 881                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 882                         resets = <&rcc SAI1_R>;
 883                         status = "disabled";
 884
 885                         sai1a: audio-controller@4400a004 {
 886                                 #sound-dai-cells = <0>;
 887
 888                                 compatible = "st,stm32-sai-sub-a";
 889                                 reg = <0x4 0x20>;
 890                                 clocks = <&rcc SAI1_K>;
 891                                 clock-names = "sai_ck";
 892                                 dmas = <&dmamux1 87 0x400 0x01>;
 893                                 status = "disabled";
 894                         };
 895
 896                         sai1b: audio-controller@4400a024 {
 897                                 #sound-dai-cells = <0>;
 898                                 compatible = "st,stm32-sai-sub-b";
 899                                 reg = <0x24 0x20>;
 900                                 clocks = <&rcc SAI1_K>;
 901                                 clock-names = "sai_ck";
 902                                 dmas = <&dmamux1 88 0x400 0x01>;
 903                                 status = "disabled";
 904                         };
 905                 };
 906
 907                 sai2: sai@4400b000 {
 908                         compatible = "st,stm32h7-sai";
 909                         #address-cells = <1>;
 910                         #size-cells = <1>;
 911                         ranges = <0 0x4400b000 0x400>;
 912                         reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
 913                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 914                         resets = <&rcc SAI2_R>;
 915                         status = "disabled";
 916
 917                         sai2a: audio-controller@4400b004 {
 918                                 #sound-dai-cells = <0>;
 919                                 compatible = "st,stm32-sai-sub-a";
 920                                 reg = <0x4 0x20>;
 921                                 clocks = <&rcc SAI2_K>;
 922                                 clock-names = "sai_ck";
 923                                 dmas = <&dmamux1 89 0x400 0x01>;
 924                                 status = "disabled";
 925                         };
 926
 927                         sai2b: audio-controller@4400b024 {
 928                                 #sound-dai-cells = <0>;
 929                                 compatible = "st,stm32-sai-sub-b";
 930                                 reg = <0x24 0x20>;
 931                                 clocks = <&rcc SAI2_K>;
 932                                 clock-names = "sai_ck";
 933                                 dmas = <&dmamux1 90 0x400 0x01>;
 934                                 status = "disabled";
 935                         };
 936                 };
 937
 938                 sai3: sai@4400c000 {
 939                         compatible = "st,stm32h7-sai";
 940                         #address-cells = <1>;
 941                         #size-cells = <1>;
 942                         ranges = <0 0x4400c000 0x400>;
 943                         reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
 944                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 945                         resets = <&rcc SAI3_R>;
 946                         status = "disabled";
 947
 948                         sai3a: audio-controller@4400c004 {
 949                                 #sound-dai-cells = <0>;
 950                                 compatible = "st,stm32-sai-sub-a";
 951                                 reg = <0x04 0x20>;
 952                                 clocks = <&rcc SAI3_K>;
 953                                 clock-names = "sai_ck";
 954                                 dmas = <&dmamux1 113 0x400 0x01>;
 955                                 status = "disabled";
 956                         };
 957
 958                         sai3b: audio-controller@4400c024 {
 959                                 #sound-dai-cells = <0>;
 960                                 compatible = "st,stm32-sai-sub-b";
 961                                 reg = <0x24 0x20>;
 962                                 clocks = <&rcc SAI3_K>;
 963                                 clock-names = "sai_ck";
 964                                 dmas = <&dmamux1 114 0x400 0x01>;
 965                                 status = "disabled";
 966                         };
 967                 };
 968
 969                 dfsdm: dfsdm@4400d000 {
 970                         compatible = "st,stm32mp1-dfsdm";
 971                         reg = <0x4400d000 0x800>;
 972                         clocks = <&rcc DFSDM_K>;
 973                         clock-names = "dfsdm";
 974                         #address-cells = <1>;
 975                         #size-cells = <0>;
 976                         status = "disabled";
 977
 978                         dfsdm0: filter@0 {
 979                                 compatible = "st,stm32-dfsdm-adc";
 980                                 #io-channel-cells = <1>;
 981                                 reg = <0>;
 982                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 983                                 dmas = <&dmamux1 101 0x400 0x01>;
 984                                 dma-names = "rx";
 985                                 status = "disabled";
 986                         };
 987
 988                         dfsdm1: filter@1 {
 989                                 compatible = "st,stm32-dfsdm-adc";
 990                                 #io-channel-cells = <1>;
 991                                 reg = <1>;
 992                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 993                                 dmas = <&dmamux1 102 0x400 0x01>;
 994                                 dma-names = "rx";
 995                                 status = "disabled";
 996                         };
 997
 998                         dfsdm2: filter@2 {
 999                                 compatible = "st,stm32-dfsdm-adc";
1000                                 #io-channel-cells = <1>;
1001                                 reg = <2>;
1002                                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1003                                 dmas = <&dmamux1 103 0x400 0x01>;
1004                                 dma-names = "rx";
1005                                 status = "disabled";
1006                         };
1007
1008                         dfsdm3: filter@3 {
1009                                 compatible = "st,stm32-dfsdm-adc";
1010                                 #io-channel-cells = <1>;
1011                                 reg = <3>;
1012                                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
1013                                 dmas = <&dmamux1 104 0x400 0x01>;
1014                                 dma-names = "rx";
1015                                 status = "disabled";
1016                         };
1017
1018                         dfsdm4: filter@4 {
1019                                 compatible = "st,stm32-dfsdm-adc";
1020                                 #io-channel-cells = <1>;
1021                                 reg = <4>;
1022                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1023                                 dmas = <&dmamux1 91 0x400 0x01>;
1024                                 dma-names = "rx";
1025                                 status = "disabled";
1026                         };
1027
1028                         dfsdm5: filter@5 {
1029                                 compatible = "st,stm32-dfsdm-adc";
1030                                 #io-channel-cells = <1>;
1031                                 reg = <5>;
1032                                 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
1033                                 dmas = <&dmamux1 92 0x400 0x01>;
1034                                 dma-names = "rx";
1035                                 status = "disabled";
1036                         };
1037                 };
1038
1039                 dma1: dma-controller@48000000 {
1040                         compatible = "st,stm32-dma";
1041                         reg = <0x48000000 0x400>;
1042                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1043                                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1044                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1045                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1046                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1047                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1048                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
1049                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1050                         clocks = <&rcc DMA1>;
1051                         resets = <&rcc DMA1_R>;
1052                         #dma-cells = <4>;
1053                         st,mem2mem;
1054                         dma-requests = <8>;
1055                 };
1056
1057                 dma2: dma-controller@48001000 {
1058                         compatible = "st,stm32-dma";
1059                         reg = <0x48001000 0x400>;
1060                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1061                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1062                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1063                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
1064                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
1065                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1066                                      <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1067                                      <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1068                         clocks = <&rcc DMA2>;
1069                         resets = <&rcc DMA2_R>;
1070                         #dma-cells = <4>;
1071                         st,mem2mem;
1072                         dma-requests = <8>;
1073                 };
1074
1075                 dmamux1: dma-router@48002000 {
1076                         compatible = "st,stm32h7-dmamux";
1077                         reg = <0x48002000 0x40>;
1078                         #dma-cells = <3>;
1079                         dma-requests = <128>;
1080                         dma-masters = <&dma1 &dma2>;
1081                         dma-channels = <16>;
1082                         clocks = <&rcc DMAMUX>;
1083                         resets = <&rcc DMAMUX_R>;
1084                 };
1085
1086                 adc: adc@48003000 {
1087                         compatible = "st,stm32mp1-adc-core";
1088                         reg = <0x48003000 0x400>;
1089                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1090                                      <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1091                         clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1092                         clock-names = "bus", "adc";
1093                         interrupt-controller;
1094                         st,syscfg = <&syscfg>;
1095                         #interrupt-cells = <1>;
1096                         #address-cells = <1>;
1097                         #size-cells = <0>;
1098                         status = "disabled";
1099
1100                         adc1: adc@0 {
1101                                 compatible = "st,stm32mp1-adc";
1102                                 #io-channel-cells = <1>;
1103                                 reg = <0x0>;
1104                                 interrupt-parent = <&adc>;
1105                                 interrupts = <0>;
1106                                 dmas = <&dmamux1 9 0x400 0x01>;
1107                                 dma-names = "rx";
1108                                 status = "disabled";
1109                         };
1110
1111                         adc2: adc@100 {
1112                                 compatible = "st,stm32mp1-adc";
1113                                 #io-channel-cells = <1>;
1114                                 reg = <0x100>;
1115                                 interrupt-parent = <&adc>;
1116                                 interrupts = <1>;
1117                                 dmas = <&dmamux1 10 0x400 0x01>;
1118                                 dma-names = "rx";
1119                                 status = "disabled";
1120                         };
1121                 };
1122
1123                 sdmmc3: mmc@48004000 {
1124                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1125                         arm,primecell-periphid = <0x00253180>;
1126                         reg = <0x48004000 0x400>;
1127                         interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1128                         interrupt-names = "cmd_irq";
1129                         clocks = <&rcc SDMMC3_K>;
1130                         clock-names = "apb_pclk";
1131                         resets = <&rcc SDMMC3_R>;
1132                         cap-sd-highspeed;
1133                         cap-mmc-highspeed;
1134                         max-frequency = <120000000>;
1135                         status = "disabled";
1136                 };
1137
1138                 usbotg_hs: usb-otg@49000000 {
1139                         compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1140                         reg = <0x49000000 0x10000>;
1141                         clocks = <&rcc USBO_K>;
1142                         clock-names = "otg";
1143                         resets = <&rcc USBO_R>;
1144                         reset-names = "dwc2";
1145                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1146                         g-rx-fifo-size = <512>;
1147                         g-np-tx-fifo-size = <32>;
1148                         g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
1149                         dr_mode = "otg";
1150                         otg-rev = <0x200>;
1151                         usb33d-supply = <&usb33>;
1152                         status = "disabled";
1153                 };
1154
1155                 ipcc: mailbox@4c001000 {
1156                         compatible = "st,stm32mp1-ipcc";
1157                         #mbox-cells = <1>;
1158                         reg = <0x4c001000 0x400>;
1159                         st,proc-id = <0>;
1160                         interrupts-extended =
1161                                 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1162                                 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1163                                 <&exti 61 1>;
1164                         interrupt-names = "rx", "tx", "wakeup";
1165                         clocks = <&rcc IPCC>;
1166                         wakeup-source;
1167                         status = "disabled";
1168                 };
1169
1170                 dcmi: dcmi@4c006000 {
1171                         compatible = "st,stm32-dcmi";
1172                         reg = <0x4c006000 0x400>;
1173                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1174                         resets = <&rcc CAMITF_R>;
1175                         clocks = <&rcc DCMI>;
1176                         clock-names = "mclk";
1177                         dmas = <&dmamux1 75 0x400 0x01>;
1178                         dma-names = "tx";
1179                         status = "disabled";
1180                 };
1181
1182                 rcc: rcc@50000000 {
1183                         compatible = "st,stm32mp1-rcc", "syscon";
1184                         reg = <0x50000000 0x1000>;
1185                         #clock-cells = <1>;
1186                         #reset-cells = <1>;
1187                 };
1188
1189                 pwr_regulators: pwr@50001000 {
1190                         compatible = "st,stm32mp1,pwr-reg";
1191                         reg = <0x50001000 0x10>;
1192
1193                         reg11: reg11 {
1194                                 regulator-name = "reg11";
1195                                 regulator-min-microvolt = <1100000>;
1196                                 regulator-max-microvolt = <1100000>;
1197                         };
1198
1199                         reg18: reg18 {
1200                                 regulator-name = "reg18";
1201                                 regulator-min-microvolt = <1800000>;
1202                                 regulator-max-microvolt = <1800000>;
1203                         };
1204
1205                         usb33: usb33 {
1206                                 regulator-name = "usb33";
1207                                 regulator-min-microvolt = <3300000>;
1208                                 regulator-max-microvolt = <3300000>;
1209                         };
1210                 };
1211
1212                 pwr_mcu: pwr_mcu@50001014 {
1213                         compatible = "st,stm32mp151-pwr-mcu", "syscon";
1214                         reg = <0x50001014 0x4>;
1215                 };
1216
1217                 exti: interrupt-controller@5000d000 {
1218                         compatible = "st,stm32mp1-exti", "syscon";
1219                         interrupt-controller;
1220                         #interrupt-cells = <2>;
1221                         reg = <0x5000d000 0x400>;
1222                 };
1223
1224                 syscfg: syscon@50020000 {
1225                         compatible = "st,stm32mp157-syscfg", "syscon";
1226                         reg = <0x50020000 0x400>;
1227                         clocks = <&rcc SYSCFG>;
1228                 };
1229
1230                 lptimer2: timer@50021000 {
1231                         #address-cells = <1>;
1232                         #size-cells = <0>;
1233                         compatible = "st,stm32-lptimer";
1234                         reg = <0x50021000 0x400>;
1235                         interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
1236                         clocks = <&rcc LPTIM2_K>;
1237                         clock-names = "mux";
1238                         wakeup-source;
1239                         status = "disabled";
1240
1241                         pwm {
1242                                 compatible = "st,stm32-pwm-lp";
1243                                 #pwm-cells = <3>;
1244                                 status = "disabled";
1245                         };
1246
1247                         trigger@1 {
1248                                 compatible = "st,stm32-lptimer-trigger";
1249                                 reg = <1>;
1250                                 status = "disabled";
1251                         };
1252
1253                         counter {
1254                                 compatible = "st,stm32-lptimer-counter";
1255                                 status = "disabled";
1256                         };
1257                 };
1258
1259                 lptimer3: timer@50022000 {
1260                         #address-cells = <1>;
1261                         #size-cells = <0>;
1262                         compatible = "st,stm32-lptimer";
1263                         reg = <0x50022000 0x400>;
1264                         interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
1265                         clocks = <&rcc LPTIM3_K>;
1266                         clock-names = "mux";
1267                         wakeup-source;
1268                         status = "disabled";
1269
1270                         pwm {
1271                                 compatible = "st,stm32-pwm-lp";
1272                                 #pwm-cells = <3>;
1273                                 status = "disabled";
1274                         };
1275
1276                         trigger@2 {
1277                                 compatible = "st,stm32-lptimer-trigger";
1278                                 reg = <2>;
1279                                 status = "disabled";
1280                         };
1281                 };
1282
1283                 lptimer4: timer@50023000 {
1284                         compatible = "st,stm32-lptimer";
1285                         reg = <0x50023000 0x400>;
1286                         interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
1287                         clocks = <&rcc LPTIM4_K>;
1288                         clock-names = "mux";
1289                         wakeup-source;
1290                         status = "disabled";
1291
1292                         pwm {
1293                                 compatible = "st,stm32-pwm-lp";
1294                                 #pwm-cells = <3>;
1295                                 status = "disabled";
1296                         };
1297                 };
1298
1299                 lptimer5: timer@50024000 {
1300                         compatible = "st,stm32-lptimer";
1301                         reg = <0x50024000 0x400>;
1302                         interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
1303                         clocks = <&rcc LPTIM5_K>;
1304                         clock-names = "mux";
1305                         wakeup-source;
1306                         status = "disabled";
1307
1308                         pwm {
1309                                 compatible = "st,stm32-pwm-lp";
1310                                 #pwm-cells = <3>;
1311                                 status = "disabled";
1312                         };
1313                 };
1314
1315                 vrefbuf: vrefbuf@50025000 {
1316                         compatible = "st,stm32-vrefbuf";
1317                         reg = <0x50025000 0x8>;
1318                         regulator-min-microvolt = <1500000>;
1319                         regulator-max-microvolt = <2500000>;
1320                         clocks = <&rcc VREF>;
1321                         status = "disabled";
1322                 };
1323
1324                 sai4: sai@50027000 {
1325                         compatible = "st,stm32h7-sai";
1326                         #address-cells = <1>;
1327                         #size-cells = <1>;
1328                         ranges = <0 0x50027000 0x400>;
1329                         reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1330                         interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1331                         resets = <&rcc SAI4_R>;
1332                         status = "disabled";
1333
1334                         sai4a: audio-controller@50027004 {
1335                                 #sound-dai-cells = <0>;
1336                                 compatible = "st,stm32-sai-sub-a";
1337                                 reg = <0x04 0x20>;
1338                                 clocks = <&rcc SAI4_K>;
1339                                 clock-names = "sai_ck";
1340                                 dmas = <&dmamux1 99 0x400 0x01>;
1341                                 status = "disabled";
1342                         };
1343
1344                         sai4b: audio-controller@50027024 {
1345                                 #sound-dai-cells = <0>;
1346                                 compatible = "st,stm32-sai-sub-b";
1347                                 reg = <0x24 0x20>;
1348                                 clocks = <&rcc SAI4_K>;
1349                                 clock-names = "sai_ck";
1350                                 dmas = <&dmamux1 100 0x400 0x01>;
1351                                 status = "disabled";
1352                         };
1353                 };
1354
1355                 dts: thermal@50028000 {
1356                         compatible = "st,stm32-thermal";
1357                         reg = <0x50028000 0x100>;
1358                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1359                         clocks = <&rcc TMPSENS>;
1360                         clock-names = "pclk";
1361                         #thermal-sensor-cells = <0>;
1362                         status = "disabled";
1363                 };
1364
1365                 hash1: hash@54002000 {
1366                         compatible = "st,stm32f756-hash";
1367                         reg = <0x54002000 0x400>;
1368                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1369                         clocks = <&rcc HASH1>;
1370                         resets = <&rcc HASH1_R>;
1371                         dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
1372                         dma-names = "in";
1373                         dma-maxburst = <2>;
1374                         status = "disabled";
1375                 };
1376
1377                 rng1: rng@54003000 {
1378                         compatible = "st,stm32-rng";
1379                         reg = <0x54003000 0x400>;
1380                         clocks = <&rcc RNG1_K>;
1381                         resets = <&rcc RNG1_R>;
1382                         status = "disabled";
1383                 };
1384
1385                 mdma1: dma-controller@58000000 {
1386                         compatible = "st,stm32h7-mdma";
1387                         reg = <0x58000000 0x1000>;
1388                         interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1389                         clocks = <&rcc MDMA>;
1390                         resets = <&rcc MDMA_R>;
1391                         #dma-cells = <5>;
1392                         dma-channels = <32>;
1393                         dma-requests = <48>;
1394                 };
1395
1396                 fmc: memory-controller@58002000 {
1397                         #address-cells = <2>;
1398                         #size-cells = <1>;
1399                         compatible = "st,stm32mp1-fmc2-ebi";
1400                         reg = <0x58002000 0x1000>;
1401                         clocks = <&rcc FMC_K>;
1402                         resets = <&rcc FMC_R>;
1403                         status = "disabled";
1404
1405                         ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
1406                                  <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
1407                                  <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
1408                                  <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
1409                                  <4 0 0x80000000 0x10000000>; /* NAND */
1410
1411                         nand-controller@4,0 {
1412                                 #address-cells = <1>;
1413                                 #size-cells = <0>;
1414                                 compatible = "st,stm32mp1-fmc2-nfc";
1415                                 reg = <4 0x00000000 0x1000>,
1416                                       <4 0x08010000 0x1000>,
1417                                       <4 0x08020000 0x1000>,
1418                                       <4 0x01000000 0x1000>,
1419                                       <4 0x09010000 0x1000>,
1420                                       <4 0x09020000 0x1000>;
1421                                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1422                                 dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
1423                                        <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
1424                                        <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
1425                                 dma-names = "tx", "rx", "ecc";
1426                                 status = "disabled";
1427                         };
1428                 };
1429
1430                 qspi: spi@58003000 {
1431                         compatible = "st,stm32f469-qspi";
1432                         reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1433                         reg-names = "qspi", "qspi_mm";
1434                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1435                         dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>,
1436                                <&mdma1 22 0x2 0x10100008 0x0 0x0>;
1437                         dma-names = "tx", "rx";
1438                         clocks = <&rcc QSPI_K>;
1439                         resets = <&rcc QSPI_R>;
1440                         #address-cells = <1>;
1441                         #size-cells = <0>;
1442                         status = "disabled";
1443                 };
1444
1445                 sdmmc1: mmc@58005000 {
1446                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1447                         arm,primecell-periphid = <0x00253180>;
1448                         reg = <0x58005000 0x1000>;
1449                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1450                         interrupt-names = "cmd_irq";
1451                         clocks = <&rcc SDMMC1_K>;
1452                         clock-names = "apb_pclk";
1453                         resets = <&rcc SDMMC1_R>;
1454                         cap-sd-highspeed;
1455                         cap-mmc-highspeed;
1456                         max-frequency = <120000000>;
1457                         status = "disabled";
1458                 };
1459
1460                 sdmmc2: mmc@58007000 {
1461                         compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
1462                         arm,primecell-periphid = <0x00253180>;
1463                         reg = <0x58007000 0x1000>;
1464                         interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1465                         interrupt-names = "cmd_irq";
1466                         clocks = <&rcc SDMMC2_K>;
1467                         clock-names = "apb_pclk";
1468                         resets = <&rcc SDMMC2_R>;
1469                         cap-sd-highspeed;
1470                         cap-mmc-highspeed;
1471                         max-frequency = <120000000>;
1472                         status = "disabled";
1473                 };
1474
1475                 crc1: crc@58009000 {
1476                         compatible = "st,stm32f7-crc";
1477                         reg = <0x58009000 0x400>;
1478                         clocks = <&rcc CRC1>;
1479                         status = "disabled";
1480                 };
1481
1482                 ethernet0: ethernet@5800a000 {
1483                         compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1484                         reg = <0x5800a000 0x2000>;
1485                         reg-names = "stmmaceth";
1486                         interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1487                         interrupt-names = "macirq";
1488                         clock-names = "stmmaceth",
1489                                       "mac-clk-tx",
1490                                       "mac-clk-rx",
1491                                       "eth-ck",
1492                                       "ptp_ref",
1493                                       "ethstp";
1494                         clocks = <&rcc ETHMAC>,
1495                                  <&rcc ETHTX>,
1496                                  <&rcc ETHRX>,
1497                                  <&rcc ETHCK_K>,
1498                                  <&rcc ETHPTP_K>,
1499                                  <&rcc ETHSTP>;
1500                         st,syscon = <&syscfg 0x4>;
1501                         snps,mixed-burst;
1502                         snps,pbl = <2>;
1503                         snps,en-tx-lpi-clockgating;
1504                         snps,axi-config = <&stmmac_axi_config_0>;
1505                         snps,tso;
1506                         status = "disabled";
1507
1508                         stmmac_axi_config_0: stmmac-axi-config {
1509                                 snps,wr_osr_lmt = <0x7>;
1510                                 snps,rd_osr_lmt = <0x7>;
1511                                 snps,blen = <0 0 0 0 16 8 4>;
1512                         };
1513                 };
1514
1515                 usbh_ohci: usb@5800c000 {
1516                         compatible = "generic-ohci";
1517                         reg = <0x5800c000 0x1000>;
1518                         clocks = <&rcc USBH>, <&usbphyc>;
1519                         resets = <&rcc USBH_R>;
1520                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1521                         status = "disabled";
1522                 };
1523
1524                 usbh_ehci: usb@5800d000 {
1525                         compatible = "generic-ehci";
1526                         reg = <0x5800d000 0x1000>;
1527                         clocks = <&rcc USBH>;
1528                         resets = <&rcc USBH_R>;
1529                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1530                         companion = <&usbh_ohci>;
1531                         status = "disabled";
1532                 };
1533
1534                 ltdc: display-controller@5a001000 {
1535                         compatible = "st,stm32-ltdc";
1536                         reg = <0x5a001000 0x400>;
1537                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1538                                      <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1539                         clocks = <&rcc LTDC_PX>;
1540                         clock-names = "lcd";
1541                         resets = <&rcc LTDC_R>;
1542                         status = "disabled";
1543
1544                         port {
1545                                 #address-cells = <1>;
1546                                 #size-cells = <0>;
1547                         };
1548                 };
1549
1550                 iwdg2: watchdog@5a002000 {
1551                         compatible = "st,stm32mp1-iwdg";
1552                         reg = <0x5a002000 0x400>;
1553                         clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1554                         clock-names = "pclk", "lsi";
1555                         status = "disabled";
1556                 };
1557
1558                 usbphyc: usbphyc@5a006000 {
1559                         #address-cells = <1>;
1560                         #size-cells = <0>;
1561                         #clock-cells = <0>;
1562                         compatible = "st,stm32mp1-usbphyc";
1563                         reg = <0x5a006000 0x1000>;
1564                         clocks = <&rcc USBPHY_K>;
1565                         resets = <&rcc USBPHY_R>;
1566                         vdda1v1-supply = <&reg11>;
1567                         vdda1v8-supply = <&reg18>;
1568                         status = "disabled";
1569
1570                         usbphyc_port0: usb-phy@0 {
1571                                 #phy-cells = <0>;
1572                                 reg = <0>;
1573                         };
1574
1575                         usbphyc_port1: usb-phy@1 {
1576                                 #phy-cells = <1>;
1577                                 reg = <1>;
1578                         };
1579                 };
1580
1581                 usart1: serial@5c000000 {
1582                         compatible = "st,stm32h7-uart";
1583                         reg = <0x5c000000 0x400>;
1584                         interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
1585                         clocks = <&rcc USART1_K>;
1586                         wakeup-source;
1587                         status = "disabled";
1588                 };
1589
1590                 spi6: spi@5c001000 {
1591                         #address-cells = <1>;
1592                         #size-cells = <0>;
1593                         compatible = "st,stm32h7-spi";
1594                         reg = <0x5c001000 0x400>;
1595                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1596                         clocks = <&rcc SPI6_K>;
1597                         resets = <&rcc SPI6_R>;
1598                         dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1599                                <&mdma1 35 0x0 0x40002 0x0 0x0>;
1600                         dma-names = "rx", "tx";
1601                         status = "disabled";
1602                 };
1603
1604                 i2c4: i2c@5c002000 {
1605                         compatible = "st,stm32mp15-i2c";
1606                         reg = <0x5c002000 0x400>;
1607                         interrupt-names = "event", "error";
1608                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1609                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1610                         clocks = <&rcc I2C4_K>;
1611                         resets = <&rcc I2C4_R>;
1612                         #address-cells = <1>;
1613                         #size-cells = <0>;
1614                         st,syscfg-fmp = <&syscfg 0x4 0x8>;
1615                         wakeup-source;
1616                         i2c-analog-filter;
1617                         status = "disabled";
1618                 };
1619
1620                 rtc: rtc@5c004000 {
1621                         compatible = "st,stm32mp1-rtc";
1622                         reg = <0x5c004000 0x400>;
1623                         clocks = <&rcc RTCAPB>, <&rcc RTC>;
1624                         clock-names = "pclk", "rtc_ck";
1625                         interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
1626                         status = "disabled";
1627                 };
1628
1629                 bsec: efuse@5c005000 {
1630                         compatible = "st,stm32mp15-bsec";
1631                         reg = <0x5c005000 0x400>;
1632                         #address-cells = <1>;
1633                         #size-cells = <1>;
1634                         ts_cal1: calib@5c {
1635                                 reg = <0x5c 0x2>;
1636                         };
1637                         ts_cal2: calib@5e {
1638                                 reg = <0x5e 0x2>;
1639                         };
1640                 };
1641
1642                 i2c6: i2c@5c009000 {
1643                         compatible = "st,stm32mp15-i2c";
1644                         reg = <0x5c009000 0x400>;
1645                         interrupt-names = "event", "error";
1646                         interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1647                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1648                         clocks = <&rcc I2C6_K>;
1649                         resets = <&rcc I2C6_R>;
1650                         #address-cells = <1>;
1651                         #size-cells = <0>;
1652                         st,syscfg-fmp = <&syscfg 0x4 0x20>;
1653                         wakeup-source;
1654                         i2c-analog-filter;
1655                         status = "disabled";
1656                 };
1657
1658                 tamp: tamp@5c00a000 {
1659                         compatible = "st,stm32-tamp", "syscon", "simple-mfd";
1660                         reg = <0x5c00a000 0x400>;
1661                 };
1662
1663                 /*
1664                  * Break node order to solve dependency probe issue between
1665                  * pinctrl and exti.
1666                  */
1667                 pinctrl: pinctrl@50002000 {
1668                         #address-cells = <1>;
1669                         #size-cells = <1>;
1670                         compatible = "st,stm32mp157-pinctrl";
1671                         ranges = <0 0x50002000 0xa400>;
1672                         interrupt-parent = <&exti>;
1673                         st,syscfg = <&exti 0x60 0xff>;
1674                         pins-are-numbered;
1675
1676                         gpioa: gpio@50002000 {
1677                                 gpio-controller;
1678                                 #gpio-cells = <2>;
1679                                 interrupt-controller;
1680                                 #interrupt-cells = <2>;
1681                                 reg = <0x0 0x400>;
1682                                 clocks = <&rcc GPIOA>;
1683                                 st,bank-name = "GPIOA";
1684                                 status = "disabled";
1685                         };
1686
1687                         gpiob: gpio@50003000 {
1688                                 gpio-controller;
1689                                 #gpio-cells = <2>;
1690                                 interrupt-controller;
1691                                 #interrupt-cells = <2>;
1692                                 reg = <0x1000 0x400>;
1693                                 clocks = <&rcc GPIOB>;
1694                                 st,bank-name = "GPIOB";
1695                                 status = "disabled";
1696                         };
1697
1698                         gpioc: gpio@50004000 {
1699                                 gpio-controller;
1700                                 #gpio-cells = <2>;
1701                                 interrupt-controller;
1702                                 #interrupt-cells = <2>;
1703                                 reg = <0x2000 0x400>;
1704                                 clocks = <&rcc GPIOC>;
1705                                 st,bank-name = "GPIOC";
1706                                 status = "disabled";
1707                         };
1708
1709                         gpiod: gpio@50005000 {
1710                                 gpio-controller;
1711                                 #gpio-cells = <2>;
1712                                 interrupt-controller;
1713                                 #interrupt-cells = <2>;
1714                                 reg = <0x3000 0x400>;
1715                                 clocks = <&rcc GPIOD>;
1716                                 st,bank-name = "GPIOD";
1717                                 status = "disabled";
1718                         };
1719
1720                         gpioe: gpio@50006000 {
1721                                 gpio-controller;
1722                                 #gpio-cells = <2>;
1723                                 interrupt-controller;
1724                                 #interrupt-cells = <2>;
1725                                 reg = <0x4000 0x400>;
1726                                 clocks = <&rcc GPIOE>;
1727                                 st,bank-name = "GPIOE";
1728                                 status = "disabled";
1729                         };
1730
1731                         gpiof: gpio@50007000 {
1732                                 gpio-controller;
1733                                 #gpio-cells = <2>;
1734                                 interrupt-controller;
1735                                 #interrupt-cells = <2>;
1736                                 reg = <0x5000 0x400>;
1737                                 clocks = <&rcc GPIOF>;
1738                                 st,bank-name = "GPIOF";
1739                                 status = "disabled";
1740                         };
1741
1742                         gpiog: gpio@50008000 {
1743                                 gpio-controller;
1744                                 #gpio-cells = <2>;
1745                                 interrupt-controller;
1746                                 #interrupt-cells = <2>;
1747                                 reg = <0x6000 0x400>;
1748                                 clocks = <&rcc GPIOG>;
1749                                 st,bank-name = "GPIOG";
1750                                 status = "disabled";
1751                         };
1752
1753                         gpioh: gpio@50009000 {
1754                                 gpio-controller;
1755                                 #gpio-cells = <2>;
1756                                 interrupt-controller;
1757                                 #interrupt-cells = <2>;
1758                                 reg = <0x7000 0x400>;
1759                                 clocks = <&rcc GPIOH>;
1760                                 st,bank-name = "GPIOH";
1761                                 status = "disabled";
1762                         };
1763
1764                         gpioi: gpio@5000a000 {
1765                                 gpio-controller;
1766                                 #gpio-cells = <2>;
1767                                 interrupt-controller;
1768                                 #interrupt-cells = <2>;
1769                                 reg = <0x8000 0x400>;
1770                                 clocks = <&rcc GPIOI>;
1771                                 st,bank-name = "GPIOI";
1772                                 status = "disabled";
1773                         };
1774
1775                         gpioj: gpio@5000b000 {
1776                                 gpio-controller;
1777                                 #gpio-cells = <2>;
1778                                 interrupt-controller;
1779                                 #interrupt-cells = <2>;
1780                                 reg = <0x9000 0x400>;
1781                                 clocks = <&rcc GPIOJ>;
1782                                 st,bank-name = "GPIOJ";
1783                                 status = "disabled";
1784                         };
1785
1786                         gpiok: gpio@5000c000 {
1787                                 gpio-controller;
1788                                 #gpio-cells = <2>;
1789                                 interrupt-controller;
1790                                 #interrupt-cells = <2>;
1791                                 reg = <0xa000 0x400>;
1792                                 clocks = <&rcc GPIOK>;
1793                                 st,bank-name = "GPIOK";
1794                                 status = "disabled";
1795                         };
1796                 };
1797
1798                 pinctrl_z: pinctrl@54004000 {
1799                         #address-cells = <1>;
1800                         #size-cells = <1>;
1801                         compatible = "st,stm32mp157-z-pinctrl";
1802                         ranges = <0 0x54004000 0x400>;
1803                         pins-are-numbered;
1804                         interrupt-parent = <&exti>;
1805                         st,syscfg = <&exti 0x60 0xff>;
1806
1807                         gpioz: gpio@54004000 {
1808                                 gpio-controller;
1809                                 #gpio-cells = <2>;
1810                                 interrupt-controller;
1811                                 #interrupt-cells = <2>;
1812                                 reg = <0 0x400>;
1813                                 clocks = <&rcc GPIOZ>;
1814                                 st,bank-name = "GPIOZ";
1815                                 st,bank-ioport = <11>;
1816                                 status = "disabled";
1817                         };
1818                 };
1819         };
1820
1821         mlahb: ahb {
1822                 compatible = "st,mlahb", "simple-bus";
1823                 #address-cells = <1>;
1824                 #size-cells = <1>;
1825                 ranges;
1826                 dma-ranges = <0x00000000 0x38000000 0x10000>,
1827                              <0x10000000 0x10000000 0x60000>,
1828                              <0x30000000 0x30000000 0x60000>;
1829
1830                 m4_rproc: m4@10000000 {
1831                         compatible = "st,stm32mp1-m4";
1832                         reg = <0x10000000 0x40000>,
1833                               <0x30000000 0x40000>,
1834                               <0x38000000 0x10000>;
1835                         resets = <&rcc MCU_R>;
1836                         st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1837                         st,syscfg-tz = <&rcc 0x000 0x1>;
1838                         st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1839                         st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>;
1840                         st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>;
1841                         status = "disabled";
1842                 };
1843         };
1844 };