2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include "skeleton.dtsi"
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/clock/stm32h7-clks.h>
46 #include <dt-bindings/mfd/stm32h7-rcc.h>
47 #include <dt-bindings/interrupt-controller/irq.h>
53 compatible = "fixed-clock";
54 clock-frequency = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <32768>;
65 compatible = "fixed-clock";
66 clock-frequency = <0>;
71 timer5: timer@40000c00 {
72 compatible = "st,stm32-timer";
73 reg = <0x40000c00 0x400>;
75 clocks = <&rcc TIM5_CK>;
78 lptimer1: timer@40002400 {
81 compatible = "st,stm32-lptimer";
82 reg = <0x40002400 0x400>;
83 clocks = <&rcc LPTIM1_CK>;
88 compatible = "st,stm32-pwm-lp";
94 compatible = "st,stm32-lptimer-trigger";
100 compatible = "st,stm32-lptimer-counter";
106 #address-cells = <1>;
108 compatible = "st,stm32h7-spi";
109 reg = <0x40003800 0x400>;
111 clocks = <&rcc SPI2_CK>;
117 #address-cells = <1>;
119 compatible = "st,stm32h7-spi";
120 reg = <0x40003c00 0x400>;
122 clocks = <&rcc SPI3_CK>;
126 usart2: serial@40004400 {
127 compatible = "st,stm32f7-uart";
128 reg = <0x40004400 0x400>;
131 clocks = <&rcc USART2_CK>;
135 compatible = "st,stm32f7-i2c";
136 #address-cells = <1>;
138 reg = <0x40005400 0x400>;
141 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
142 clocks = <&rcc I2C1_CK>;
147 compatible = "st,stm32f7-i2c";
148 #address-cells = <1>;
150 reg = <0x40005800 0x400>;
153 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
154 clocks = <&rcc I2C2_CK>;
159 compatible = "st,stm32f7-i2c";
160 #address-cells = <1>;
162 reg = <0x40005C00 0x400>;
165 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
166 clocks = <&rcc I2C3_CK>;
171 compatible = "st,stm32h7-dac-core";
172 reg = <0x40007400 0x400>;
173 clocks = <&rcc DAC12_CK>;
174 clock-names = "pclk";
175 #address-cells = <1>;
180 compatible = "st,stm32-dac";
181 #io-channels-cells = <1>;
187 compatible = "st,stm32-dac";
188 #io-channels-cells = <1>;
194 usart1: serial@40011000 {
195 compatible = "st,stm32f7-uart";
196 reg = <0x40011000 0x400>;
199 clocks = <&rcc USART1_CK>;
203 #address-cells = <1>;
205 compatible = "st,stm32h7-spi";
206 reg = <0x40013000 0x400>;
208 clocks = <&rcc SPI1_CK>;
213 #address-cells = <1>;
215 compatible = "st,stm32h7-spi";
216 reg = <0x40013400 0x400>;
218 clocks = <&rcc SPI4_CK>;
223 #address-cells = <1>;
225 compatible = "st,stm32h7-spi";
226 reg = <0x40015000 0x400>;
228 clocks = <&rcc SPI5_CK>;
233 compatible = "st,stm32-dma";
234 reg = <0x40020000 0x400>;
243 clocks = <&rcc DMA1_CK>;
251 compatible = "st,stm32-dma";
252 reg = <0x40020400 0x400>;
261 clocks = <&rcc DMA2_CK>;
268 dmamux1: dma-router@40020800 {
269 compatible = "st,stm32h7-dmamux";
270 reg = <0x40020800 0x1c>;
273 dma-requests = <128>;
274 dma-masters = <&dma1 &dma2>;
275 clocks = <&rcc DMA1_CK>;
278 adc_12: adc@40022000 {
279 compatible = "st,stm32h7-adc-core";
280 reg = <0x40022000 0x400>;
282 clocks = <&rcc ADC12_CK>;
284 interrupt-controller;
285 #interrupt-cells = <1>;
286 #address-cells = <1>;
291 compatible = "st,stm32h7-adc";
292 #io-channel-cells = <1>;
294 interrupt-parent = <&adc_12>;
300 compatible = "st,stm32h7-adc";
301 #io-channel-cells = <1>;
303 interrupt-parent = <&adc_12>;
309 usbotg_hs: usb@40040000 {
310 compatible = "st,stm32f7-hsotg";
311 reg = <0x40040000 0x40000>;
313 clocks = <&rcc USB1OTG_CK>;
315 g-rx-fifo-size = <256>;
316 g-np-tx-fifo-size = <32>;
317 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
321 usbotg_fs: usb@40080000 {
322 compatible = "st,stm32f4x9-fsotg";
323 reg = <0x40080000 0x40000>;
325 clocks = <&rcc USB2OTG_CK>;
330 mdma1: dma@52000000 {
331 compatible = "st,stm32h7-mdma";
332 reg = <0x52000000 0x1000>;
334 clocks = <&rcc MDMA_CK>;
340 exti: interrupt-controller@58000000 {
341 compatible = "st,stm32h7-exti";
342 interrupt-controller;
343 #interrupt-cells = <2>;
344 reg = <0x58000000 0x400>;
345 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
348 syscfg: system-config@58000400 {
349 compatible = "syscon";
350 reg = <0x58000400 0x400>;
354 #address-cells = <1>;
356 compatible = "st,stm32h7-spi";
357 reg = <0x58001400 0x400>;
359 clocks = <&rcc SPI6_CK>;
364 compatible = "st,stm32f7-i2c";
365 #address-cells = <1>;
367 reg = <0x58001C00 0x400>;
370 resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
371 clocks = <&rcc I2C4_CK>;
375 lptimer2: timer@58002400 {
376 #address-cells = <1>;
378 compatible = "st,stm32-lptimer";
379 reg = <0x58002400 0x400>;
380 clocks = <&rcc LPTIM2_CK>;
385 compatible = "st,stm32-pwm-lp";
391 compatible = "st,stm32-lptimer-trigger";
397 compatible = "st,stm32-lptimer-counter";
402 lptimer3: timer@58002800 {
403 #address-cells = <1>;
405 compatible = "st,stm32-lptimer";
406 reg = <0x58002800 0x400>;
407 clocks = <&rcc LPTIM3_CK>;
412 compatible = "st,stm32-pwm-lp";
418 compatible = "st,stm32-lptimer-trigger";
424 lptimer4: timer@58002c00 {
425 #address-cells = <1>;
427 compatible = "st,stm32-lptimer";
428 reg = <0x58002c00 0x400>;
429 clocks = <&rcc LPTIM4_CK>;
434 compatible = "st,stm32-pwm-lp";
440 lptimer5: timer@58003000 {
441 #address-cells = <1>;
443 compatible = "st,stm32-lptimer";
444 reg = <0x58003000 0x400>;
445 clocks = <&rcc LPTIM5_CK>;
450 compatible = "st,stm32-pwm-lp";
456 vrefbuf: regulator@58003c00 {
457 compatible = "st,stm32-vrefbuf";
458 reg = <0x58003C00 0x8>;
459 clocks = <&rcc VREF_CK>;
460 regulator-min-microvolt = <1500000>;
461 regulator-max-microvolt = <2500000>;
466 compatible = "st,stm32h7-rtc";
467 reg = <0x58004000 0x400>;
468 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
469 clock-names = "pclk", "rtc_ck";
470 assigned-clocks = <&rcc RTC_CK>;
471 assigned-clock-parents = <&rcc LSE_CK>;
472 interrupt-parent = <&exti>;
473 interrupts = <17 IRQ_TYPE_EDGE_RISING>;
474 interrupt-names = "alarm";
475 st,syscfg = <&pwrcfg 0x00 0x100>;
479 rcc: reset-clock-controller@58024400 {
480 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
481 reg = <0x58024400 0x400>;
484 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
485 st,syscfg = <&pwrcfg>;
488 pwrcfg: power-config@58024800 {
489 compatible = "syscon";
490 reg = <0x58024800 0x400>;
493 adc_3: adc@58026000 {
494 compatible = "st,stm32h7-adc-core";
495 reg = <0x58026000 0x400>;
497 clocks = <&rcc ADC3_CK>;
499 interrupt-controller;
500 #interrupt-cells = <1>;
501 #address-cells = <1>;
506 compatible = "st,stm32h7-adc";
507 #io-channel-cells = <1>;
509 interrupt-parent = <&adc_3>;
518 clock-frequency = <250000000>;