Merge git://git.kvack.org/~bcrl/aio-next
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / stih416-pinctrl.dtsi
1
2 /*
3  * Copyright (C) 2013 STMicroelectronics Limited.
4  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * publishhed by the Free Software Foundation.
9  */
10 #include "st-pincfg.h"
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 / {
13
14         aliases {
15                 gpio0   = &PIO0;
16                 gpio1   = &PIO1;
17                 gpio2   = &PIO2;
18                 gpio3   = &PIO3;
19                 gpio4   = &PIO4;
20                 gpio5   = &PIO40;
21                 gpio6   = &PIO5;
22                 gpio7   = &PIO6;
23                 gpio8   = &PIO7;
24                 gpio9   = &PIO8;
25                 gpio10  = &PIO9;
26                 gpio11  = &PIO10;
27                 gpio12  = &PIO11;
28                 gpio13  = &PIO12;
29                 gpio14  = &PIO30;
30                 gpio15  = &PIO31;
31                 gpio16  = &PIO13;
32                 gpio17  = &PIO14;
33                 gpio18  = &PIO15;
34                 gpio19  = &PIO16;
35                 gpio20  = &PIO17;
36                 gpio21  = &PIO18;
37                 gpio22  = &PIO100;
38                 gpio23  = &PIO101;
39                 gpio24  = &PIO102;
40                 gpio25  = &PIO103;
41                 gpio26  = &PIO104;
42                 gpio27  = &PIO105;
43                 gpio28  = &PIO106;
44                 gpio29  = &PIO107;
45         };
46
47         soc {
48                 pin-controller-sbc {
49                         #address-cells  = <1>;
50                         #size-cells     = <1>;
51                         compatible      = "st,stih416-sbc-pinctrl";
52                         st,syscfg       = <&syscfg_sbc>;
53                         reg             = <0xfe61f080 0x4>;
54                         reg-names       = "irqmux";
55                         interrupts      = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
56                         interrupt-names = "irqmux";
57                         ranges          = <0 0xfe610000 0x6000>;
58
59                         PIO0: gpio@fe610000 {
60                                 gpio-controller;
61                                 #gpio-cells = <1>;
62                                 interrupt-controller;
63                                 #interrupt-cells = <2>;
64                                 reg             = <0 0x100>;
65                                 st,bank-name    = "PIO0";
66                         };
67                         PIO1: gpio@fe611000 {
68                                 gpio-controller;
69                                 #gpio-cells     = <1>;
70                                 interrupt-controller;
71                                 #interrupt-cells = <2>;
72                                 reg             = <0x1000 0x100>;
73                                 st,bank-name    = "PIO1";
74                         };
75                         PIO2: gpio@fe612000 {
76                                 gpio-controller;
77                                 #gpio-cells     = <1>;
78                                 interrupt-controller;
79                                 #interrupt-cells = <2>;
80                                 reg             = <0x2000 0x100>;
81                                 st,bank-name    = "PIO2";
82                         };
83                         PIO3: gpio@fe613000 {
84                                 gpio-controller;
85                                 #gpio-cells     = <1>;
86                                 interrupt-controller;
87                                 #interrupt-cells = <2>;
88                                 reg             = <0x3000 0x100>;
89                                 st,bank-name    = "PIO3";
90                         };
91                         PIO4: gpio@fe614000 {
92                                 gpio-controller;
93                                 #gpio-cells     = <1>;
94                                 interrupt-controller;
95                                 #interrupt-cells = <2>;
96                                 reg             = <0x4000 0x100>;
97                                 st,bank-name    = "PIO4";
98                         };
99                         PIO40: gpio@fe615000 {
100                                 gpio-controller;
101                                 #gpio-cells     = <1>;
102                                 interrupt-controller;
103                                 #interrupt-cells = <2>;
104                                 reg             = <0x5000 0x100>;
105                                 st,bank-name    = "PIO40";
106                                 st,retime-pin-mask = <0x7f>;
107                         };
108
109                         rc{
110                                 pinctrl_ir: ir0 {
111                                         st,pins {
112                                                 ir = <&PIO4 0 ALT2 IN>;
113                                         };
114                                 };
115                         };
116                         sbc_serial1 {
117                                 pinctrl_sbc_serial1: sbc_serial1 {
118                                         st,pins {
119                                                 tx      = <&PIO2 6 ALT3 OUT>;
120                                                 rx      = <&PIO2 7 ALT3 IN>;
121                                         };
122                                 };
123                         };
124
125                         keyscan {
126                                 pinctrl_keyscan: keyscan {
127                                         st,pins {
128                                                 keyin0 = <&PIO0 2 ALT2 IN>;
129                                                 keyin1 = <&PIO0 3 ALT2 IN>;
130                                                 keyin2 = <&PIO0 4 ALT2 IN>;
131                                                 keyin3 = <&PIO2 6 ALT2 IN>;
132
133                                                 keyout0 = <&PIO1 6 ALT2 OUT>;
134                                                 keyout1 = <&PIO1 7 ALT2 OUT>;
135                                                 keyout2 = <&PIO0 6 ALT2 OUT>;
136                                                 keyout3 = <&PIO2 7 ALT2 OUT>;
137                                         };
138                                 };
139                         };
140
141                         sbc_i2c0 {
142                                 pinctrl_sbc_i2c0_default: sbc_i2c0-default {
143                                         st,pins {
144                                                 sda = <&PIO4 6 ALT1 BIDIR>;
145                                                 scl = <&PIO4 5 ALT1 BIDIR>;
146                                         };
147                                 };
148                         };
149
150                         sbc_i2c1 {
151                                 pinctrl_sbc_i2c1_default: sbc_i2c1-default {
152                                         st,pins {
153                                                 sda = <&PIO3 2 ALT2 BIDIR>;
154                                                 scl = <&PIO3 1 ALT2 BIDIR>;
155                                         };
156                                 };
157                         };
158
159                         gmac1 {
160                                 pinctrl_mii1: mii1 {
161                                         st,pins {
162                                                 txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
163                                                 txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
164                                                 txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
165                                                 txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
166                                                 txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
167                                                 txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
168                                                 txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>;
169                                                 col =   <&PIO0 7 ALT1 IN BYPASS 1000>;
170
171                                                 mdio =  <&PIO1 0 ALT1 OUT BYPASS 1500>;
172                                                 mdc =   <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>;
173                                                 crs =   <&PIO1 2 ALT1 IN BYPASS 1000>;
174                                                 mdint = <&PIO1 3 ALT1 IN BYPASS 0>;
175                                                 rxd0 =  <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
176                                                 rxd1 =  <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
177                                                 rxd2 =  <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
178                                                 rxd3 =  <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
179
180                                                 rxdv =  <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
181                                                 rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
182                                                 rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>;
183                                                 phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>;
184                                         };
185                                 };
186                                 pinctrl_rgmii1: rgmii1-0 {
187                                         st,pins {
188                                                 txd0 =  <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>;
189                                                 txd1 =  <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>;
190                                                 txd2 =  <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>;
191                                                 txd3 =  <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>;
192                                                 txen =  <&PIO0 5 ALT1 OUT DE_IO 0   CLK_A>;
193                                                 txclk = <&PIO0 6 ALT1 IN  NICLK 0   CLK_A>;
194
195                                                 mdio = <&PIO1 0 ALT1 OUT BYPASS 0>;
196                                                 mdc  = <&PIO1 1 ALT1 OUT NICLK  0 CLK_A>;
197                                                 rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>;
198                                                 rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>;
199                                                 rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>;
200                                                 rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>;
201
202                                                 rxdv   = <&PIO2 0 ALT1 IN  DE_IO 500 CLK_A>;
203                                                 rxclk  = <&PIO2 2 ALT1 IN  NICLK 0   CLK_A>;
204                                                 phyclk = <&PIO2 3 ALT4 OUT NICLK 0   CLK_B>;
205
206                                                 clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>;
207                                         };
208                                 };
209                         };
210                 };
211
212                 pin-controller-front {
213                         #address-cells  = <1>;
214                         #size-cells     = <1>;
215                         compatible      = "st,stih416-front-pinctrl";
216                         st,syscfg       = <&syscfg_front>;
217                         reg             = <0xfee0f080 0x4>;
218                         reg-names       = "irqmux";
219                         interrupts      = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
220                         interrupt-names = "irqmux";
221                         ranges          = <0 0xfee00000 0x10000>;
222
223                         PIO5: gpio@fee00000 {
224                                 gpio-controller;
225                                 #gpio-cells     = <1>;
226                                 interrupt-controller;
227                                 #interrupt-cells = <2>;
228                                 reg             = <0 0x100>;
229                                 st,bank-name    = "PIO5";
230                         };
231                         PIO6: gpio@fee01000 {
232                                 gpio-controller;
233                                 #gpio-cells     = <1>;
234                                 interrupt-controller;
235                                 #interrupt-cells = <2>;
236                                 reg             = <0x1000 0x100>;
237                                 st,bank-name    = "PIO6";
238                         };
239                         PIO7: gpio@fee02000 {
240                                 gpio-controller;
241                                 #gpio-cells     = <1>;
242                                 interrupt-controller;
243                                 #interrupt-cells = <2>;
244                                 reg             = <0x2000 0x100>;
245                                 st,bank-name    = "PIO7";
246                         };
247                         PIO8: gpio@fee03000 {
248                                 gpio-controller;
249                                 #gpio-cells     = <1>;
250                                 interrupt-controller;
251                                 #interrupt-cells = <2>;
252                                 reg             = <0x3000 0x100>;
253                                 st,bank-name    = "PIO8";
254                         };
255                         PIO9: gpio@fee04000 {
256                                 gpio-controller;
257                                 #gpio-cells     = <1>;
258                                 interrupt-controller;
259                                 #interrupt-cells = <2>;
260                                 reg             = <0x4000 0x100>;
261                                 st,bank-name    = "PIO9";
262                         };
263                         PIO10: gpio@fee05000 {
264                                 gpio-controller;
265                                 #gpio-cells     = <1>;
266                                 interrupt-controller;
267                                 #interrupt-cells = <2>;
268                                 reg             = <0x5000 0x100>;
269                                 st,bank-name    = "PIO10";
270                         };
271                         PIO11: gpio@fee06000 {
272                                 gpio-controller;
273                                 #gpio-cells     = <1>;
274                                 interrupt-controller;
275                                 #interrupt-cells = <2>;
276                                 reg             = <0x6000 0x100>;
277                                 st,bank-name    = "PIO11";
278                         };
279                         PIO12: gpio@fee07000 {
280                                 gpio-controller;
281                                 #gpio-cells     = <1>;
282                                 interrupt-controller;
283                                 #interrupt-cells = <2>;
284                                 reg             = <0x7000 0x100>;
285                                 st,bank-name    = "PIO12";
286                         };
287                         PIO30: gpio@fee08000 {
288                                 gpio-controller;
289                                 #gpio-cells     = <1>;
290                                 interrupt-controller;
291                                 #interrupt-cells = <2>;
292                                 reg             = <0x8000 0x100>;
293                                 st,bank-name    = "PIO30";
294                         };
295                         PIO31: gpio@fee09000 {
296                                 gpio-controller;
297                                 #gpio-cells     = <1>;
298                                 interrupt-controller;
299                                 #interrupt-cells = <2>;
300                                 reg             = <0x9000 0x100>;
301                                 st,bank-name    = "PIO31";
302                         };
303
304                         serial2-oe {
305                                 pinctrl_serial2_oe: serial2-1 {
306                                         st,pins {
307                                                 output-enable   = <&PIO11 3 ALT2 OUT>;
308                                         };
309                                 };
310                         };
311
312                         i2c0 {
313                                 pinctrl_i2c0_default: i2c0-default {
314                                         st,pins {
315                                                 sda = <&PIO9 3 ALT1 BIDIR>;
316                                                 scl = <&PIO9 2 ALT1 BIDIR>;
317                                         };
318                                 };
319                         };
320
321                         i2c1 {
322                                 pinctrl_i2c1_default: i2c1-default {
323                                         st,pins {
324                                                 sda = <&PIO12 1 ALT1 BIDIR>;
325                                                 scl = <&PIO12 0 ALT1 BIDIR>;
326                                         };
327                                 };
328                         };
329
330                         fsm {
331                                 pinctrl_fsm: fsm {
332                                         st,pins {
333                                                 spi-fsm-clk  = <&PIO12 2 ALT1 OUT>;
334                                                 spi-fsm-cs   = <&PIO12 3 ALT1 OUT>;
335                                                 spi-fsm-mosi = <&PIO12 4 ALT1 OUT>;
336                                                 spi-fsm-miso = <&PIO12 5 ALT1 IN>;
337                                                 spi-fsm-hol  = <&PIO12 6 ALT1 OUT>;
338                                                 spi-fsm-wp   = <&PIO12 7 ALT1 OUT>;
339                                         };
340                                 };
341                         };
342                 };
343
344                 pin-controller-rear {
345                         #address-cells  = <1>;
346                         #size-cells     = <1>;
347                         compatible      = "st,stih416-rear-pinctrl";
348                         st,syscfg       = <&syscfg_rear>;
349                         reg             = <0xfe82f080 0x4>;
350                         reg-names       = "irqmux";
351                         interrupts      = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
352                         interrupt-names = "irqmux";
353                         ranges          = <0 0xfe820000 0x6000>;
354
355                         PIO13: gpio@fe820000 {
356                                 gpio-controller;
357                                 #gpio-cells     = <1>;
358                                 interrupt-controller;
359                                 #interrupt-cells = <2>;
360                                 reg             = <0 0x100>;
361                                 st,bank-name    = "PIO13";
362                         };
363                         PIO14: gpio@fe821000 {
364                                 gpio-controller;
365                                 #gpio-cells     = <1>;
366                                 interrupt-controller;
367                                 #interrupt-cells = <2>;
368                                 reg             = <0x1000 0x100>;
369                                 st,bank-name    = "PIO14";
370                         };
371                         PIO15: gpio@fe822000 {
372                                 gpio-controller;
373                                 #gpio-cells     = <1>;
374                                 interrupt-controller;
375                                 #interrupt-cells = <2>;
376                                 reg             = <0x2000 0x100>;
377                                 st,bank-name    = "PIO15";
378                         };
379                         PIO16: gpio@fe823000 {
380                                 gpio-controller;
381                                 #gpio-cells     = <1>;
382                                 interrupt-controller;
383                                 #interrupt-cells = <2>;
384                                 reg             = <0x3000 0x100>;
385                                 st,bank-name    = "PIO16";
386                         };
387                         PIO17: gpio@fe824000 {
388                                 gpio-controller;
389                                 #gpio-cells     = <1>;
390                                 interrupt-controller;
391                                 #interrupt-cells = <2>;
392                                 reg             = <0x4000 0x100>;
393                                 st,bank-name    = "PIO17";
394                         };
395                         PIO18: gpio@fe825000 {
396                                 gpio-controller;
397                                 #gpio-cells     = <1>;
398                                 interrupt-controller;
399                                 #interrupt-cells = <2>;
400                                 reg             = <0x5000 0x100>;
401                                 st,bank-name    = "PIO18";
402                                 st,retime-pin-mask = <0xf>;
403                         };
404
405                         serial2 {
406                                 pinctrl_serial2: serial2-0 {
407                                         st,pins {
408                                                 tx      = <&PIO17 4 ALT2 OUT>;
409                                                 rx      = <&PIO17 5 ALT2 IN>;
410                                         };
411                                 };
412                         };
413
414                         gmac0 {
415                                 pinctrl_mii0: mii0 {
416                                         st,pins {
417                                                 mdint = <&PIO13 6 ALT2 IN  BYPASS      0>;
418                                                 txen =  <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
419                                                 txd0 =  <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
420                                                 txd1 =  <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
421                                                 txd2 =  <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
422                                                 txd3 =  <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
423
424                                                 txclk = <&PIO15 0 ALT2 IN  NICLK       0 CLK_A>;
425                                                 txer =  <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
426                                                 crs = <&PIO15 2 ALT2 IN  BYPASS 1000>;
427                                                 col = <&PIO15 3 ALT2 IN  BYPASS 1000>;
428                                                 mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>;
429                                                 mdc = <&PIO15 5 ALT2 OUT NICLK  0    CLK_B>;
430
431                                                 rxd0 =  <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
432                                                 rxd1 =  <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
433                                                 rxd2 =  <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
434                                                 rxd3 =  <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
435                                                 rxdv =  <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
436                                                 rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
437                                                 rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
438                                                 phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>;
439                                         };
440                                 };
441
442                                 pinctrl_gmii0: gmii0 {
443                                         st,pins {
444                                                 };
445                                 };
446                                 pinctrl_rgmii0: rgmii0 {
447                                         st,pins {
448                                                  phyclk = <&PIO13  5 ALT4 OUT NICLK 0 CLK_B>;
449                                                  txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>;
450                                                  txd0  = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>;
451                                                  txd1  = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>;
452                                                  txd2  = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>;
453                                                  txd3  = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>;
454                                                  txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>;
455
456                                                  mdio = <&PIO15 4 ALT2 OUT BYPASS 0>;
457                                                  mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>;
458
459                                                  rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>;
460                                                  rxd0 =<&PIO16 0 ALT2 IN DE_IO  500 CLK_A>;
461                                                  rxd1 =<&PIO16 1 ALT2 IN DE_IO  500 CLK_A>;
462                                                  rxd2 =<&PIO16 2 ALT2 IN DE_IO  500 CLK_A>;
463                                                  rxd3  =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>;
464                                                  rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>;
465
466                                                  clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>;
467                                         };
468                                 };
469                         };
470                 };
471
472                 pin-controller-fvdp-fe {
473                         #address-cells  = <1>;
474                         #size-cells     = <1>;
475                         compatible      = "st,stih416-fvdp-fe-pinctrl";
476                         st,syscfg       = <&syscfg_fvdp_fe>;
477                         reg             = <0xfd6bf080 0x4>;
478                         reg-names       = "irqmux";
479                         interrupts      = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
480                         interrupt-names = "irqmux";
481                         ranges          = <0 0xfd6b0000 0x3000>;
482
483                         PIO100: gpio@fd6b0000 {
484                                 gpio-controller;
485                                 #gpio-cells     = <1>;
486                                 interrupt-controller;
487                                 #interrupt-cells = <2>;
488                                 reg             = <0 0x100>;
489                                 st,bank-name    = "PIO100";
490                         };
491                         PIO101: gpio@fd6b1000 {
492                                 gpio-controller;
493                                 #gpio-cells     = <1>;
494                                 interrupt-controller;
495                                 #interrupt-cells = <2>;
496                                 reg             = <0x1000 0x100>;
497                                 st,bank-name    = "PIO101";
498                         };
499                         PIO102: gpio@fd6b2000 {
500                                 gpio-controller;
501                                 #gpio-cells     = <1>;
502                                 interrupt-controller;
503                                 #interrupt-cells = <2>;
504                                 reg             = <0x2000 0x100>;
505                                 st,bank-name    = "PIO102";
506                         };
507                 };
508
509                 pin-controller-fvdp-lite {
510                         #address-cells  = <1>;
511                         #size-cells     = <1>;
512                         compatible      = "st,stih416-fvdp-lite-pinctrl";
513                         st,syscfg               = <&syscfg_fvdp_lite>;
514                         reg             = <0xfd33f080 0x4>;
515                         reg-names       = "irqmux";
516                         interrupts      = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
517                         interrupt-names = "irqmux";
518                         ranges                  = <0 0xfd330000 0x5000>;
519
520                         PIO103: gpio@fd330000 {
521                                 gpio-controller;
522                                 #gpio-cells     = <1>;
523                                 interrupt-controller;
524                                 #interrupt-cells = <2>;
525                                 reg             = <0 0x100>;
526                                 st,bank-name    = "PIO103";
527                         };
528                         PIO104: gpio@fd331000 {
529                                 gpio-controller;
530                                 #gpio-cells     = <1>;
531                                 interrupt-controller;
532                                 #interrupt-cells = <2>;
533                                 reg             = <0x1000 0x100>;
534                                 st,bank-name    = "PIO104";
535                         };
536                         PIO105: gpio@fd332000 {
537                                 gpio-controller;
538                                 #gpio-cells     = <1>;
539                                 interrupt-controller;
540                                 #interrupt-cells = <2>;
541                                 reg             = <0x2000 0x100>;
542                                 st,bank-name    = "PIO105";
543                         };
544                         PIO106: gpio@fd333000 {
545                                 gpio-controller;
546                                 #gpio-cells     = <1>;
547                                 interrupt-controller;
548                                 #interrupt-cells = <2>;
549                                 reg             = <0x3000 0x100>;
550                                 st,bank-name    = "PIO106";
551                         };
552
553                         PIO107: gpio@fd334000 {
554                                 gpio-controller;
555                                 #gpio-cells     = <1>;
556                                 interrupt-controller;
557                                 #interrupt-cells = <2>;
558                                 reg             = <0x4000 0x100>;
559                                 st,bank-name    = "PIO107";
560                                 st,retime-pin-mask = <0xf>;
561                         };
562                 };
563         };
564 };