arch/arm/boot/dts/stih410.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2014 STMicroelectronics Limited.
   4  * Author: Peter Griffin <peter.griffin@linaro.org>
   5  */
   6 #include "stih410-clock.dtsi"
   7 #include "stih407-family.dtsi"
   8 #include "stih410-pinctrl.dtsi"
   9 #include <dt-bindings/gpio/gpio.h>
  10 / {
  11         aliases {
  12                 bdisp0 = &bdisp0;
  13         };
  14
  15         usb2_picophy1: phy2 {
  16                 compatible = "st,stih407-usb2-phy";
  17                 #phy-cells = <0>;
  18                 st,syscfg = <&syscfg_core 0xf8 0xf4>;
  19                 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  20                          <&picophyreset STIH407_PICOPHY0_RESET>;
  21                 reset-names = "global", "port";
  22
  23                 status = "disabled";
  24         };
  25
  26         usb2_picophy2: phy3 {
  27                 compatible = "st,stih407-usb2-phy";
  28                 #phy-cells = <0>;
  29                 st,syscfg = <&syscfg_core 0xfc 0xf4>;
  30                 resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
  31                          <&picophyreset STIH407_PICOPHY1_RESET>;
  32                 reset-names = "global", "port";
  33
  34                 status = "disabled";
  35         };
  36
  37         soc {
  38                 ohci0: usb@9a03c00 {
  39                         compatible = "st,st-ohci-300x";
  40                         reg = <0x9a03c00 0x100>;
  41                         interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  42                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  43                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  44                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  45                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  46                         reset-names = "power", "softreset";
  47                         phys = <&usb2_picophy1>;
  48                         phy-names = "usb";
  49
  50                         status = "disabled";
  51                 };
  52
  53                 ehci0: usb@9a03e00 {
  54                         compatible = "st,st-ehci-300x";
  55                         reg = <0x9a03e00 0x100>;
  56                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
  57                         pinctrl-names = "default";
  58                         pinctrl-0 = <&pinctrl_usb0>;
  59                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  60                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  61                         resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
  62                                  <&softreset STIH407_USB2_PORT0_SOFTRESET>;
  63                         reset-names = "power", "softreset";
  64                         phys = <&usb2_picophy1>;
  65                         phy-names = "usb";
  66
  67                         status = "disabled";
  68                 };
  69
  70                 ohci1: usb@9a83c00 {
  71                         compatible = "st,st-ohci-300x";
  72                         reg = <0x9a83c00 0x100>;
  73                         interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
  74                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  75                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  76                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  77                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  78                         reset-names = "power", "softreset";
  79                         phys = <&usb2_picophy2>;
  80                         phy-names = "usb";
  81
  82                         status = "disabled";
  83                 };
  84
  85                 ehci1: usb@9a83e00 {
  86                         compatible = "st,st-ehci-300x";
  87                         reg = <0x9a83e00 0x100>;
  88                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
  89                         pinctrl-names = "default";
  90                         pinctrl-0 = <&pinctrl_usb1>;
  91                         clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>,
  92                                  <&clk_s_c0_flexgen CLK_RX_ICN_DISP_0>;
  93                         resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
  94                                  <&softreset STIH407_USB2_PORT1_SOFTRESET>;
  95                         reset-names = "power", "softreset";
  96                         phys = <&usb2_picophy2>;
  97                         phy-names = "usb";
  98
  99                         status = "disabled";
 100                 };
 101
 102                 sti-display-subsystem@0 {
 103                         compatible = "st,sti-display-subsystem";
 104                         #address-cells = <1>;
 105                         #size-cells = <1>;
 106
 107                         reg = <0 0>;
 108                         assigned-clocks = <&clk_s_d2_quadfs 0>,
 109                                           <&clk_s_d2_quadfs 1>,
 110                                           <&clk_s_c0_pll1 0>,
 111                                           <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 112                                           <&clk_s_c0_flexgen CLK_MAIN_DISP>,
 113                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 114                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 115                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 116                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 117                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 118                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
 119
 120                         assigned-clock-parents = <0>,
 121                                                  <0>,
 122                                                  <0>,
 123                                                  <&clk_s_c0_pll1 0>,
 124                                                  <&clk_s_c0_pll1 0>,
 125                                                  <&clk_s_d2_quadfs 0>,
 126                                                  <&clk_s_d2_quadfs 1>,
 127                                                  <&clk_s_d2_quadfs 0>,
 128                                                  <&clk_s_d2_quadfs 0>,
 129                                                  <&clk_s_d2_quadfs 0>,
 130                                                  <&clk_s_d2_quadfs 0>;
 131
 132                         assigned-clock-rates = <297000000>,
 133                                                <297000000>,
 134                                                <0>,
 135                                                <400000000>,
 136                                                <400000000>;
 137
 138                         ranges;
 139
 140                         sti-compositor@9d11000 {
 141                                 compatible = "st,stih407-compositor";
 142                                 reg = <0x9d11000 0x1000>;
 143
 144                                 clock-names = "compo_main",
 145                                               "compo_aux",
 146                                               "pix_main",
 147                                               "pix_aux",
 148                                               "pix_gdp1",
 149                                               "pix_gdp2",
 150                                               "pix_gdp3",
 151                                               "pix_gdp4",
 152                                               "main_parent",
 153                                               "aux_parent";
 154
 155                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 156                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
 157                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
 158                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
 159                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
 160                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
 161                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
 162                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
 163                                          <&clk_s_d2_quadfs 0>,
 164                                          <&clk_s_d2_quadfs 1>;
 165
 166                                 reset-names = "compo-main", "compo-aux";
 167                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
 168                                          <&softreset STIH407_COMPO_SOFTRESET>;
 169                                 st,vtg = <&vtg_main>, <&vtg_aux>;
 170                         };
 171
 172                         sti-tvout@8d08000 {
 173                                 compatible = "st,stih407-tvout";
 174                                 reg = <0x8d08000 0x1000>;
 175                                 reg-names = "tvout-reg";
 176                                 reset-names = "tvout";
 177                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
 178                                 #address-cells = <1>;
 179                                 #size-cells = <1>;
 180                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 181                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 182                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 183                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
 184                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 185                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
 186
 187                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
 188                                                          <&clk_tmdsout_hdmi>,
 189                                                          <&clk_s_d2_quadfs 0>,
 190                                                          <&clk_s_d0_quadfs 0>,
 191                                                          <&clk_s_d2_quadfs 0>,
 192                                                          <&clk_s_d2_quadfs 0>;
 193                         };
 194
 195                         sti_hdmi: sti-hdmi@8d04000 {
 196                                 compatible = "st,stih407-hdmi";
 197                                 reg = <0x8d04000 0x1000>;
 198                                 reg-names = "hdmi-reg";
 199                                 #sound-dai-cells = <0>;
 200                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 201                                 interrupt-names = "irq";
 202                                 clock-names = "pix",
 203                                               "tmds",
 204                                               "phy",
 205                                               "audio",
 206                                               "main_parent",
 207                                               "aux_parent";
 208
 209                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 210                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 211                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 212                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 213                                          <&clk_s_d2_quadfs 0>,
 214                                          <&clk_s_d2_quadfs 1>;
 215
 216                                 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
 217                                 reset-names = "hdmi";
 218                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 219                                 ddc = <&hdmiddc>;
 220                         };
 221
 222                         sti-hda@8d02000 {
 223                                 compatible = "st,stih407-hda";
 224                                 status = "disabled";
 225                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 226                                 reg-names = "hda-reg", "video-dacs-ctrl";
 227                                 clock-names = "pix",
 228                                               "hddac",
 229                                               "main_parent",
 230                                               "aux_parent";
 231                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 232                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 233                                          <&clk_s_d2_quadfs 0>,
 234                                          <&clk_s_d2_quadfs 1>;
 235                         };
 236
 237                         sti-hqvdp@9c00000 {
 238                                 compatible = "st,stih407-hqvdp";
 239                                 reg = <0x9C00000 0x100000>;
 240                                 clock-names = "hqvdp", "pix_main";
 241                                 clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
 242                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
 243                                 reset-names = "hqvdp";
 244                                 resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
 245                                 st,vtg = <&vtg_main>;
 246                         };
 247                 };
 248
 249                 bdisp0:bdisp@9f10000 {
 250                         compatible = "st,stih407-bdisp";
 251                         reg = <0x9f10000 0x1000>;
 252                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 253                         clock-names = "bdisp";
 254                         clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>;
 255                 };
 256
 257                 hva@8c85000 {
 258                         compatible = "st,st-hva";
 259                         reg = <0x8c85000 0x400>, <0x6000000 0x40000>;
 260                         reg-names = "hva_registers", "hva_esram";
 261                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 262                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 263                         clock-names = "clk_hva";
 264                         clocks = <&clk_s_c0_flexgen CLK_HVA>;
 265                 };
 266
 267                 thermal@91a0000 {
 268                         compatible = "st,stih407-thermal";
 269                         reg = <0x91a0000 0x28>;
 270                         clock-names = "thermal";
 271                         clocks = <&clk_sysin>;
 272                         interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>;
 273                 };
 274
 275                 sti-cec@94a087c {
 276                         compatible = "st,stih-cec";
 277                         reg = <0x94a087c 0x64>;
 278                         clocks = <&clk_sysin>;
 279                         clock-names = "cec-clk";
 280                         interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
 281                         interrupt-names = "cec-irq";
 282                         pinctrl-names = "default";
 283                         pinctrl-0 = <&pinctrl_cec0_default>;
 284                         resets = <&softreset STIH407_LPM_SOFTRESET>;
 285                         hdmi-phandle = <&sti_hdmi>;
 286                 };
 287         };
 288 };