2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include "skeleton.dtsi"
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
19 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
28 enable-method = "altr,socfpga-a10-smp";
31 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
37 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
48 reg = <0xffffd000 0x1000>,
55 compatible = "simple-bus";
57 interrupt-parent = <&intc>;
61 compatible = "simple-bus";
67 compatible = "arm,pl330", "arm,primecell";
68 reg = <0xffda1000 0x1000>;
69 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
70 <0 84 IRQ_TYPE_LEVEL_HIGH>,
71 <0 85 IRQ_TYPE_LEVEL_HIGH>,
72 <0 86 IRQ_TYPE_LEVEL_HIGH>,
73 <0 87 IRQ_TYPE_LEVEL_HIGH>,
74 <0 88 IRQ_TYPE_LEVEL_HIGH>,
75 <0 89 IRQ_TYPE_LEVEL_HIGH>,
76 <0 90 IRQ_TYPE_LEVEL_HIGH>,
77 <0 91 IRQ_TYPE_LEVEL_HIGH>;
81 clocks = <&l4_main_clk>;
82 clock-names = "apb_pclk";
87 compatible = "altr,clk-mgr";
88 reg = <0xffd04000 0x1000>;
94 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
96 compatible = "fixed-clock";
99 cb_intosc_ls_clk: cb_intosc_ls_clk {
101 compatible = "fixed-clock";
104 f2s_free_clk: f2s_free_clk {
106 compatible = "fixed-clock";
111 compatible = "fixed-clock";
115 #address-cells = <1>;
118 compatible = "altr,socfpga-a10-pll-clock";
119 clocks = <&osc1>, <&cb_intosc_ls_clk>,
123 main_mpu_base_clk: main_mpu_base_clk {
125 compatible = "altr,socfpga-a10-perip-clk";
126 clocks = <&main_pll>;
127 div-reg = <0x140 0 11>;
130 main_noc_base_clk: main_noc_base_clk {
132 compatible = "altr,socfpga-a10-perip-clk";
133 clocks = <&main_pll>;
134 div-reg = <0x144 0 11>;
137 main_emaca_clk: main_emaca_clk {
139 compatible = "altr,socfpga-a10-perip-clk";
140 clocks = <&main_pll>;
144 main_emacb_clk: main_emacb_clk {
146 compatible = "altr,socfpga-a10-perip-clk";
147 clocks = <&main_pll>;
151 main_emac_ptp_clk: main_emac_ptp_clk {
153 compatible = "altr,socfpga-a10-perip-clk";
154 clocks = <&main_pll>;
158 main_gpio_db_clk: main_gpio_db_clk {
160 compatible = "altr,socfpga-a10-perip-clk";
161 clocks = <&main_pll>;
165 main_sdmmc_clk: main_sdmmc_clk {
167 compatible = "altr,socfpga-a10-perip-clk"
169 clocks = <&main_pll>;
173 main_s2f_usr0_clk: main_s2f_usr0_clk {
175 compatible = "altr,socfpga-a10-perip-clk";
176 clocks = <&main_pll>;
180 main_s2f_usr1_clk: main_s2f_usr1_clk {
182 compatible = "altr,socfpga-a10-perip-clk";
183 clocks = <&main_pll>;
187 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
189 compatible = "altr,socfpga-a10-perip-clk";
190 clocks = <&main_pll>;
194 main_periph_ref_clk: main_periph_ref_clk {
196 compatible = "altr,socfpga-a10-perip-clk";
197 clocks = <&main_pll>;
202 periph_pll: periph_pll {
203 #address-cells = <1>;
206 compatible = "altr,socfpga-a10-pll-clock";
207 clocks = <&osc1>, <&cb_intosc_ls_clk>,
208 <&f2s_free_clk>, <&main_periph_ref_clk>;
211 peri_mpu_base_clk: peri_mpu_base_clk {
213 compatible = "altr,socfpga-a10-perip-clk";
214 clocks = <&periph_pll>;
215 div-reg = <0x140 16 11>;
218 peri_noc_base_clk: peri_noc_base_clk {
220 compatible = "altr,socfpga-a10-perip-clk";
221 clocks = <&periph_pll>;
222 div-reg = <0x144 16 11>;
225 peri_emaca_clk: peri_emaca_clk {
227 compatible = "altr,socfpga-a10-perip-clk";
228 clocks = <&periph_pll>;
232 peri_emacb_clk: peri_emacb_clk {
234 compatible = "altr,socfpga-a10-perip-clk";
235 clocks = <&periph_pll>;
239 peri_emac_ptp_clk: peri_emac_ptp_clk {
241 compatible = "altr,socfpga-a10-perip-clk";
242 clocks = <&periph_pll>;
246 peri_gpio_db_clk: peri_gpio_db_clk {
248 compatible = "altr,socfpga-a10-perip-clk";
249 clocks = <&periph_pll>;
253 peri_sdmmc_clk: peri_sdmmc_clk {
255 compatible = "altr,socfpga-a10-perip-clk";
256 clocks = <&periph_pll>;
260 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
262 compatible = "altr,socfpga-a10-perip-clk";
263 clocks = <&periph_pll>;
267 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
269 compatible = "altr,socfpga-a10-perip-clk";
270 clocks = <&periph_pll>;
274 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
276 compatible = "altr,socfpga-a10-perip-clk";
277 clocks = <&periph_pll>;
282 mpu_free_clk: mpu_free_clk {
284 compatible = "altr,socfpga-a10-perip-clk";
285 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
286 <&osc1>, <&cb_intosc_hs_div2_clk>,
291 noc_free_clk: noc_free_clk {
293 compatible = "altr,socfpga-a10-perip-clk";
294 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
295 <&osc1>, <&cb_intosc_hs_div2_clk>,
300 s2f_user1_free_clk: s2f_user1_free_clk {
302 compatible = "altr,socfpga-a10-perip-clk";
303 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
304 <&osc1>, <&cb_intosc_hs_div2_clk>,
309 sdmmc_free_clk: sdmmc_free_clk {
311 compatible = "altr,socfpga-a10-perip-clk";
312 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
313 <&osc1>, <&cb_intosc_hs_div2_clk>,
319 l4_sys_free_clk: l4_sys_free_clk {
321 compatible = "altr,socfpga-a10-perip-clk";
322 clocks = <&noc_free_clk>;
326 l4_main_clk: l4_main_clk {
328 compatible = "altr,socfpga-a10-gate-clk";
329 clocks = <&noc_free_clk>;
330 div-reg = <0xA8 0 2>;
334 l4_mp_clk: l4_mp_clk {
336 compatible = "altr,socfpga-a10-gate-clk";
337 clocks = <&noc_free_clk>;
338 div-reg = <0xA8 8 2>;
342 l4_sp_clk: l4_sp_clk {
344 compatible = "altr,socfpga-a10-gate-clk";
345 clocks = <&noc_free_clk>;
346 div-reg = <0xA8 16 2>;
350 mpu_periph_clk: mpu_periph_clk {
352 compatible = "altr,socfpga-a10-gate-clk";
353 clocks = <&mpu_free_clk>;
358 sdmmc_clk: sdmmc_clk {
360 compatible = "altr,socfpga-a10-gate-clk";
361 clocks = <&sdmmc_free_clk>;
368 compatible = "altr,socfpga-a10-gate-clk";
369 clocks = <&l4_main_clk>;
370 clk-gate = <0xC8 11>;
375 compatible = "altr,socfpga-a10-gate-clk";
376 clocks = <&l4_mp_clk>;
377 clk-gate = <0xC8 10>;
380 spi_m_clk: spi_m_clk {
382 compatible = "altr,socfpga-a10-gate-clk";
383 clocks = <&l4_main_clk>;
389 compatible = "altr,socfpga-a10-gate-clk";
390 clocks = <&l4_mp_clk>;
394 s2f_usr1_clk: s2f_usr1_clk {
396 compatible = "altr,socfpga-a10-gate-clk";
397 clocks = <&peri_s2f_usr1_clk>;
403 gmac0: ethernet@ff800000 {
404 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
405 altr,sysmgr-syscon = <&sysmgr 0x44 0>;
406 reg = <0xff800000 0x2000>;
407 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
408 interrupt-names = "macirq";
409 /* Filled in by bootloader */
410 mac-address = [00 00 00 00 00 00];
411 snps,multicast-filter-bins = <256>;
412 snps,perfect-filter-entries = <128>;
413 tx-fifo-depth = <4096>;
414 rx-fifo-depth = <16384>;
415 clocks = <&l4_mp_clk>;
416 clock-names = "stmmaceth";
417 resets = <&rst EMAC0_RESET>;
418 reset-names = "stmmaceth";
422 gmac1: ethernet@ff802000 {
423 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
424 altr,sysmgr-syscon = <&sysmgr 0x48 0>;
425 reg = <0xff802000 0x2000>;
426 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "macirq";
428 /* Filled in by bootloader */
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
434 clocks = <&l4_mp_clk>;
435 clock-names = "stmmaceth";
436 resets = <&rst EMAC1_RESET>;
437 reset-names = "stmmaceth";
441 gmac2: ethernet@ff804000 {
442 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
443 altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
444 reg = <0xff804000 0x2000>;
445 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
446 interrupt-names = "macirq";
447 /* Filled in by bootloader */
448 mac-address = [00 00 00 00 00 00];
449 snps,multicast-filter-bins = <256>;
450 snps,perfect-filter-entries = <128>;
451 tx-fifo-depth = <4096>;
452 rx-fifo-depth = <16384>;
453 clocks = <&l4_mp_clk>;
454 clock-names = "stmmaceth";
458 gpio0: gpio@ffc02900 {
459 #address-cells = <1>;
461 compatible = "snps,dw-apb-gpio";
462 reg = <0xffc02900 0x100>;
465 porta: gpio-controller@0 {
466 compatible = "snps,dw-apb-gpio-port";
469 snps,nr-gpios = <29>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
477 gpio1: gpio@ffc02a00 {
478 #address-cells = <1>;
480 compatible = "snps,dw-apb-gpio";
481 reg = <0xffc02a00 0x100>;
484 portb: gpio-controller@0 {
485 compatible = "snps,dw-apb-gpio-port";
488 snps,nr-gpios = <29>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
496 gpio2: gpio@ffc02b00 {
497 #address-cells = <1>;
499 compatible = "snps,dw-apb-gpio";
500 reg = <0xffc02b00 0x100>;
503 portc: gpio-controller@0 {
504 compatible = "snps,dw-apb-gpio-port";
507 snps,nr-gpios = <27>;
509 interrupt-controller;
510 #interrupt-cells = <2>;
511 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
518 compatible = "snps,designware-i2c";
519 reg = <0xffc02200 0x100>;
520 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&l4_sp_clk>;
526 #address-cells = <1>;
528 compatible = "snps,designware-i2c";
529 reg = <0xffc02300 0x100>;
530 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&l4_sp_clk>;
536 #address-cells = <1>;
538 compatible = "snps,designware-i2c";
539 reg = <0xffc02400 0x100>;
540 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
541 clocks = <&l4_sp_clk>;
546 #address-cells = <1>;
548 compatible = "snps,designware-i2c";
549 reg = <0xffc02500 0x100>;
550 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&l4_sp_clk>;
556 #address-cells = <1>;
558 compatible = "snps,designware-i2c";
559 reg = <0xffc02600 0x100>;
560 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&l4_sp_clk>;
566 compatible = "snps,dw-apb-ssi";
567 #address-cells = <1>;
569 reg = <0xffda5000 0x100>;
570 interrupts = <0 102 4>;
571 num-chipselect = <4>;
574 tx-dma-channel = <&pdma 16>;
575 rx-dma-channel = <&pdma 17>;
576 clocks = <&spi_m_clk>;
581 compatible = "syscon";
582 reg = <0xffcfb100 0x80>;
585 L2: l2-cache@fffff000 {
586 compatible = "arm,pl310-cache";
587 reg = <0xfffff000 0x1000>;
588 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
592 prefetch-instr = <1>;
596 mmc: dwmmc0@ff808000 {
597 #address-cells = <1>;
599 compatible = "altr,socfpga-dw-mshc";
600 reg = <0xff808000 0x1000>;
601 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
602 fifo-depth = <0x400>;
603 clocks = <&l4_mp_clk>, <&sdmmc_clk>;
604 clock-names = "biu", "ciu";
608 ocram: sram@ffe00000 {
609 compatible = "mmio-sram";
610 reg = <0xffe00000 0x40000>;
613 eccmgr: eccmgr@ffd06000 {
614 compatible = "altr,socfpga-a10-ecc-manager";
615 altr,sysmgr-syscon = <&sysmgr>;
616 #address-cells = <1>;
618 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
619 <0 0 IRQ_TYPE_LEVEL_HIGH>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
625 compatible = "altr,sdram-edac-a10";
626 altr,sdr-syscon = <&sdr>;
627 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
628 <49 IRQ_TYPE_LEVEL_HIGH>;
632 compatible = "altr,socfpga-a10-l2-ecc";
633 reg = <0xffd06010 0x4>;
634 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
635 <32 IRQ_TYPE_LEVEL_HIGH>;
639 compatible = "altr,socfpga-a10-ocram-ecc";
640 reg = <0xff8c3000 0x400>;
641 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
642 <33 IRQ_TYPE_LEVEL_HIGH>;
645 emac0-rx-ecc@ff8c0800 {
646 compatible = "altr,socfpga-eth-mac-ecc";
647 reg = <0xff8c0800 0x400>;
648 altr,ecc-parent = <&gmac0>;
649 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
650 <36 IRQ_TYPE_LEVEL_HIGH>;
653 emac0-tx-ecc@ff8c0c00 {
654 compatible = "altr,socfpga-eth-mac-ecc";
655 reg = <0xff8c0c00 0x400>;
656 altr,ecc-parent = <&gmac0>;
657 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
658 <37 IRQ_TYPE_LEVEL_HIGH>;
662 compatible = "altr,socfpga-dma-ecc";
663 reg = <0xff8c8000 0x400>;
664 altr,ecc-parent = <&pdma>;
665 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
666 <42 IRQ_TYPE_LEVEL_HIGH>;
670 compatible = "altr,socfpga-usb-ecc";
671 reg = <0xff8c8800 0x400>;
672 altr,ecc-parent = <&usb0>;
673 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
674 <34 IRQ_TYPE_LEVEL_HIGH>;
679 compatible = "cdns,qspi-nor";
680 #address-cells = <1>;
682 reg = <0xff809000 0x100>,
683 <0xffa00000 0x100000>;
684 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
685 cdns,fifo-depth = <128>;
686 cdns,fifo-width = <4>;
687 cdns,trigger-address = <0x00000000>;
688 clocks = <&qspi_clk>;
692 rst: rstmgr@ffd05000 {
694 compatible = "altr,rst-mgr";
695 reg = <0xffd05000 0x100>;
696 altr,modrst-offset = <0x20>;
699 scu: snoop-control-unit@ffffc000 {
700 compatible = "arm,cortex-a9-scu";
701 reg = <0xffffc000 0x100>;
704 sysmgr: sysmgr@ffd06000 {
705 compatible = "altr,sys-mgr", "syscon";
706 reg = <0xffd06000 0x300>;
707 cpu1-start-addr = <0xffd06230>;
712 compatible = "arm,cortex-a9-twd-timer";
713 reg = <0xffffc600 0x100>;
714 interrupts = <1 13 0xf04>;
715 clocks = <&mpu_periph_clk>;
718 timer0: timer0@ffc02700 {
719 compatible = "snps,dw-apb-timer";
720 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
721 reg = <0xffc02700 0x100>;
722 clocks = <&l4_sp_clk>;
723 clock-names = "timer";
726 timer1: timer1@ffc02800 {
727 compatible = "snps,dw-apb-timer";
728 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
729 reg = <0xffc02800 0x100>;
730 clocks = <&l4_sp_clk>;
731 clock-names = "timer";
734 timer2: timer2@ffd00000 {
735 compatible = "snps,dw-apb-timer";
736 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
737 reg = <0xffd00000 0x100>;
738 clocks = <&l4_sys_free_clk>;
739 clock-names = "timer";
742 timer3: timer3@ffd00100 {
743 compatible = "snps,dw-apb-timer";
744 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
745 reg = <0xffd01000 0x100>;
746 clocks = <&l4_sys_free_clk>;
747 clock-names = "timer";
750 uart0: serial0@ffc02000 {
751 compatible = "snps,dw-apb-uart";
752 reg = <0xffc02000 0x100>;
753 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&l4_sp_clk>;
760 uart1: serial1@ffc02100 {
761 compatible = "snps,dw-apb-uart";
762 reg = <0xffc02100 0x100>;
763 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&l4_sp_clk>;
772 compatible = "usb-nop-xceiv";
777 compatible = "snps,dwc2";
778 reg = <0xffb00000 0xffff>;
779 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
782 resets = <&rst USB0_RESET>;
783 reset-names = "dwc2";
785 phy-names = "usb2-phy";
790 compatible = "snps,dwc2";
791 reg = <0xffb40000 0xffff>;
792 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
795 resets = <&rst USB1_RESET>;
796 reset-names = "dwc2";
798 phy-names = "usb2-phy";
802 watchdog0: watchdog@ffd00200 {
803 compatible = "snps,dw-wdt";
804 reg = <0xffd00200 0x100>;
805 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&l4_sys_free_clk>;
810 watchdog1: watchdog@ffd00300 {
811 compatible = "snps,dw-wdt";
812 reg = <0xffd00300 0x100>;
813 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&l4_sys_free_clk>;