arch/arm/boot/dts/sh73a0.dtsi

   1 /*
   2  * Device Tree Source for the SH73A0 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/sh73a0-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,sh73a0";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <0>;
  29                         clock-frequency = <1196000000>;
  30                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
  31                         power-domains = <&pd_a2sl>;
  32                         next-level-cache = <&L2>;
  33                 };
  34                 cpu@1 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a9";
  37                         reg = <1>;
  38                         clock-frequency = <1196000000>;
  39                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
  40                         power-domains = <&pd_a2sl>;
  41                         next-level-cache = <&L2>;
  42                 };
  43         };
  44
  45         timer@f0000600 {
  46                 compatible = "arm,cortex-a9-twd-timer";
  47                 reg = <0xf0000600 0x20>;
  48                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
  49                 clocks = <&twd_clk>;
  50         };
  51
  52         gic: interrupt-controller@f0001000 {
  53                 compatible = "arm,cortex-a9-gic";
  54                 #interrupt-cells = <3>;
  55                 interrupt-controller;
  56                 reg = <0xf0001000 0x1000>,
  57                       <0xf0000100 0x100>;
  58         };
  59
  60         L2: cache-controller@f0100000 {
  61                 compatible = "arm,pl310-cache";
  62                 reg = <0xf0100000 0x1000>;
  63                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  64                 power-domains = <&pd_a3sm>;
  65                 arm,data-latency = <3 3 3>;
  66                 arm,tag-latency = <2 2 2>;
  67                 arm,shared-override;
  68                 cache-unified;
  69                 cache-level = <2>;
  70         };
  71
  72         sbsc2: memory-controller@fb400000 {
  73                 compatible = "renesas,sbsc-sh73a0";
  74                 reg = <0xfb400000 0x400>;
  75                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  77                 interrupt-names = "sec", "temp";
  78                 power-domains = <&pd_a4bc1>;
  79         };
  80
  81         sbsc1: memory-controller@fe400000 {
  82                 compatible = "renesas,sbsc-sh73a0";
  83                 reg = <0xfe400000 0x400>;
  84                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  86                 interrupt-names = "sec", "temp";
  87                 power-domains = <&pd_a4bc0>;
  88         };
  89
  90         pmu {
  91                 compatible = "arm,cortex-a9-pmu";
  92                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  93                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  94         };
  95
  96         cmt1: timer@e6138000 {
  97                 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
  98                 reg = <0xe6138000 0x200>;
  99                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 100                 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
 101                 clock-names = "fck";
 102                 power-domains = <&pd_c5>;
 103
 104                 renesas,channels-mask = <0x3f>;
 105
 106                 status = "disabled";
 107         };
 108
 109         irqpin0: interrupt-controller@e6900000 {
 110                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 111                 #interrupt-cells = <2>;
 112                 interrupt-controller;
 113                 reg = <0xe6900000 4>,
 114                         <0xe6900010 4>,
 115                         <0xe6900020 1>,
 116                         <0xe6900040 1>,
 117                         <0xe6900060 1>;
 118                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 119                               GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 120                               GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 121                               GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
 122                               GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
 123                               GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
 124                               GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
 125                               GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 126                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 127                 power-domains = <&pd_a4s>;
 128                 control-parent;
 129         };
 130
 131         irqpin1: interrupt-controller@e6900004 {
 132                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 133                 #interrupt-cells = <2>;
 134                 interrupt-controller;
 135                 reg = <0xe6900004 4>,
 136                         <0xe6900014 4>,
 137                         <0xe6900024 1>,
 138                         <0xe6900044 1>,
 139                         <0xe6900064 1>;
 140                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
 141                               GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
 142                               GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
 143                               GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
 144                               GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
 145                               GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
 146                               GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
 147                               GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 148                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 149                 power-domains = <&pd_a4s>;
 150                 control-parent;
 151         };
 152
 153         irqpin2: interrupt-controller@e6900008 {
 154                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 155                 #interrupt-cells = <2>;
 156                 interrupt-controller;
 157                 reg = <0xe6900008 4>,
 158                         <0xe6900018 4>,
 159                         <0xe6900028 1>,
 160                         <0xe6900048 1>,
 161                         <0xe6900068 1>;
 162                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
 163                               GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 164                               GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
 165                               GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
 166                               GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
 167                               GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
 168                               GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
 169                               GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 171                 power-domains = <&pd_a4s>;
 172                 control-parent;
 173         };
 174
 175         irqpin3: interrupt-controller@e690000c {
 176                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 177                 #interrupt-cells = <2>;
 178                 interrupt-controller;
 179                 reg = <0xe690000c 4>,
 180                         <0xe690001c 4>,
 181                         <0xe690002c 1>,
 182                         <0xe690004c 1>,
 183                         <0xe690006c 1>;
 184                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
 185                               GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
 186                               GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
 187                               GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
 188                               GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
 189                               GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
 190                               GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
 191                               GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 193                 power-domains = <&pd_a4s>;
 194                 control-parent;
 195         };
 196
 197         i2c0: i2c@e6820000 {
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 201                 reg = <0xe6820000 0x425>;
 202                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
 203                               GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
 204                               GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
 205                               GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
 206                 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
 207                 power-domains = <&pd_a3sp>;
 208                 status = "disabled";
 209         };
 210
 211         i2c1: i2c@e6822000 {
 212                 #address-cells = <1>;
 213                 #size-cells = <0>;
 214                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 215                 reg = <0xe6822000 0x425>;
 216                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
 217                               GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
 218                               GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
 219                               GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
 221                 power-domains = <&pd_a3sp>;
 222                 status = "disabled";
 223         };
 224
 225         i2c2: i2c@e6824000 {
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 229                 reg = <0xe6824000 0x425>;
 230                 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
 231                               GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
 232                               GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
 233                               GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 234                 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
 235                 power-domains = <&pd_a3sp>;
 236                 status = "disabled";
 237         };
 238
 239         i2c3: i2c@e6826000 {
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 243                 reg = <0xe6826000 0x425>;
 244                 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
 245                               GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
 246                               GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
 247                               GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 248                 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
 249                 power-domains = <&pd_a3sp>;
 250                 status = "disabled";
 251         };
 252
 253         i2c4: i2c@e6828000 {
 254                 #address-cells = <1>;
 255                 #size-cells = <0>;
 256                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 257                 reg = <0xe6828000 0x425>;
 258                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
 259                               GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
 260                               GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
 261                               GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 262                 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
 263                 power-domains = <&pd_c5>;
 264                 status = "disabled";
 265         };
 266
 267         mmcif: mmc@e6bd0000 {
 268                 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
 269                 reg = <0xe6bd0000 0x100>;
 270                 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
 271                               GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
 272                 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
 273                 power-domains = <&pd_a3sp>;
 274                 reg-io-width = <4>;
 275                 status = "disabled";
 276         };
 277
 278         msiof0: spi@e6e20000 {
 279                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 280                 reg = <0xe6e20000 0x0064>;
 281                 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 282                 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
 283                 power-domains = <&pd_a3sp>;
 284                 #address-cells = <1>;
 285                 #size-cells = <0>;
 286                 status = "disabled";
 287         };
 288
 289         msiof1: spi@e6e10000 {
 290                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 291                 reg = <0xe6e10000 0x0064>;
 292                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 293                 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
 294                 power-domains = <&pd_a3sp>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 status = "disabled";
 298         };
 299
 300         msiof2: spi@e6e00000 {
 301                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 302                 reg = <0xe6e00000 0x0064>;
 303                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
 305                 power-domains = <&pd_a3sp>;
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308                 status = "disabled";
 309         };
 310
 311         msiof3: spi@e6c90000 {
 312                 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
 313                 reg = <0xe6c90000 0x0064>;
 314                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
 316                 power-domains = <&pd_a3sp>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319                 status = "disabled";
 320         };
 321
 322         sdhi0: sd@ee100000 {
 323                 compatible = "renesas,sdhi-sh73a0";
 324                 reg = <0xee100000 0x100>;
 325                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
 326                               GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
 327                               GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
 329                 power-domains = <&pd_a3sp>;
 330                 cap-sd-highspeed;
 331                 status = "disabled";
 332         };
 333
 334         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
 335         sdhi1: sd@ee120000 {
 336                 compatible = "renesas,sdhi-sh73a0";
 337                 reg = <0xee120000 0x100>;
 338                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
 339                               GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
 341                 power-domains = <&pd_a3sp>;
 342                 toshiba,mmc-wrprotect-disable;
 343                 cap-sd-highspeed;
 344                 status = "disabled";
 345         };
 346
 347         sdhi2: sd@ee140000 {
 348                 compatible = "renesas,sdhi-sh73a0";
 349                 reg = <0xee140000 0x100>;
 350                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
 351                               GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
 353                 power-domains = <&pd_a3sp>;
 354                 toshiba,mmc-wrprotect-disable;
 355                 cap-sd-highspeed;
 356                 status = "disabled";
 357         };
 358
 359         scifa0: serial@e6c40000 {
 360                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 361                 reg = <0xe6c40000 0x100>;
 362                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
 364                 clock-names = "fck";
 365                 power-domains = <&pd_a3sp>;
 366                 status = "disabled";
 367         };
 368
 369         scifa1: serial@e6c50000 {
 370                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 371                 reg = <0xe6c50000 0x100>;
 372                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
 374                 clock-names = "fck";
 375                 power-domains = <&pd_a3sp>;
 376                 status = "disabled";
 377         };
 378
 379         scifa2: serial@e6c60000 {
 380                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 381                 reg = <0xe6c60000 0x100>;
 382                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
 384                 clock-names = "fck";
 385                 power-domains = <&pd_a3sp>;
 386                 status = "disabled";
 387         };
 388
 389         scifa3: serial@e6c70000 {
 390                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 391                 reg = <0xe6c70000 0x100>;
 392                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
 394                 clock-names = "fck";
 395                 power-domains = <&pd_a3sp>;
 396                 status = "disabled";
 397         };
 398
 399         scifa4: serial@e6c80000 {
 400                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 401                 reg = <0xe6c80000 0x100>;
 402                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 403                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
 404                 clock-names = "fck";
 405                 power-domains = <&pd_a3sp>;
 406                 status = "disabled";
 407         };
 408
 409         scifa5: serial@e6cb0000 {
 410                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 411                 reg = <0xe6cb0000 0x100>;
 412                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
 414                 clock-names = "fck";
 415                 power-domains = <&pd_a3sp>;
 416                 status = "disabled";
 417         };
 418
 419         scifa6: serial@e6cc0000 {
 420                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 421                 reg = <0xe6cc0000 0x100>;
 422                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 423                 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
 424                 clock-names = "fck";
 425                 power-domains = <&pd_a3sp>;
 426                 status = "disabled";
 427         };
 428
 429         scifa7: serial@e6cd0000 {
 430                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 431                 reg = <0xe6cd0000 0x100>;
 432                 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 433                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
 434                 clock-names = "fck";
 435                 power-domains = <&pd_a3sp>;
 436                 status = "disabled";
 437         };
 438
 439         scifb: serial@e6c30000 {
 440                 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
 441                 reg = <0xe6c30000 0x100>;
 442                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
 444                 clock-names = "fck";
 445                 power-domains = <&pd_a3sp>;
 446                 status = "disabled";
 447         };
 448
 449         pfc: pin-controller@e6050000 {
 450                 compatible = "renesas,pfc-sh73a0";
 451                 reg = <0xe6050000 0x8000>,
 452                       <0xe605801c 0x1c>;
 453                 gpio-controller;
 454                 #gpio-cells = <2>;
 455                 gpio-ranges =
 456                         <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
 457                         <&pfc 288 288 22>;
 458                 interrupts-extended =
 459                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 460                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 461                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 462                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 463                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 464                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 465                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 466                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 467                 power-domains = <&pd_c5>;
 468         };
 469
 470         sysc: system-controller@e6180000 {
 471                 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
 472                 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
 473
 474                 pm-domains {
 475                         pd_c5: c5 {
 476                                 #address-cells = <1>;
 477                                 #size-cells = <0>;
 478                                 #power-domain-cells = <0>;
 479
 480                                 pd_c4: c4@0 {
 481                                         reg = <0>;
 482                                         #power-domain-cells = <0>;
 483                                 };
 484
 485                                 pd_d4: d4@1 {
 486                                         reg = <1>;
 487                                         #power-domain-cells = <0>;
 488                                 };
 489
 490                                 pd_a4bc0: a4bc0@4 {
 491                                         reg = <4>;
 492                                         #power-domain-cells = <0>;
 493                                 };
 494
 495                                 pd_a4bc1: a4bc1@5 {
 496                                         reg = <5>;
 497                                         #power-domain-cells = <0>;
 498                                 };
 499
 500                                 pd_a4lc0: a4lc0@6 {
 501                                         reg = <6>;
 502                                         #power-domain-cells = <0>;
 503                                 };
 504
 505                                 pd_a4lc1: a4lc1@7 {
 506                                         reg = <7>;
 507                                         #power-domain-cells = <0>;
 508                                 };
 509
 510                                 pd_a4mp: a4mp@8 {
 511                                         reg = <8>;
 512                                         #address-cells = <1>;
 513                                         #size-cells = <0>;
 514                                         #power-domain-cells = <0>;
 515
 516                                         pd_a3mp: a3mp@9 {
 517                                                 reg = <9>;
 518                                                 #power-domain-cells = <0>;
 519                                         };
 520
 521                                         pd_a3vc: a3vc@10 {
 522                                                 reg = <10>;
 523                                                 #power-domain-cells = <0>;
 524                                         };
 525                                 };
 526
 527                                 pd_a4rm: a4rm@12 {
 528                                         reg = <12>;
 529                                         #address-cells = <1>;
 530                                         #size-cells = <0>;
 531                                         #power-domain-cells = <0>;
 532
 533                                         pd_a3r: a3r@13 {
 534                                                 reg = <13>;
 535                                                 #address-cells = <1>;
 536                                                 #size-cells = <0>;
 537                                                 #power-domain-cells = <0>;
 538
 539                                                 pd_a2rv: a2rv@14 {
 540                                                         reg = <14>;
 541                                                         #address-cells = <1>;
 542                                                         #size-cells = <0>;
 543                                                         #power-domain-cells = <0>;
 544                                                 };
 545                                         };
 546                                 };
 547
 548                                 pd_a4s: a4s@16 {
 549                                         reg = <16>;
 550                                         #address-cells = <1>;
 551                                         #size-cells = <0>;
 552                                         #power-domain-cells = <0>;
 553
 554                                         pd_a3sp: a3sp@17 {
 555                                                 reg = <17>;
 556                                                 #power-domain-cells = <0>;
 557                                         };
 558
 559                                         pd_a3sg: a3sg@18 {
 560                                                 reg = <18>;
 561                                                 #power-domain-cells = <0>;
 562                                         };
 563
 564                                         pd_a3sm: a3sm@19 {
 565                                                 reg = <19>;
 566                                                 #address-cells = <1>;
 567                                                 #size-cells = <0>;
 568                                                 #power-domain-cells = <0>;
 569
 570                                                 pd_a2sl: a2sl@20 {
 571                                                         reg = <20>;
 572                                                         #power-domain-cells = <0>;
 573                                                 };
 574                                         };
 575                                 };
 576                         };
 577                 };
 578         };
 579
 580         sh_fsi2: sound@ec230000 {
 581                 #sound-dai-cells = <1>;
 582                 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
 583                 reg = <0xec230000 0x400>;
 584                 interrupts = <GIC_SPI 146 0x4>;
 585                 power-domains = <&pd_a4mp>;
 586                 status = "disabled";
 587         };
 588
 589         bsc: bus@fec10000 {
 590                 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
 591                              "simple-pm-bus";
 592                 #address-cells = <1>;
 593                 #size-cells = <1>;
 594                 ranges = <0 0 0x20000000>;
 595                 reg = <0xfec10000 0x400>;
 596                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 597                 clocks = <&zb_clk>;
 598                 power-domains = <&pd_a4s>;
 599         };
 600
 601         clocks {
 602                 #address-cells = <1>;
 603                 #size-cells = <1>;
 604                 ranges;
 605
 606                 /* External root clocks */
 607                 extalr_clk: extalr {
 608                         compatible = "fixed-clock";
 609                         #clock-cells = <0>;
 610                         clock-frequency = <32768>;
 611                 };
 612                 extal1_clk: extal1 {
 613                         compatible = "fixed-clock";
 614                         #clock-cells = <0>;
 615                         clock-frequency = <26000000>;
 616                 };
 617                 extal2_clk: extal2 {
 618                         compatible = "fixed-clock";
 619                         #clock-cells = <0>;
 620                 };
 621                 extcki_clk: extcki {
 622                         compatible = "fixed-clock";
 623                         #clock-cells = <0>;
 624                 };
 625                 fsiack_clk: fsiack {
 626                         compatible = "fixed-clock";
 627                         #clock-cells = <0>;
 628                         clock-frequency = <0>;
 629                 };
 630                 fsibck_clk: fsibck {
 631                         compatible = "fixed-clock";
 632                         #clock-cells = <0>;
 633                         clock-frequency = <0>;
 634                 };
 635
 636                 /* Special CPG clocks */
 637                 cpg_clocks: cpg_clocks@e6150000 {
 638                         compatible = "renesas,sh73a0-cpg-clocks";
 639                         reg = <0xe6150000 0x10000>;
 640                         clocks = <&extal1_clk>, <&extal2_clk>;
 641                         #clock-cells = <1>;
 642                         clock-output-names = "main", "pll0", "pll1", "pll2",
 643                                              "pll3", "dsi0phy", "dsi1phy",
 644                                              "zg", "m3", "b", "m1", "m2",
 645                                              "z", "zx", "hp";
 646                 };
 647
 648                 /* Variable factor clocks (DIV6) */
 649                 vclk1_clk: vclk1@e6150008 {
 650                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 651                         reg = <0xe6150008 4>;
 652                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 653                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 654                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 655                                  <0>;
 656                         #clock-cells = <0>;
 657                 };
 658                 vclk2_clk: vclk2@e615000c {
 659                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 660                         reg = <0xe615000c 4>;
 661                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 662                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 663                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 664                                  <0>;
 665                         #clock-cells = <0>;
 666                 };
 667                 vclk3_clk: vclk3@e615001c {
 668                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 669                         reg = <0xe615001c 4>;
 670                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 671                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 672                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 673                                  <0>;
 674                         #clock-cells = <0>;
 675                 };
 676                 zb_clk: zb_clk@e6150010 {
 677                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 678                         reg = <0xe6150010 4>;
 679                         clocks = <&pll1_div2_clk>, <0>,
 680                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 681                         #clock-cells = <0>;
 682                         clock-output-names = "zb";
 683                 };
 684                 flctl_clk: flctlck@e6150014 {
 685                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 686                         reg = <0xe6150014 4>;
 687                         clocks = <&pll1_div2_clk>, <0>,
 688                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 689                         #clock-cells = <0>;
 690                 };
 691                 sdhi0_clk: sdhi0ck@e6150074 {
 692                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 693                         reg = <0xe6150074 4>;
 694                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 695                                  <&pll1_div13_clk>, <0>;
 696                         #clock-cells = <0>;
 697                 };
 698                 sdhi1_clk: sdhi1ck@e6150078 {
 699                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 700                         reg = <0xe6150078 4>;
 701                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 702                                  <&pll1_div13_clk>, <0>;
 703                         #clock-cells = <0>;
 704                 };
 705                 sdhi2_clk: sdhi2ck@e615007c {
 706                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 707                         reg = <0xe615007c 4>;
 708                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 709                                  <&pll1_div13_clk>, <0>;
 710                         #clock-cells = <0>;
 711                 };
 712                 fsia_clk: fsia@e6150018 {
 713                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 714                         reg = <0xe6150018 4>;
 715                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 716                                  <&fsiack_clk>, <&fsiack_clk>;
 717                         #clock-cells = <0>;
 718                 };
 719                 fsib_clk: fsib@e6150090 {
 720                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 721                         reg = <0xe6150090 4>;
 722                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 723                                  <&fsibck_clk>, <&fsibck_clk>;
 724                         #clock-cells = <0>;
 725                 };
 726                 sub_clk: sub@e6150080 {
 727                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 728                         reg = <0xe6150080 4>;
 729                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 730                                  <&extal2_clk>, <&extal2_clk>;
 731                         #clock-cells = <0>;
 732                 };
 733                 spua_clk: spua@e6150084 {
 734                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 735                         reg = <0xe6150084 4>;
 736                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 737                                  <&extal2_clk>, <&extal2_clk>;
 738                         #clock-cells = <0>;
 739                 };
 740                 spuv_clk: spuv@e6150094 {
 741                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 742                         reg = <0xe6150094 4>;
 743                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 744                                  <&extal2_clk>, <&extal2_clk>;
 745                         #clock-cells = <0>;
 746                 };
 747                 msu_clk: msu@e6150088 {
 748                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 749                         reg = <0xe6150088 4>;
 750                         clocks = <&pll1_div2_clk>, <0>,
 751                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 752                         #clock-cells = <0>;
 753                 };
 754                 hsi_clk: hsi@e615008c {
 755                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 756                         reg = <0xe615008c 4>;
 757                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 758                                  <&pll1_div7_clk>, <0>;
 759                         #clock-cells = <0>;
 760                 };
 761                 mfg1_clk: mfg1@e6150098 {
 762                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 763                         reg = <0xe6150098 4>;
 764                         clocks = <&pll1_div2_clk>, <0>,
 765                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 766                         #clock-cells = <0>;
 767                 };
 768                 mfg2_clk: mfg2@e615009c {
 769                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 770                         reg = <0xe615009c 4>;
 771                         clocks = <&pll1_div2_clk>, <0>,
 772                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 773                         #clock-cells = <0>;
 774                 };
 775                 dsit_clk: dsit@e6150060 {
 776                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 777                         reg = <0xe6150060 4>;
 778                         clocks = <&pll1_div2_clk>, <0>,
 779                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 780                         #clock-cells = <0>;
 781                 };
 782                 dsi0p_clk: dsi0pck@e6150064 {
 783                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 784                         reg = <0xe6150064 4>;
 785                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 786                                  <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
 787                                  <&extcki_clk>, <0>, <0>, <0>;
 788                         #clock-cells = <0>;
 789                 };
 790
 791                 /* Fixed factor clocks */
 792                 main_div2_clk: main_div2 {
 793                         compatible = "fixed-factor-clock";
 794                         clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
 795                         #clock-cells = <0>;
 796                         clock-div = <2>;
 797                         clock-mult = <1>;
 798                 };
 799                 pll1_div2_clk: pll1_div2 {
 800                         compatible = "fixed-factor-clock";
 801                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 802                         #clock-cells = <0>;
 803                         clock-div = <2>;
 804                         clock-mult = <1>;
 805                 };
 806                 pll1_div7_clk: pll1_div7 {
 807                         compatible = "fixed-factor-clock";
 808                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 809                         #clock-cells = <0>;
 810                         clock-div = <7>;
 811                         clock-mult = <1>;
 812                 };
 813                 pll1_div13_clk: pll1_div13 {
 814                         compatible = "fixed-factor-clock";
 815                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 816                         #clock-cells = <0>;
 817                         clock-div = <13>;
 818                         clock-mult = <1>;
 819                 };
 820                 twd_clk: twd {
 821                         compatible = "fixed-factor-clock";
 822                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
 823                         #clock-cells = <0>;
 824                         clock-div = <4>;
 825                         clock-mult = <1>;
 826                 };
 827
 828                 /* Gate clocks */
 829                 mstp0_clks: mstp0_clks@e6150130 {
 830                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 831                         reg = <0xe6150130 4>, <0xe6150030 4>;
 832                         clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
 833                         #clock-cells = <1>;
 834                         clock-indices = <
 835                                 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
 836                         >;
 837                         clock-output-names =
 838                                 "iic2", "msiof0";
 839                 };
 840                 mstp1_clks: mstp1_clks@e6150134 {
 841                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 842                         reg = <0xe6150134 4>, <0xe6150038 4>;
 843                         clocks = <&cpg_clocks SH73A0_CLK_B>,
 844                                  <&cpg_clocks SH73A0_CLK_B>,
 845                                  <&cpg_clocks SH73A0_CLK_B>,
 846                                  <&cpg_clocks SH73A0_CLK_B>,
 847                                  <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
 848                                  <&cpg_clocks SH73A0_CLK_HP>,
 849                                  <&cpg_clocks SH73A0_CLK_ZG>,
 850                                  <&cpg_clocks SH73A0_CLK_B>;
 851                         #clock-cells = <1>;
 852                         clock-indices = <
 853                                 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
 854                                 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
 855                                 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
 856                                 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
 857                                 SH73A0_CLK_LCDC0
 858                         >;
 859                         clock-output-names =
 860                                 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
 861                                 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
 862                 };
 863                 mstp2_clks: mstp2_clks@e6150138 {
 864                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 865                         reg = <0xe6150138 4>, <0xe6150040 4>;
 866                         clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
 867                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 868                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 869                                  <&sub_clk>, <&sub_clk>, <&sub_clk>,
 870                                  <&sub_clk>, <&sub_clk>, <&sub_clk>;
 871                         #clock-cells = <1>;
 872                         clock-indices = <
 873                                 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
 874                                 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
 875                                 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
 876                                 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
 877                                 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
 878                                 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
 879                                 SH73A0_CLK_SCIFA4
 880                         >;
 881                         clock-output-names =
 882                                 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
 883                                 "msiof1", "scifa5", "scifb", "msiof2",
 884                                 "scifa0", "scifa1", "scifa2", "scifa3",
 885                                 "scifa4";
 886                 };
 887                 mstp3_clks: mstp3_clks@e615013c {
 888                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 889                         reg = <0xe615013c 4>, <0xe6150048 4>;
 890                         clocks = <&sub_clk>, <&extalr_clk>,
 891                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 892                                  <&cpg_clocks SH73A0_CLK_HP>,
 893                                  <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
 894                                  <&sdhi0_clk>, <&sdhi1_clk>,
 895                                  <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
 896                                  <&main_div2_clk>, <&main_div2_clk>,
 897                                  <&main_div2_clk>, <&main_div2_clk>,
 898                                  <&main_div2_clk>;
 899                         #clock-cells = <1>;
 900                         clock-indices = <
 901                                 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
 902                                 SH73A0_CLK_FSI SH73A0_CLK_IRDA
 903                                 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
 904                                 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
 905                                 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
 906                                 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
 907                                 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
 908                                 SH73A0_CLK_TPU4
 909                         >;
 910                         clock-output-names =
 911                                 "scifa6", "cmt1", "fsi", "irda", "iic1",
 912                                 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
 913                                 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
 914                 };
 915                 mstp4_clks: mstp4_clks@e6150140 {
 916                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 917                         reg = <0xe6150140 4>, <0xe615004c 4>;
 918                         clocks = <&cpg_clocks SH73A0_CLK_HP>,
 919                                  <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
 920                         #clock-cells = <1>;
 921                         clock-indices = <
 922                                 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
 923                                 SH73A0_CLK_KEYSC
 924                         >;
 925                         clock-output-names =
 926                                 "iic3", "iic4", "keysc";
 927                 };
 928                 mstp5_clks: mstp5_clks@e6150144 {
 929                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 930                         reg = <0xe6150144 4>, <0xe615003c 4>;
 931                         clocks = <&cpg_clocks SH73A0_CLK_HP>;
 932                         #clock-cells = <1>;
 933                         clock-indices = <
 934                                 SH73A0_CLK_INTCA0
 935                         >;
 936                         clock-output-names =
 937                                 "intca0";
 938                 };
 939         };
 940 };