arch/arm/boot/dts/rockchip/rk3128.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2017 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3128-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3128-power.h>
  12
  13 / {
  14         compatible = "rockchip,rk3128";
  15         interrupt-parent = <&gic>;
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         aliases {
  20                 gpio0 = &gpio0;
  21                 gpio1 = &gpio1;
  22                 gpio2 = &gpio2;
  23                 gpio3 = &gpio3;
  24                 i2c0 = &i2c0;
  25                 i2c1 = &i2c1;
  26                 i2c2 = &i2c2;
  27                 i2c3 = &i2c3;
  28                 serial0 = &uart0;
  29                 serial1 = &uart1;
  30                 serial2 = &uart2;
  31         };
  32
  33         arm-pmu {
  34                 compatible = "arm,cortex-a7-pmu";
  35                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  36                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  37                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  38                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  39                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45                 enable-method = "rockchip,rk3036-smp";
  46
  47                 cpu0: cpu@f00 {
  48                         device_type = "cpu";
  49                         compatible = "arm,cortex-a7";
  50                         reg = <0xf00>;
  51                         clock-latency = <40000>;
  52                         clocks = <&cru ARMCLK>;
  53                         resets = <&cru SRST_CORE0>;
  54                         operating-points-v2 = <&cpu_opp_table>;
  55                         #cooling-cells = <2>; /* min followed by max */
  56                 };
  57
  58                 cpu1: cpu@f01 {
  59                         device_type = "cpu";
  60                         compatible = "arm,cortex-a7";
  61                         reg = <0xf01>;
  62                         resets = <&cru SRST_CORE1>;
  63                         operating-points-v2 = <&cpu_opp_table>;
  64                 };
  65
  66                 cpu2: cpu@f02 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a7";
  69                         reg = <0xf02>;
  70                         resets = <&cru SRST_CORE2>;
  71                         operating-points-v2 = <&cpu_opp_table>;
  72                 };
  73
  74                 cpu3: cpu@f03 {
  75                         device_type = "cpu";
  76                         compatible = "arm,cortex-a7";
  77                         reg = <0xf03>;
  78                         resets = <&cru SRST_CORE3>;
  79                         operating-points-v2 = <&cpu_opp_table>;
  80                 };
  81         };
  82
  83         cpu_opp_table: opp-table-0 {
  84                 compatible = "operating-points-v2";
  85                 opp-shared;
  86
  87                 opp-216000000 {
  88                         opp-hz = /bits/ 64 <216000000>;
  89                         opp-microvolt = <950000 950000 1325000>;
  90                 };
  91                 opp-408000000 {
  92                         opp-hz = /bits/ 64 <408000000>;
  93                         opp-microvolt = <950000 950000 1325000>;
  94                 };
  95                 opp-600000000 {
  96                         opp-hz = /bits/ 64 <600000000>;
  97                         opp-microvolt = <950000 950000 1325000>;
  98                 };
  99                 opp-696000000 {
 100                         opp-hz = /bits/ 64 <696000000>;
 101                         opp-microvolt = <975000 975000 1325000>;
 102                 };
 103                 opp-816000000 {
 104                         opp-hz = /bits/ 64 <816000000>;
 105                         opp-microvolt = <1075000 1075000 1325000>;
 106                         opp-suspend;
 107                 };
 108                 opp-1008000000 {
 109                         opp-hz = /bits/ 64 <1008000000>;
 110                         opp-microvolt = <1200000 1200000 1325000>;
 111                 };
 112                 opp-1200000000 {
 113                         opp-hz = /bits/ 64 <1200000000>;
 114                         opp-microvolt = <1325000 1325000 1325000>;
 115                 };
 116         };
 117
 118         gpu_opp_table: opp-table-1 {
 119                 compatible = "operating-points-v2";
 120
 121                 opp-200000000 {
 122                         opp-hz = /bits/ 64 <200000000>;
 123                         opp-microvolt = <975000 975000 1250000>;
 124                 };
 125                 opp-300000000 {
 126                         opp-hz = /bits/ 64 <300000000>;
 127                         opp-microvolt = <1050000 1050000 1250000>;
 128                 };
 129                 opp-400000000 {
 130                         opp-hz = /bits/ 64 <400000000>;
 131                         opp-microvolt = <1150000 1150000 1250000>;
 132                 };
 133                 opp-480000000 {
 134                         opp-hz = /bits/ 64 <480000000>;
 135                         opp-microvolt = <1250000 1250000 1250000>;
 136                 };
 137         };
 138
 139         timer {
 140                 compatible = "arm,armv7-timer";
 141                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 142                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 143                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 144                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 145                 arm,cpu-registers-not-fw-configured;
 146                 clock-frequency = <24000000>;
 147         };
 148
 149         xin24m: oscillator {
 150                 compatible = "fixed-clock";
 151                 clock-frequency = <24000000>;
 152                 clock-output-names = "xin24m";
 153                 #clock-cells = <0>;
 154         };
 155
 156         imem: sram@10080000 {
 157                 compatible = "mmio-sram";
 158                 reg = <0x10080000 0x2000>;
 159                 #address-cells = <1>;
 160                 #size-cells = <1>;
 161                 ranges = <0 0x10080000 0x2000>;
 162
 163                 smp-sram@0 {
 164                         compatible = "rockchip,rk3066-smp-sram";
 165                         reg = <0x00 0x10>;
 166                 };
 167         };
 168
 169         gpu: gpu@10090000 {
 170                 compatible = "rockchip,rk3128-mali", "arm,mali-400";
 171                 reg = <0x10090000 0x10000>;
 172                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 176                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 177                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 178                 interrupt-names = "gp",
 179                                   "gpmmu",
 180                                   "pp0",
 181                                   "ppmmu0",
 182                                   "pp1",
 183                                   "ppmmu1";
 184                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
 185                 clock-names = "bus", "core";
 186                 operating-points-v2 = <&gpu_opp_table>;
 187                 resets = <&cru SRST_GPU>;
 188                 power-domains = <&power RK3128_PD_GPU>;
 189                 status = "disabled";
 190         };
 191
 192         pmu: syscon@100a0000 {
 193                 compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
 194                 reg = <0x100a0000 0x1000>;
 195
 196                 power: power-controller {
 197                         compatible = "rockchip,rk3128-power-controller";
 198                         #power-domain-cells = <1>;
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201
 202                         power-domain@RK3128_PD_VIO {
 203                                 reg = <RK3128_PD_VIO>;
 204                                 clocks = <&cru ACLK_CIF>,
 205                                          <&cru HCLK_CIF>,
 206                                          <&cru DCLK_EBC>,
 207                                          <&cru HCLK_EBC>,
 208                                          <&cru ACLK_IEP>,
 209                                          <&cru HCLK_IEP>,
 210                                          <&cru ACLK_LCDC0>,
 211                                          <&cru HCLK_LCDC0>,
 212                                          <&cru PCLK_MIPI>,
 213                                          <&cru ACLK_RGA>,
 214                                          <&cru HCLK_RGA>,
 215                                          <&cru ACLK_VIO0>,
 216                                          <&cru ACLK_VIO1>,
 217                                          <&cru HCLK_VIO>,
 218                                          <&cru HCLK_VIO_H2P>,
 219                                          <&cru DCLK_VOP>,
 220                                          <&cru SCLK_VOP>;
 221                                 pm_qos = <&qos_ebc>,
 222                                          <&qos_iep>,
 223                                          <&qos_lcdc>,
 224                                          <&qos_rga>,
 225                                          <&qos_vip>;
 226                                 #power-domain-cells = <0>;
 227                         };
 228
 229                         power-domain@RK3128_PD_VIDEO {
 230                                 reg = <RK3128_PD_VIDEO>;
 231                                 clocks = <&cru ACLK_VDPU>,
 232                                          <&cru HCLK_VDPU>,
 233                                          <&cru ACLK_VEPU>,
 234                                          <&cru HCLK_VEPU>,
 235                                          <&cru SCLK_HEVC_CORE>;
 236                                 pm_qos = <&qos_vpu>;
 237                                 #power-domain-cells = <0>;
 238                         };
 239
 240                         power-domain@RK3128_PD_GPU {
 241                                 reg = <RK3128_PD_GPU>;
 242                                 clocks = <&cru ACLK_GPU>;
 243                                 pm_qos = <&qos_gpu>;
 244                                 #power-domain-cells = <0>;
 245                         };
 246                 };
 247         };
 248
 249         qos_gpu: qos@1012d000 {
 250                 compatible = "rockchip,rk3128-qos", "syscon";
 251                 reg = <0x1012d000 0x20>;
 252         };
 253
 254         qos_vpu: qos@1012e000 {
 255                 compatible = "rockchip,rk3128-qos", "syscon";
 256                 reg = <0x1012e000 0x20>;
 257         };
 258
 259         qos_rga: qos@1012f000 {
 260                 compatible = "rockchip,rk3128-qos", "syscon";
 261                 reg = <0x1012f000 0x20>;
 262         };
 263
 264         qos_ebc: qos@1012f080 {
 265                 compatible = "rockchip,rk3128-qos", "syscon";
 266                 reg = <0x1012f080 0x20>;
 267         };
 268
 269         qos_iep: qos@1012f100 {
 270                 compatible = "rockchip,rk3128-qos", "syscon";
 271                 reg = <0x1012f100 0x20>;
 272         };
 273
 274         qos_lcdc: qos@1012f180 {
 275                 compatible = "rockchip,rk3128-qos", "syscon";
 276                 reg = <0x1012f180 0x20>;
 277         };
 278
 279         qos_vip: qos@1012f200 {
 280                 compatible = "rockchip,rk3128-qos", "syscon";
 281                 reg = <0x1012f200 0x20>;
 282         };
 283
 284         gic: interrupt-controller@10139000 {
 285                 compatible = "arm,cortex-a7-gic";
 286                 reg = <0x10139000 0x1000>,
 287                       <0x1013a000 0x1000>,
 288                       <0x1013c000 0x2000>,
 289                       <0x1013e000 0x2000>;
 290                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 291                 interrupt-controller;
 292                 #interrupt-cells = <3>;
 293                 #address-cells = <0>;
 294         };
 295
 296         usb_otg: usb@10180000 {
 297                 compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2";
 298                 reg = <0x10180000 0x40000>;
 299                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&cru HCLK_OTG>;
 301                 clock-names = "otg";
 302                 dr_mode = "otg";
 303                 g-np-tx-fifo-size = <16>;
 304                 g-rx-fifo-size = <280>;
 305                 g-tx-fifo-size = <256 128 128 64 32 16>;
 306                 phys = <&usb2phy_otg>;
 307                 phy-names = "usb2-phy";
 308                 status = "disabled";
 309         };
 310
 311         usb_host_ehci: usb@101c0000 {
 312                 compatible = "generic-ehci";
 313                 reg = <0x101c0000 0x20000>;
 314                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 315                 clocks = <&cru HCLK_HOST2>;
 316                 phys = <&usb2phy_host>;
 317                 phy-names = "usb";
 318                 status = "disabled";
 319         };
 320
 321         usb_host_ohci: usb@101e0000 {
 322                 compatible = "generic-ohci";
 323                 reg = <0x101e0000 0x20000>;
 324                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 325                 clocks = <&cru HCLK_HOST2>;
 326                 phys = <&usb2phy_host>;
 327                 phy-names = "usb";
 328                 status = "disabled";
 329         };
 330
 331         sdmmc: mmc@10214000 {
 332                 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 333                 reg = <0x10214000 0x4000>;
 334                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 335                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 336                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 337                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 338                 dmas = <&pdma 10>;
 339                 dma-names = "rx-tx";
 340                 fifo-depth = <256>;
 341                 max-frequency = <150000000>;
 342                 resets = <&cru SRST_SDMMC>;
 343                 reset-names = "reset";
 344                 status = "disabled";
 345         };
 346
 347         sdio: mmc@10218000 {
 348                 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 349                 reg = <0x10218000 0x4000>;
 350                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 351                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 352                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 dmas = <&pdma 11>;
 355                 dma-names = "rx-tx";
 356                 fifo-depth = <256>;
 357                 max-frequency = <150000000>;
 358                 resets = <&cru SRST_SDIO>;
 359                 reset-names = "reset";
 360                 status = "disabled";
 361         };
 362
 363         emmc: mmc@1021c000 {
 364                 compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc";
 365                 reg = <0x1021c000 0x4000>;
 366                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 368                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 369                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 370                 dmas = <&pdma 12>;
 371                 dma-names = "rx-tx";
 372                 fifo-depth = <256>;
 373                 max-frequency = <150000000>;
 374                 resets = <&cru SRST_EMMC>;
 375                 reset-names = "reset";
 376                 status = "disabled";
 377         };
 378
 379         nfc: nand-controller@10500000 {
 380                 compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc";
 381                 reg = <0x10500000 0x4000>;
 382                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
 384                 clock-names = "ahb", "nfc";
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
 387                              &flash_dqs &flash_rdn &flash_rdy &flash_wrn>;
 388                 status = "disabled";
 389         };
 390
 391         cru: clock-controller@20000000 {
 392                 compatible = "rockchip,rk3128-cru";
 393                 reg = <0x20000000 0x1000>;
 394                 clocks = <&xin24m>;
 395                 clock-names = "xin24m";
 396                 rockchip,grf = <&grf>;
 397                 #clock-cells = <1>;
 398                 #reset-cells = <1>;
 399                 assigned-clocks = <&cru PLL_GPLL>;
 400                 assigned-clock-rates = <594000000>;
 401         };
 402
 403         grf: syscon@20008000 {
 404                 compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd";
 405                 reg = <0x20008000 0x1000>;
 406                 #address-cells = <1>;
 407                 #size-cells = <1>;
 408
 409                 usb2phy: usb2phy@17c {
 410                         compatible = "rockchip,rk3128-usb2phy";
 411                         reg = <0x017c 0x0c>;
 412                         clocks = <&cru SCLK_OTGPHY0>;
 413                         clock-names = "phyclk";
 414                         clock-output-names = "usb480m_phy";
 415                         assigned-clocks = <&cru SCLK_USB480M>;
 416                         assigned-clock-parents = <&usb2phy>;
 417                         #clock-cells = <0>;
 418                         status = "disabled";
 419
 420                         usb2phy_host: host-port {
 421                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 422                                 interrupt-names = "linestate";
 423                                 #phy-cells = <0>;
 424                                 status = "disabled";
 425                         };
 426
 427                         usb2phy_otg: otg-port {
 428                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 429                                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 430                                              <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 431                                 interrupt-names = "otg-bvalid", "otg-id",
 432                                                   "linestate";
 433                                 #phy-cells = <0>;
 434                                 status = "disabled";
 435                         };
 436                 };
 437         };
 438
 439         timer0: timer@20044000 {
 440                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 441                 reg = <0x20044000 0x20>;
 442                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 443                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
 444                 clock-names = "pclk", "timer";
 445         };
 446
 447         timer1: timer@20044020 {
 448                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 449                 reg = <0x20044020 0x20>;
 450                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 451                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
 452                 clock-names = "pclk", "timer";
 453         };
 454
 455         timer2: timer@20044040 {
 456                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 457                 reg = <0x20044040 0x20>;
 458                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 459                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
 460                 clock-names = "pclk", "timer";
 461         };
 462
 463         timer3: timer@20044060 {
 464                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 465                 reg = <0x20044060 0x20>;
 466                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
 468                 clock-names = "pclk", "timer";
 469         };
 470
 471         timer4: timer@20044080 {
 472                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 473                 reg = <0x20044080 0x20>;
 474                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 475                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
 476                 clock-names = "pclk", "timer";
 477         };
 478
 479         timer5: timer@200440a0 {
 480                 compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
 481                 reg = <0x200440a0 0x20>;
 482                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 483                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
 484                 clock-names = "pclk", "timer";
 485         };
 486
 487         watchdog: watchdog@2004c000 {
 488                 compatible = "rockchip,rk3128-wdt", "snps,dw-wdt";
 489                 reg = <0x2004c000 0x100>;
 490                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 491                 clocks = <&cru PCLK_WDT>;
 492                 status = "disabled";
 493         };
 494
 495         pwm0: pwm@20050000 {
 496                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 497                 reg = <0x20050000 0x10>;
 498                 clocks = <&cru PCLK_PWM>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&pwm0_pin>;
 501                 #pwm-cells = <3>;
 502                 status = "disabled";
 503         };
 504
 505         pwm1: pwm@20050010 {
 506                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 507                 reg = <0x20050010 0x10>;
 508                 clocks = <&cru PCLK_PWM>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&pwm1_pin>;
 511                 #pwm-cells = <3>;
 512                 status = "disabled";
 513         };
 514
 515         pwm2: pwm@20050020 {
 516                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 517                 reg = <0x20050020 0x10>;
 518                 clocks = <&cru PCLK_PWM>;
 519                 pinctrl-names = "default";
 520                 pinctrl-0 = <&pwm2_pin>;
 521                 #pwm-cells = <3>;
 522                 status = "disabled";
 523         };
 524
 525         pwm3: pwm@20050030 {
 526                 compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm";
 527                 reg = <0x20050030 0x10>;
 528                 clocks = <&cru PCLK_PWM>;
 529                 pinctrl-names = "default";
 530                 pinctrl-0 = <&pwm3_pin>;
 531                 #pwm-cells = <3>;
 532                 status = "disabled";
 533         };
 534
 535         i2c1: i2c@20056000 {
 536                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 537                 reg = <0x20056000 0x1000>;
 538                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 539                 clock-names = "i2c";
 540                 clocks = <&cru PCLK_I2C1>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&i2c1_xfer>;
 543                 #address-cells = <1>;
 544                 #size-cells = <0>;
 545                 status = "disabled";
 546         };
 547
 548         i2c2: i2c@2005a000 {
 549                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 550                 reg = <0x2005a000 0x1000>;
 551                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 552                 clock-names = "i2c";
 553                 clocks = <&cru PCLK_I2C2>;
 554                 pinctrl-names = "default";
 555                 pinctrl-0 = <&i2c2_xfer>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 status = "disabled";
 559         };
 560
 561         i2c3: i2c@2005e000 {
 562                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 563                 reg = <0x2005e000 0x1000>;
 564                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 565                 clock-names = "i2c";
 566                 clocks = <&cru PCLK_I2C3>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&i2c3_xfer>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 status = "disabled";
 572         };
 573
 574         uart0: serial@20060000 {
 575                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 576                 reg = <0x20060000 0x100>;
 577                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 578                 clock-frequency = <24000000>;
 579                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 580                 clock-names = "baudclk", "apb_pclk";
 581                 dmas = <&pdma 2>, <&pdma 3>;
 582                 dma-names = "tx", "rx";
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 585                 reg-io-width = <4>;
 586                 reg-shift = <2>;
 587                 status = "disabled";
 588         };
 589
 590         uart1: serial@20064000 {
 591                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 592                 reg = <0x20064000 0x100>;
 593                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
 594                 clock-frequency = <24000000>;
 595                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 596                 clock-names = "baudclk", "apb_pclk";
 597                 dmas = <&pdma 4>, <&pdma 5>;
 598                 dma-names = "tx", "rx";
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&uart1_xfer>;
 601                 reg-io-width = <4>;
 602                 reg-shift = <2>;
 603                 status = "disabled";
 604         };
 605
 606         uart2: serial@20068000 {
 607                 compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart";
 608                 reg = <0x20068000 0x100>;
 609                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 610                 clock-frequency = <24000000>;
 611                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 612                 clock-names = "baudclk", "apb_pclk";
 613                 dmas = <&pdma 6>, <&pdma 7>;
 614                 dma-names = "tx", "rx";
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&uart2_xfer>;
 617                 reg-io-width = <4>;
 618                 reg-shift = <2>;
 619                 status = "disabled";
 620         };
 621
 622         saradc: saradc@2006c000 {
 623                 compatible = "rockchip,saradc";
 624                 reg = <0x2006c000 0x100>;
 625                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 626                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 627                 clock-names = "saradc", "apb_pclk";
 628                 resets = <&cru SRST_SARADC>;
 629                 reset-names = "saradc-apb";
 630                 #io-channel-cells = <1>;
 631                 status = "disabled";
 632         };
 633
 634         i2c0: i2c@20072000 {
 635                 compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c";
 636                 reg = <0x20072000 0x1000>;
 637                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 638                 clock-names = "i2c";
 639                 clocks = <&cru PCLK_I2C0>;
 640                 pinctrl-names = "default";
 641                 pinctrl-0 = <&i2c0_xfer>;
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 status = "disabled";
 645         };
 646
 647         spi0: spi@20074000 {
 648                 compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi";
 649                 reg = <0x20074000 0x1000>;
 650                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 652                 clock-names = "spiclk", "apb_pclk";
 653                 dmas = <&pdma 8>, <&pdma 9>;
 654                 dma-names = "tx", "rx";
 655                 pinctrl-names = "default";
 656                 pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
 657                 #address-cells = <1>;
 658                 #size-cells = <0>;
 659                 status = "disabled";
 660         };
 661
 662         pdma: dma-controller@20078000 {
 663                 compatible = "arm,pl330", "arm,primecell";
 664                 reg = <0x20078000 0x4000>;
 665                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 666                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 667                 arm,pl330-broken-no-flushp;
 668                 arm,pl330-periph-burst;
 669                 clocks = <&cru ACLK_DMAC>;
 670                 clock-names = "apb_pclk";
 671                 #dma-cells = <1>;
 672         };
 673
 674         gmac: ethernet@2008c000 {
 675                 compatible = "rockchip,rk3128-gmac";
 676                 reg = <0x2008c000 0x4000>;
 677                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 678                              <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 679                 interrupt-names = "macirq", "eth_wake_irq";
 680                 clocks = <&cru SCLK_MAC>,
 681                          <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 682                          <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
 683                          <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 684                 clock-names = "stmmaceth",
 685                               "mac_clk_rx", "mac_clk_tx",
 686                               "clk_mac_ref", "clk_mac_refout",
 687                               "aclk_mac", "pclk_mac";
 688                 resets = <&cru SRST_GMAC>;
 689                 reset-names = "stmmaceth";
 690                 rockchip,grf = <&grf>;
 691                 rx-fifo-depth = <4096>;
 692                 tx-fifo-depth = <2048>;
 693                 status = "disabled";
 694
 695                 mdio: mdio {
 696                         compatible = "snps,dwmac-mdio";
 697                         #address-cells = <0x1>;
 698                         #size-cells = <0x0>;
 699                 };
 700         };
 701
 702         pinctrl: pinctrl {
 703                 compatible = "rockchip,rk3128-pinctrl";
 704                 rockchip,grf = <&grf>;
 705                 #address-cells = <1>;
 706                 #size-cells = <1>;
 707                 ranges;
 708
 709                 gpio0: gpio@2007c000 {
 710                         compatible = "rockchip,gpio-bank";
 711                         reg = <0x2007c000 0x100>;
 712                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 713                         clocks = <&cru PCLK_GPIO0>;
 714                         gpio-controller;
 715                         #gpio-cells = <2>;
 716                         interrupt-controller;
 717                         #interrupt-cells = <2>;
 718                 };
 719
 720                 gpio1: gpio@20080000 {
 721                         compatible = "rockchip,gpio-bank";
 722                         reg = <0x20080000 0x100>;
 723                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 724                         clocks = <&cru PCLK_GPIO1>;
 725                         gpio-controller;
 726                         #gpio-cells = <2>;
 727                         interrupt-controller;
 728                         #interrupt-cells = <2>;
 729                 };
 730
 731                 gpio2: gpio@20084000 {
 732                         compatible = "rockchip,gpio-bank";
 733                         reg = <0x20084000 0x100>;
 734                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 735                         clocks = <&cru PCLK_GPIO2>;
 736                         gpio-controller;
 737                         #gpio-cells = <2>;
 738                         interrupt-controller;
 739                         #interrupt-cells = <2>;
 740                 };
 741
 742                 gpio3: gpio@20088000 {
 743                         compatible = "rockchip,gpio-bank";
 744                         reg = <0x20088000 0x100>;
 745                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 746                         clocks = <&cru PCLK_GPIO3>;
 747                         gpio-controller;
 748                         #gpio-cells = <2>;
 749                         interrupt-controller;
 750                         #interrupt-cells = <2>;
 751                 };
 752
 753                 pcfg_pull_default: pcfg-pull-default {
 754                         bias-pull-pin-default;
 755                 };
 756
 757                 pcfg_pull_none: pcfg-pull-none {
 758                         bias-disable;
 759                 };
 760
 761                 emmc {
 762                         emmc_clk: emmc-clk {
 763                                 rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>;
 764                         };
 765
 766                         emmc_cmd: emmc-cmd {
 767                                 rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>;
 768                         };
 769
 770                         emmc_cmd1: emmc-cmd1 {
 771                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>;
 772                         };
 773
 774                         emmc_pwr: emmc-pwr {
 775                                 rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>;
 776                         };
 777
 778                         emmc_bus1: emmc-bus1 {
 779                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>;
 780                         };
 781
 782                         emmc_bus4: emmc-bus4 {
 783                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 784                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 785                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 786                                                 <1 RK_PD3 2 &pcfg_pull_default>;
 787                         };
 788
 789                         emmc_bus8: emmc-bus8 {
 790                                 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
 791                                                 <1 RK_PD1 2 &pcfg_pull_default>,
 792                                                 <1 RK_PD2 2 &pcfg_pull_default>,
 793                                                 <1 RK_PD3 2 &pcfg_pull_default>,
 794                                                 <1 RK_PD4 2 &pcfg_pull_default>,
 795                                                 <1 RK_PD5 2 &pcfg_pull_default>,
 796                                                 <1 RK_PD6 2 &pcfg_pull_default>,
 797                                                 <1 RK_PD7 2 &pcfg_pull_default>;
 798                         };
 799                 };
 800
 801                 gmac {
 802                         rgmii_pins: rgmii-pins {
 803                                 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
 804                                                 <2 RK_PB1 3 &pcfg_pull_default>,
 805                                                 <2 RK_PB3 3 &pcfg_pull_default>,
 806                                                 <2 RK_PB4 3 &pcfg_pull_default>,
 807                                                 <2 RK_PB5 3 &pcfg_pull_default>,
 808                                                 <2 RK_PB6 3 &pcfg_pull_default>,
 809                                                 <2 RK_PC0 3 &pcfg_pull_default>,
 810                                                 <2 RK_PC1 3 &pcfg_pull_default>,
 811                                                 <2 RK_PC2 3 &pcfg_pull_default>,
 812                                                 <2 RK_PC3 3 &pcfg_pull_default>,
 813                                                 <2 RK_PD1 3 &pcfg_pull_default>,
 814                                                 <2 RK_PC4 4 &pcfg_pull_default>,
 815                                                 <2 RK_PC5 4 &pcfg_pull_default>,
 816                                                 <2 RK_PC6 4 &pcfg_pull_default>,
 817                                                 <2 RK_PC7 4 &pcfg_pull_default>;
 818                         };
 819
 820                         rmii_pins: rmii-pins {
 821                                 rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>,
 822                                                 <2 RK_PB4 3 &pcfg_pull_default>,
 823                                                 <2 RK_PB5 3 &pcfg_pull_default>,
 824                                                 <2 RK_PB6 3 &pcfg_pull_default>,
 825                                                 <2 RK_PB7 3 &pcfg_pull_default>,
 826                                                 <2 RK_PC0 3 &pcfg_pull_default>,
 827                                                 <2 RK_PC1 3 &pcfg_pull_default>,
 828                                                 <2 RK_PC2 3 &pcfg_pull_default>,
 829                                                 <2 RK_PC3 3 &pcfg_pull_default>,
 830                                                 <2 RK_PD1 3 &pcfg_pull_default>;
 831                         };
 832                 };
 833
 834                 hdmi {
 835                         hdmii2c_xfer: hdmii2c-xfer {
 836                                 rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>,
 837                                                 <0 RK_PA7 2 &pcfg_pull_none>;
 838                         };
 839
 840                         hdmi_hpd: hdmi-hpd {
 841                                 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
 842                         };
 843
 844                         hdmi_cec: hdmi-cec {
 845                                 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
 846                         };
 847                 };
 848
 849                 i2c0 {
 850                         i2c0_xfer: i2c0-xfer {
 851                                 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
 852                                                 <0 RK_PA1 1 &pcfg_pull_none>;
 853                         };
 854                 };
 855
 856                 i2c1 {
 857                         i2c1_xfer: i2c1-xfer {
 858                                 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
 859                                                 <0 RK_PA3 1 &pcfg_pull_none>;
 860                         };
 861                 };
 862
 863                 i2c2 {
 864                         i2c2_xfer: i2c2-xfer {
 865                                 rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>,
 866                                                 <2 RK_PC5 3 &pcfg_pull_none>;
 867                         };
 868                 };
 869
 870                 i2c3 {
 871                         i2c3_xfer: i2c3-xfer {
 872                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
 873                                                 <0 RK_PA7 1 &pcfg_pull_none>;
 874                         };
 875                 };
 876
 877                 i2s {
 878                         i2s_bus: i2s-bus {
 879                                 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>,
 880                                                 <0 RK_PB1 1 &pcfg_pull_none>,
 881                                                 <0 RK_PB3 1 &pcfg_pull_none>,
 882                                                 <0 RK_PB4 1 &pcfg_pull_none>,
 883                                                 <0 RK_PB5 1 &pcfg_pull_none>,
 884                                                 <0 RK_PB6 1 &pcfg_pull_none>;
 885                         };
 886
 887                         i2s1_bus: i2s1-bus {
 888                                 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>,
 889                                                 <1 RK_PA1 1 &pcfg_pull_none>,
 890                                                 <1 RK_PA2 1 &pcfg_pull_none>,
 891                                                 <1 RK_PA3 1 &pcfg_pull_none>,
 892                                                 <1 RK_PA4 1 &pcfg_pull_none>,
 893                                                 <1 RK_PA5 1 &pcfg_pull_none>;
 894                         };
 895                 };
 896
 897                 lcdc {
 898                         lcdc_dclk: lcdc-dclk {
 899                                 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>;
 900                         };
 901
 902                         lcdc_den: lcdc-den {
 903                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>;
 904                         };
 905
 906                         lcdc_hsync: lcdc-hsync {
 907                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
 908                         };
 909
 910                         lcdc_vsync: lcdc-vsync {
 911                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>;
 912                         };
 913
 914                         lcdc_rgb24: lcdc-rgb24 {
 915                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
 916                                                 <2 RK_PB5 1 &pcfg_pull_none>,
 917                                                 <2 RK_PB6 1 &pcfg_pull_none>,
 918                                                 <2 RK_PB7 1 &pcfg_pull_none>,
 919                                                 <2 RK_PC0 1 &pcfg_pull_none>,
 920                                                 <2 RK_PC1 1 &pcfg_pull_none>,
 921                                                 <2 RK_PC2 1 &pcfg_pull_none>,
 922                                                 <2 RK_PC3 1 &pcfg_pull_none>,
 923                                                 <2 RK_PC4 1 &pcfg_pull_none>,
 924                                                 <2 RK_PC5 1 &pcfg_pull_none>,
 925                                                 <2 RK_PC6 1 &pcfg_pull_none>,
 926                                                 <2 RK_PC7 1 &pcfg_pull_none>,
 927                                                 <2 RK_PD0 1 &pcfg_pull_none>,
 928                                                 <2 RK_PD1 1 &pcfg_pull_none>;
 929                         };
 930                 };
 931
 932                 nfc {
 933                         flash_ale: flash-ale {
 934                                 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>;
 935                         };
 936
 937                         flash_cle: flash-cle {
 938                                 rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>;
 939                         };
 940
 941                         flash_wrn: flash-wrn {
 942                                 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
 943                         };
 944
 945                         flash_rdn: flash-rdn {
 946                                 rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>;
 947                         };
 948
 949                         flash_rdy: flash-rdy {
 950                                 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
 951                         };
 952
 953                         flash_cs0: flash-cs0 {
 954                                 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
 955                         };
 956
 957                         flash_dqs: flash-dqs {
 958                                 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
 959                         };
 960
 961                         flash_bus8: flash-bus8 {
 962                                 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>,
 963                                                 <1 RK_PD1 1 &pcfg_pull_none>,
 964                                                 <1 RK_PD2 1 &pcfg_pull_none>,
 965                                                 <1 RK_PD3 1 &pcfg_pull_none>,
 966                                                 <1 RK_PD4 1 &pcfg_pull_none>,
 967                                                 <1 RK_PD5 1 &pcfg_pull_none>,
 968                                                 <1 RK_PD6 1 &pcfg_pull_none>,
 969                                                 <1 RK_PD7 1 &pcfg_pull_none>;
 970                         };
 971                 };
 972
 973                 pwm0 {
 974                         pwm0_pin: pwm0-pin {
 975                                 rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>;
 976                         };
 977                 };
 978
 979                 pwm1 {
 980                         pwm1_pin: pwm1-pin {
 981                                 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
 982                         };
 983                 };
 984
 985                 pwm2 {
 986                         pwm2_pin: pwm2-pin {
 987                                 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
 988                         };
 989                 };
 990
 991                 pwm3 {
 992                         pwm3_pin: pwm3-pin {
 993                                 rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>;
 994                         };
 995                 };
 996
 997                 sdio {
 998                         sdio_clk: sdio-clk {
 999                                 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>;
1000                         };
1001
1002                         sdio_cmd: sdio-cmd {
1003                                 rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>;
1004                         };
1005
1006                         sdio_pwren: sdio-pwren {
1007                                 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>;
1008                         };
1009
1010                         sdio_bus4: sdio-bus4 {
1011                                 rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>,
1012                                                 <1 RK_PA2 2 &pcfg_pull_default>,
1013                                                 <1 RK_PA4 2 &pcfg_pull_default>,
1014                                                 <1 RK_PA5 2 &pcfg_pull_default>;
1015                         };
1016                 };
1017
1018                 sdmmc {
1019                         sdmmc_clk: sdmmc-clk {
1020                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1021                         };
1022
1023                         sdmmc_cmd: sdmmc-cmd {
1024                                 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
1025                         };
1026
1027                         sdmmc_det: sdmmc-det {
1028                                 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
1029                         };
1030
1031                         sdmmc_wp: sdmmc-wp {
1032                                 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>;
1033                         };
1034
1035                         sdmmc_pwren: sdmmc-pwren {
1036                                 rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_default>;
1037                         };
1038
1039                         sdmmc_bus4: sdmmc-bus4 {
1040                                 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
1041                                                 <1 RK_PC3 1 &pcfg_pull_default>,
1042                                                 <1 RK_PC4 1 &pcfg_pull_default>,
1043                                                 <1 RK_PC5 1 &pcfg_pull_default>;
1044                         };
1045                 };
1046
1047                 spdif {
1048                         spdif_tx: spdif-tx {
1049                                 rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>;
1050                         };
1051                 };
1052
1053                 spi0 {
1054                         spi0_clk: spi0-clk {
1055                                 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1056                         };
1057
1058                         spi0_cs0: spi0-cs0 {
1059                                 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1060                         };
1061
1062                         spi0_tx: spi0-tx {
1063                                 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1064                         };
1065
1066                         spi0_rx: spi0-rx {
1067                                 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1068                         };
1069
1070                         spi0_cs1: spi0-cs1 {
1071                                 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1072                         };
1073
1074                         spi1_clk: spi1-clk {
1075                                 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1076                         };
1077
1078                         spi1_cs0: spi1-cs0 {
1079                                 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1080                         };
1081
1082                         spi1_tx: spi1-tx {
1083                                 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1084                         };
1085
1086                         spi1_rx: spi1-rx {
1087                                 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1088                         };
1089
1090                         spi1_cs1: spi1-cs1 {
1091                                 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1092                         };
1093
1094                         spi2_clk: spi2-clk {
1095                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1096                         };
1097
1098                         spi2_cs0: spi2-cs0 {
1099                                 rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1100                         };
1101
1102                         spi2_tx: spi2-tx {
1103                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1104                         };
1105
1106                         spi2_rx: spi2-rx {
1107                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1108                         };
1109                 };
1110
1111                 uart0 {
1112                         uart0_xfer: uart0-xfer {
1113                                 rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1114                                                 <2 RK_PD3 2 &pcfg_pull_none>;
1115                         };
1116
1117                         uart0_cts: uart0-cts {
1118                                 rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>;
1119                         };
1120
1121                         uart0_rts: uart0-rts {
1122                                 rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>;
1123                         };
1124                 };
1125
1126                 uart1 {
1127                         uart1_xfer: uart1-xfer {
1128                                 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1129                                                 <1 RK_PB2 2 &pcfg_pull_default>;
1130                         };
1131
1132                         uart1_cts: uart1-cts {
1133                                 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
1134                         };
1135
1136                         uart1_rts: uart1-rts {
1137                                 rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>;
1138                         };
1139                 };
1140
1141                 uart2 {
1142                         uart2_xfer: uart2-xfer {
1143                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1144                                                 <1 RK_PC3 2 &pcfg_pull_none>;
1145                         };
1146
1147                         uart2_cts: uart2-cts {
1148                                 rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>;
1149                         };
1150
1151                         uart2_rts: uart2-rts {
1152                                 rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>;
1153                         };
1154                 };
1155         };
1156 };