1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/power/rk3288-power.h>
11 #include <dt-bindings/soc/rockchip,boot-mode.h>
17 compatible = "rockchip,rk3288";
19 interrupt-parent = <&gic>;
44 compatible = "arm,cortex-a12-pmu";
45 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
49 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
55 enable-method = "rockchip,rk3066-smp";
56 rockchip,pmu = <&pmu>;
60 compatible = "arm,cortex-a12";
62 resets = <&cru SRST_CORE0>;
63 operating-points-v2 = <&cpu_opp_table>;
64 #cooling-cells = <2>; /* min followed by max */
65 clock-latency = <40000>;
66 clocks = <&cru ARMCLK>;
70 compatible = "arm,cortex-a12";
72 resets = <&cru SRST_CORE1>;
73 operating-points = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
76 clocks = <&cru ARMCLK>;
80 compatible = "arm,cortex-a12";
82 resets = <&cru SRST_CORE2>;
83 operating-points = <&cpu_opp_table>;
84 #cooling-cells = <2>; /* min followed by max */
85 clock-latency = <40000>;
86 clocks = <&cru ARMCLK>;
90 compatible = "arm,cortex-a12";
92 resets = <&cru SRST_CORE3>;
93 operating-points = <&cpu_opp_table>;
94 #cooling-cells = <2>; /* min followed by max */
95 clock-latency = <40000>;
96 clocks = <&cru ARMCLK>;
100 cpu_opp_table: cpu-opp-table {
101 compatible = "operating-points-v2";
105 opp-hz = /bits/ 64 <126000000>;
106 opp-microvolt = <900000>;
109 opp-hz = /bits/ 64 <216000000>;
110 opp-microvolt = <900000>;
113 opp-hz = /bits/ 64 <312000000>;
114 opp-microvolt = <900000>;
117 opp-hz = /bits/ 64 <408000000>;
118 opp-microvolt = <900000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <900000>;
125 opp-hz = /bits/ 64 <696000000>;
126 opp-microvolt = <950000>;
129 opp-hz = /bits/ 64 <816000000>;
130 opp-microvolt = <1000000>;
133 opp-hz = /bits/ 64 <1008000000>;
134 opp-microvolt = <1050000>;
137 opp-hz = /bits/ 64 <1200000000>;
138 opp-microvolt = <1100000>;
141 opp-hz = /bits/ 64 <1416000000>;
142 opp-microvolt = <1200000>;
145 opp-hz = /bits/ 64 <1512000000>;
146 opp-microvolt = <1300000>;
149 opp-hz = /bits/ 64 <1608000000>;
150 opp-microvolt = <1350000>;
155 compatible = "simple-bus";
156 #address-cells = <2>;
160 dmac_peri: dma-controller@ff250000 {
161 compatible = "arm,pl330", "arm,primecell";
162 reg = <0x0 0xff250000 0x0 0x4000>;
163 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
166 arm,pl330-broken-no-flushp;
167 clocks = <&cru ACLK_DMAC2>;
168 clock-names = "apb_pclk";
171 dmac_bus_ns: dma-controller@ff600000 {
172 compatible = "arm,pl330", "arm,primecell";
173 reg = <0x0 0xff600000 0x0 0x4000>;
174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
177 arm,pl330-broken-no-flushp;
178 clocks = <&cru ACLK_DMAC1>;
179 clock-names = "apb_pclk";
183 dmac_bus_s: dma-controller@ffb20000 {
184 compatible = "arm,pl330", "arm,primecell";
185 reg = <0x0 0xffb20000 0x0 0x4000>;
186 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
189 arm,pl330-broken-no-flushp;
190 clocks = <&cru ACLK_DMAC1>;
191 clock-names = "apb_pclk";
196 #address-cells = <2>;
201 * The rk3288 cannot use the memory area above 0xfe000000
202 * for dma operations for some reason. While there is
203 * probably a better solution available somewhere, we
204 * haven't found it yet and while devices with 2GB of ram
205 * are not affected, this issue prevents 4GB from booting.
206 * So to make these devices at least bootable, block
207 * this area for the time being until the real solution
210 dma-unusable@fe000000 {
211 reg = <0x0 0xfe000000 0x0 0x1000000>;
216 compatible = "fixed-clock";
217 clock-frequency = <24000000>;
218 clock-output-names = "xin24m";
223 compatible = "arm,armv7-timer";
224 arm,cpu-registers-not-fw-configured;
225 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
226 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
227 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
228 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
229 clock-frequency = <24000000>;
232 timer: timer@ff810000 {
233 compatible = "rockchip,rk3288-timer";
234 reg = <0x0 0xff810000 0x0 0x20>;
235 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
236 clocks = <&xin24m>, <&cru PCLK_TIMER>;
237 clock-names = "timer", "pclk";
241 compatible = "rockchip,display-subsystem";
242 ports = <&vopl_out>, <&vopb_out>;
245 sdmmc: dwmmc@ff0c0000 {
246 compatible = "rockchip,rk3288-dw-mshc";
247 max-frequency = <150000000>;
248 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
249 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
251 fifo-depth = <0x100>;
252 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
253 reg = <0x0 0xff0c0000 0x0 0x4000>;
254 resets = <&cru SRST_MMC0>;
255 reset-names = "reset";
259 sdio0: dwmmc@ff0d0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 max-frequency = <150000000>;
262 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
263 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0x0 0xff0d0000 0x0 0x4000>;
268 resets = <&cru SRST_SDIO0>;
269 reset-names = "reset";
273 sdio1: dwmmc@ff0e0000 {
274 compatible = "rockchip,rk3288-dw-mshc";
275 max-frequency = <150000000>;
276 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
277 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
278 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
279 fifo-depth = <0x100>;
280 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
281 reg = <0x0 0xff0e0000 0x0 0x4000>;
282 resets = <&cru SRST_SDIO1>;
283 reset-names = "reset";
287 emmc: dwmmc@ff0f0000 {
288 compatible = "rockchip,rk3288-dw-mshc";
289 max-frequency = <150000000>;
290 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
291 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
292 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
293 fifo-depth = <0x100>;
294 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
295 reg = <0x0 0xff0f0000 0x0 0x4000>;
296 resets = <&cru SRST_EMMC>;
297 reset-names = "reset";
301 saradc: saradc@ff100000 {
302 compatible = "rockchip,saradc";
303 reg = <0x0 0xff100000 0x0 0x100>;
304 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
305 #io-channel-cells = <1>;
306 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
307 clock-names = "saradc", "apb_pclk";
308 resets = <&cru SRST_SARADC>;
309 reset-names = "saradc-apb";
314 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
315 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
316 clock-names = "spiclk", "apb_pclk";
317 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
318 dma-names = "tx", "rx";
319 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
322 reg = <0x0 0xff110000 0x0 0x1000>;
323 #address-cells = <1>;
329 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
330 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
331 clock-names = "spiclk", "apb_pclk";
332 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
333 dma-names = "tx", "rx";
334 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
337 reg = <0x0 0xff120000 0x0 0x1000>;
338 #address-cells = <1>;
344 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
345 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
346 clock-names = "spiclk", "apb_pclk";
347 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
348 dma-names = "tx", "rx";
349 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
352 reg = <0x0 0xff130000 0x0 0x1000>;
353 #address-cells = <1>;
359 compatible = "rockchip,rk3288-i2c";
360 reg = <0x0 0xff140000 0x0 0x1000>;
361 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
362 #address-cells = <1>;
365 clocks = <&cru PCLK_I2C1>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&i2c1_xfer>;
372 compatible = "rockchip,rk3288-i2c";
373 reg = <0x0 0xff150000 0x0 0x1000>;
374 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
375 #address-cells = <1>;
378 clocks = <&cru PCLK_I2C3>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&i2c3_xfer>;
385 compatible = "rockchip,rk3288-i2c";
386 reg = <0x0 0xff160000 0x0 0x1000>;
387 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
388 #address-cells = <1>;
391 clocks = <&cru PCLK_I2C4>;
392 pinctrl-names = "default";
393 pinctrl-0 = <&i2c4_xfer>;
398 compatible = "rockchip,rk3288-i2c";
399 reg = <0x0 0xff170000 0x0 0x1000>;
400 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
404 clocks = <&cru PCLK_I2C5>;
405 pinctrl-names = "default";
406 pinctrl-0 = <&i2c5_xfer>;
410 uart0: serial@ff180000 {
411 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
412 reg = <0x0 0xff180000 0x0 0x100>;
413 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
417 clock-names = "baudclk", "apb_pclk";
418 pinctrl-names = "default";
419 pinctrl-0 = <&uart0_xfer>;
423 uart1: serial@ff190000 {
424 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
425 reg = <0x0 0xff190000 0x0 0x100>;
426 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
430 clock-names = "baudclk", "apb_pclk";
431 pinctrl-names = "default";
432 pinctrl-0 = <&uart1_xfer>;
436 uart2: serial@ff690000 {
437 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
438 reg = <0x0 0xff690000 0x0 0x100>;
439 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
443 clock-names = "baudclk", "apb_pclk";
444 pinctrl-names = "default";
445 pinctrl-0 = <&uart2_xfer>;
449 uart3: serial@ff1b0000 {
450 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
451 reg = <0x0 0xff1b0000 0x0 0x100>;
452 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
456 clock-names = "baudclk", "apb_pclk";
457 pinctrl-names = "default";
458 pinctrl-0 = <&uart3_xfer>;
462 uart4: serial@ff1c0000 {
463 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
464 reg = <0x0 0xff1c0000 0x0 0x100>;
465 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
469 clock-names = "baudclk", "apb_pclk";
470 pinctrl-names = "default";
471 pinctrl-0 = <&uart4_xfer>;
476 reserve_thermal: reserve_thermal {
477 polling-delay-passive = <1000>; /* milliseconds */
478 polling-delay = <5000>; /* milliseconds */
480 thermal-sensors = <&tsadc 0>;
483 cpu_thermal: cpu_thermal {
484 polling-delay-passive = <100>; /* milliseconds */
485 polling-delay = <5000>; /* milliseconds */
487 thermal-sensors = <&tsadc 1>;
490 cpu_alert0: cpu_alert0 {
491 temperature = <70000>; /* millicelsius */
492 hysteresis = <2000>; /* millicelsius */
495 cpu_alert1: cpu_alert1 {
496 temperature = <75000>; /* millicelsius */
497 hysteresis = <2000>; /* millicelsius */
501 temperature = <90000>; /* millicelsius */
502 hysteresis = <2000>; /* millicelsius */
509 trip = <&cpu_alert0>;
511 <&cpu0 THERMAL_NO_LIMIT 6>;
514 trip = <&cpu_alert1>;
516 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
521 gpu_thermal: gpu_thermal {
522 polling-delay-passive = <100>; /* milliseconds */
523 polling-delay = <5000>; /* milliseconds */
525 thermal-sensors = <&tsadc 2>;
528 gpu_alert0: gpu_alert0 {
529 temperature = <70000>; /* millicelsius */
530 hysteresis = <2000>; /* millicelsius */
534 temperature = <90000>; /* millicelsius */
535 hysteresis = <2000>; /* millicelsius */
542 trip = <&gpu_alert0>;
544 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
550 tsadc: tsadc@ff280000 {
551 compatible = "rockchip,rk3288-tsadc";
552 reg = <0x0 0xff280000 0x0 0x100>;
553 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
555 clock-names = "tsadc", "apb_pclk";
556 resets = <&cru SRST_TSADC>;
557 reset-names = "tsadc-apb";
558 pinctrl-names = "init", "default", "sleep";
559 pinctrl-0 = <&otp_gpio>;
560 pinctrl-1 = <&otp_out>;
561 pinctrl-2 = <&otp_gpio>;
562 #thermal-sensor-cells = <1>;
563 rockchip,hw-tshut-temp = <95000>;
567 gmac: ethernet@ff290000 {
568 compatible = "rockchip,rk3288-gmac";
569 reg = <0x0 0xff290000 0x0 0x10000>;
570 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
572 interrupt-names = "macirq", "eth_wake_irq";
573 rockchip,grf = <&grf>;
574 clocks = <&cru SCLK_MAC>,
575 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
576 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
577 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
578 clock-names = "stmmaceth",
579 "mac_clk_rx", "mac_clk_tx",
580 "clk_mac_ref", "clk_mac_refout",
581 "aclk_mac", "pclk_mac";
582 resets = <&cru SRST_MAC>;
583 reset-names = "stmmaceth";
587 usb_host0_ehci: usb@ff500000 {
588 compatible = "generic-ehci";
589 reg = <0x0 0xff500000 0x0 0x100>;
590 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
591 clocks = <&cru HCLK_USBHOST0>;
592 clock-names = "usbhost";
598 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
600 usb_host1: usb@ff540000 {
601 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
603 reg = <0x0 0xff540000 0x0 0x40000>;
604 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
605 clocks = <&cru HCLK_USBHOST1>;
609 phy-names = "usb2-phy";
613 usb_otg: usb@ff580000 {
614 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
616 reg = <0x0 0xff580000 0x0 0x40000>;
617 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&cru HCLK_OTG0>;
621 g-np-tx-fifo-size = <16>;
622 g-rx-fifo-size = <275>;
623 g-tx-fifo-size = <256 128 128 64 64 32>;
625 phy-names = "usb2-phy";
629 usb_hsic: usb@ff5c0000 {
630 compatible = "generic-ehci";
631 reg = <0x0 0xff5c0000 0x0 0x100>;
632 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cru HCLK_HSIC>;
634 clock-names = "usbhost";
639 compatible = "rockchip,rk3288-i2c";
640 reg = <0x0 0xff650000 0x0 0x1000>;
641 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
642 #address-cells = <1>;
645 clocks = <&cru PCLK_I2C0>;
646 pinctrl-names = "default";
647 pinctrl-0 = <&i2c0_xfer>;
652 compatible = "rockchip,rk3288-i2c";
653 reg = <0x0 0xff660000 0x0 0x1000>;
654 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
658 clocks = <&cru PCLK_I2C2>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&i2c2_xfer>;
665 compatible = "rockchip,rk3288-pwm";
666 reg = <0x0 0xff680000 0x0 0x10>;
668 pinctrl-names = "default";
669 pinctrl-0 = <&pwm0_pin>;
670 clocks = <&cru PCLK_PWM>;
676 compatible = "rockchip,rk3288-pwm";
677 reg = <0x0 0xff680010 0x0 0x10>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pwm1_pin>;
681 clocks = <&cru PCLK_PWM>;
687 compatible = "rockchip,rk3288-pwm";
688 reg = <0x0 0xff680020 0x0 0x10>;
690 pinctrl-names = "default";
691 pinctrl-0 = <&pwm2_pin>;
692 clocks = <&cru PCLK_PWM>;
698 compatible = "rockchip,rk3288-pwm";
699 reg = <0x0 0xff680030 0x0 0x10>;
701 pinctrl-names = "default";
702 pinctrl-0 = <&pwm3_pin>;
703 clocks = <&cru PCLK_PWM>;
708 bus_intmem@ff700000 {
709 compatible = "mmio-sram";
710 reg = <0x0 0xff700000 0x0 0x18000>;
711 #address-cells = <1>;
713 ranges = <0 0x0 0xff700000 0x18000>;
715 compatible = "rockchip,rk3066-smp-sram";
721 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
722 reg = <0x0 0xff720000 0x0 0x1000>;
725 pmu: power-management@ff730000 {
726 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
727 reg = <0x0 0xff730000 0x0 0x100>;
729 power: power-controller {
730 compatible = "rockchip,rk3288-power-controller";
731 #power-domain-cells = <1>;
732 #address-cells = <1>;
735 assigned-clocks = <&cru SCLK_EDP_24M>;
736 assigned-clock-parents = <&xin24m>;
739 * Note: Although SCLK_* are the working clocks
740 * of device without including on the NOC, needed for
743 * The clocks on the which NOC:
744 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
745 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
746 * ACLK_RGA is on ACLK_RGA_NIU.
747 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
749 * Which clock are device clocks:
751 * *_IEP IEP:Image Enhancement Processor
752 * *_ISP ISP:Image Signal Processing
753 * *_VIP VIP:Video Input Processor
754 * *_VOP* VOP:Visual Output Processor
761 pd_vio@RK3288_PD_VIO {
762 reg = <RK3288_PD_VIO>;
763 clocks = <&cru ACLK_IEP>,
777 <&cru PCLK_EDP_CTRL>,
778 <&cru PCLK_HDMI_CTRL>,
779 <&cru PCLK_LVDS_PHY>,
780 <&cru PCLK_MIPI_CSI>,
781 <&cru PCLK_MIPI_DSI0>,
782 <&cru PCLK_MIPI_DSI1>,
788 pm_qos = <&qos_vio0_iep>,
800 * Note: The following 3 are HEVC(H.265) clocks,
801 * and on the ACLK_HEVC_NIU (NOC).
803 pd_hevc@RK3288_PD_HEVC {
804 reg = <RK3288_PD_HEVC>;
805 clocks = <&cru ACLK_HEVC>,
806 <&cru SCLK_HEVC_CABAC>,
807 <&cru SCLK_HEVC_CORE>;
808 pm_qos = <&qos_hevc_r>,
813 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
814 * (video endecoder & decoder) clocks that on the
815 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
817 pd_video@RK3288_PD_VIDEO {
818 reg = <RK3288_PD_VIDEO>;
819 clocks = <&cru ACLK_VCODEC>,
821 pm_qos = <&qos_video>;
825 * Note: ACLK_GPU is the GPU clock,
826 * and on the ACLK_GPU_NIU (NOC).
828 pd_gpu@RK3288_PD_GPU {
829 reg = <RK3288_PD_GPU>;
830 clocks = <&cru ACLK_GPU>;
831 pm_qos = <&qos_gpu_r>,
837 compatible = "syscon-reboot-mode";
839 mode-normal = <BOOT_NORMAL>;
840 mode-recovery = <BOOT_RECOVERY>;
841 mode-bootloader = <BOOT_FASTBOOT>;
842 mode-loader = <BOOT_BL_DOWNLOAD>;
846 sgrf: syscon@ff740000 {
847 compatible = "rockchip,rk3288-sgrf", "syscon";
848 reg = <0x0 0xff740000 0x0 0x1000>;
851 cru: clock-controller@ff760000 {
852 compatible = "rockchip,rk3288-cru";
853 reg = <0x0 0xff760000 0x0 0x1000>;
854 rockchip,grf = <&grf>;
857 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
858 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
859 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
860 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
862 assigned-clock-rates = <594000000>, <400000000>,
863 <500000000>, <300000000>,
864 <150000000>, <75000000>,
865 <300000000>, <150000000>,
869 grf: syscon@ff770000 {
870 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
871 reg = <0x0 0xff770000 0x0 0x1000>;
874 compatible = "rockchip,rk3288-dp-phy";
875 clocks = <&cru SCLK_EDP_24M>;
881 io_domains: io-domains {
882 compatible = "rockchip,rk3288-io-voltage-domain";
887 compatible = "rockchip,rk3288-usb-phy";
888 #address-cells = <1>;
892 usbphy0: usb-phy@320 {
895 clocks = <&cru SCLK_OTGPHY0>;
896 clock-names = "phyclk";
900 usbphy1: usb-phy@334 {
903 clocks = <&cru SCLK_OTGPHY1>;
904 clock-names = "phyclk";
908 usbphy2: usb-phy@348 {
911 clocks = <&cru SCLK_OTGPHY2>;
912 clock-names = "phyclk";
918 wdt: watchdog@ff800000 {
919 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
920 reg = <0x0 0xff800000 0x0 0x100>;
921 clocks = <&cru PCLK_WDT>;
922 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
926 spdif: sound@ff88b0000 {
927 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
928 reg = <0x0 0xff8b0000 0x0 0x10000>;
929 #sound-dai-cells = <0>;
930 clock-names = "hclk", "mclk";
931 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
932 dmas = <&dmac_bus_s 3>;
934 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
935 pinctrl-names = "default";
936 pinctrl-0 = <&spdif_tx>;
937 rockchip,grf = <&grf>;
942 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
943 reg = <0x0 0xff890000 0x0 0x10000>;
944 #sound-dai-cells = <0>;
945 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
946 #address-cells = <1>;
948 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
949 dma-names = "tx", "rx";
950 clock-names = "i2s_hclk", "i2s_clk";
951 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
952 pinctrl-names = "default";
953 pinctrl-0 = <&i2s0_bus>;
954 rockchip,playback-channels = <8>;
955 rockchip,capture-channels = <2>;
959 crypto: cypto-controller@ff8a0000 {
960 compatible = "rockchip,rk3288-crypto";
961 reg = <0x0 0xff8a0000 0x0 0x4000>;
962 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>,
964 <&cru SCLK_CRYPTO>, <&cru ACLK_DMAC1>;
965 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
966 resets = <&cru SRST_CRYPTO>;
967 reset-names = "crypto-rst";
971 iep_mmu: iommu@ff900800 {
972 compatible = "rockchip,iommu";
973 reg = <0x0 0xff900800 0x0 0x40>;
974 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
975 interrupt-names = "iep_mmu";
976 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
977 clock-names = "aclk", "iface";
982 isp_mmu: iommu@ff914000 {
983 compatible = "rockchip,iommu";
984 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
985 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
986 interrupt-names = "isp_mmu";
987 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
988 clock-names = "aclk", "iface";
990 rockchip,disable-mmu-reset;
995 compatible = "rockchip,rk3288-rga";
996 reg = <0x0 0xff920000 0x0 0x180>;
997 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
999 clock-names = "aclk", "hclk", "sclk";
1000 power-domains = <&power RK3288_PD_VIO>;
1001 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1002 reset-names = "core", "axi", "ahb";
1005 vopb: vop@ff930000 {
1006 compatible = "rockchip,rk3288-vop";
1007 reg = <0x0 0xff930000 0x0 0x19c>;
1008 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1010 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1011 power-domains = <&power RK3288_PD_VIO>;
1012 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1013 reset-names = "axi", "ahb", "dclk";
1014 iommus = <&vopb_mmu>;
1015 status = "disabled";
1018 #address-cells = <1>;
1021 vopb_out_hdmi: endpoint@0 {
1023 remote-endpoint = <&hdmi_in_vopb>;
1026 vopb_out_edp: endpoint@1 {
1028 remote-endpoint = <&edp_in_vopb>;
1031 vopb_out_mipi: endpoint@2 {
1033 remote-endpoint = <&mipi_in_vopb>;
1036 vopb_out_lvds: endpoint@3 {
1038 remote-endpoint = <&lvds_in_vopb>;
1043 vopb_mmu: iommu@ff930300 {
1044 compatible = "rockchip,iommu";
1045 reg = <0x0 0xff930300 0x0 0x100>;
1046 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1047 interrupt-names = "vopb_mmu";
1048 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1049 clock-names = "aclk", "iface";
1050 power-domains = <&power RK3288_PD_VIO>;
1052 status = "disabled";
1055 vopl: vop@ff940000 {
1056 compatible = "rockchip,rk3288-vop";
1057 reg = <0x0 0xff940000 0x0 0x19c>;
1058 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1060 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1061 power-domains = <&power RK3288_PD_VIO>;
1062 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1063 reset-names = "axi", "ahb", "dclk";
1064 iommus = <&vopl_mmu>;
1065 status = "disabled";
1068 #address-cells = <1>;
1071 vopl_out_hdmi: endpoint@0 {
1073 remote-endpoint = <&hdmi_in_vopl>;
1076 vopl_out_edp: endpoint@1 {
1078 remote-endpoint = <&edp_in_vopl>;
1081 vopl_out_mipi: endpoint@2 {
1083 remote-endpoint = <&mipi_in_vopl>;
1086 vopl_out_lvds: endpoint@3 {
1088 remote-endpoint = <&lvds_in_vopl>;
1093 vopl_mmu: iommu@ff940300 {
1094 compatible = "rockchip,iommu";
1095 reg = <0x0 0xff940300 0x0 0x100>;
1096 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1097 interrupt-names = "vopl_mmu";
1098 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1099 clock-names = "aclk", "iface";
1100 power-domains = <&power RK3288_PD_VIO>;
1102 status = "disabled";
1105 mipi_dsi: mipi@ff960000 {
1106 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1107 reg = <0x0 0xff960000 0x0 0x4000>;
1108 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1109 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1110 clock-names = "ref", "pclk";
1111 power-domains = <&power RK3288_PD_VIO>;
1112 rockchip,grf = <&grf>;
1113 #address-cells = <1>;
1115 status = "disabled";
1119 #address-cells = <1>;
1121 mipi_in_vopb: endpoint@0 {
1123 remote-endpoint = <&vopb_out_mipi>;
1125 mipi_in_vopl: endpoint@1 {
1127 remote-endpoint = <&vopl_out_mipi>;
1133 lvds: lvds@ff96c000 {
1134 compatible = "rockchip,rk3288-lvds";
1135 reg = <0x0 0xff96c000 0x0 0x4000>;
1136 clocks = <&cru PCLK_LVDS_PHY>;
1137 clock-names = "pclk_lvds";
1138 pinctrl-names = "lcdc";
1139 pinctrl-0 = <&lcdc_ctl>;
1140 power-domains = <&power RK3288_PD_VIO>;
1141 rockchip,grf = <&grf>;
1142 status = "disabled";
1145 #address-cells = <1>;
1151 #address-cells = <1>;
1154 lvds_in_vopb: endpoint@0 {
1156 remote-endpoint = <&vopb_out_lvds>;
1158 lvds_in_vopl: endpoint@1 {
1160 remote-endpoint = <&vopl_out_lvds>;
1167 compatible = "rockchip,rk3288-dp";
1168 reg = <0x0 0xff970000 0x0 0x4000>;
1169 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1171 clock-names = "dp", "pclk";
1174 resets = <&cru SRST_EDP>;
1176 rockchip,grf = <&grf>;
1177 status = "disabled";
1180 #address-cells = <1>;
1184 #address-cells = <1>;
1186 edp_in_vopb: endpoint@0 {
1188 remote-endpoint = <&vopb_out_edp>;
1190 edp_in_vopl: endpoint@1 {
1192 remote-endpoint = <&vopl_out_edp>;
1198 hdmi: hdmi@ff980000 {
1199 compatible = "rockchip,rk3288-dw-hdmi";
1200 reg = <0x0 0xff980000 0x0 0x20000>;
1202 #sound-dai-cells = <0>;
1203 rockchip,grf = <&grf>;
1204 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1205 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
1206 clock-names = "iahb", "isfr", "cec";
1207 power-domains = <&power RK3288_PD_VIO>;
1208 status = "disabled";
1212 #address-cells = <1>;
1214 hdmi_in_vopb: endpoint@0 {
1216 remote-endpoint = <&vopb_out_hdmi>;
1218 hdmi_in_vopl: endpoint@1 {
1220 remote-endpoint = <&vopl_out_hdmi>;
1226 vpu_mmu: iommu@ff9a0800 {
1227 compatible = "rockchip,iommu";
1228 reg = <0x0 0xff9a0800 0x0 0x100>;
1229 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1230 interrupt-names = "vpu_mmu";
1231 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1232 clock-names = "aclk", "iface";
1234 status = "disabled";
1237 hevc_mmu: iommu@ff9c0440 {
1238 compatible = "rockchip,iommu";
1239 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1240 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1241 interrupt-names = "hevc_mmu";
1242 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>;
1243 clock-names = "aclk", "iface";
1245 status = "disabled";
1249 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1250 reg = <0x0 0xffa30000 0x0 0x10000>;
1251 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1254 interrupt-names = "job", "mmu", "gpu";
1255 clocks = <&cru ACLK_GPU>;
1256 operating-points-v2 = <&gpu_opp_table>;
1257 power-domains = <&power RK3288_PD_GPU>;
1258 status = "disabled";
1261 gpu_opp_table: gpu-opp-table {
1262 compatible = "operating-points-v2";
1265 opp-hz = /bits/ 64 <100000000>;
1266 opp-microvolt = <950000>;
1269 opp-hz = /bits/ 64 <200000000>;
1270 opp-microvolt = <950000>;
1273 opp-hz = /bits/ 64 <300000000>;
1274 opp-microvolt = <1000000>;
1277 opp-hz = /bits/ 64 <400000000>;
1278 opp-microvolt = <1100000>;
1281 opp-hz = /bits/ 64 <500000000>;
1282 opp-microvolt = <1200000>;
1285 opp-hz = /bits/ 64 <600000000>;
1286 opp-microvolt = <1250000>;
1290 qos_gpu_r: qos@ffaa0000 {
1291 compatible = "syscon";
1292 reg = <0x0 0xffaa0000 0x0 0x20>;
1295 qos_gpu_w: qos@ffaa0080 {
1296 compatible = "syscon";
1297 reg = <0x0 0xffaa0080 0x0 0x20>;
1300 qos_vio1_vop: qos@ffad0000 {
1301 compatible = "syscon";
1302 reg = <0x0 0xffad0000 0x0 0x20>;
1305 qos_vio1_isp_w0: qos@ffad0100 {
1306 compatible = "syscon";
1307 reg = <0x0 0xffad0100 0x0 0x20>;
1310 qos_vio1_isp_w1: qos@ffad0180 {
1311 compatible = "syscon";
1312 reg = <0x0 0xffad0180 0x0 0x20>;
1315 qos_vio0_vop: qos@ffad0400 {
1316 compatible = "syscon";
1317 reg = <0x0 0xffad0400 0x0 0x20>;
1320 qos_vio0_vip: qos@ffad0480 {
1321 compatible = "syscon";
1322 reg = <0x0 0xffad0480 0x0 0x20>;
1325 qos_vio0_iep: qos@ffad0500 {
1326 compatible = "syscon";
1327 reg = <0x0 0xffad0500 0x0 0x20>;
1330 qos_vio2_rga_r: qos@ffad0800 {
1331 compatible = "syscon";
1332 reg = <0x0 0xffad0800 0x0 0x20>;
1335 qos_vio2_rga_w: qos@ffad0880 {
1336 compatible = "syscon";
1337 reg = <0x0 0xffad0880 0x0 0x20>;
1340 qos_vio1_isp_r: qos@ffad0900 {
1341 compatible = "syscon";
1342 reg = <0x0 0xffad0900 0x0 0x20>;
1345 qos_video: qos@ffae0000 {
1346 compatible = "syscon";
1347 reg = <0x0 0xffae0000 0x0 0x20>;
1350 qos_hevc_r: qos@ffaf0000 {
1351 compatible = "syscon";
1352 reg = <0x0 0xffaf0000 0x0 0x20>;
1355 qos_hevc_w: qos@ffaf0080 {
1356 compatible = "syscon";
1357 reg = <0x0 0xffaf0080 0x0 0x20>;
1360 gic: interrupt-controller@ffc01000 {
1361 compatible = "arm,gic-400";
1362 interrupt-controller;
1363 #interrupt-cells = <3>;
1364 #address-cells = <0>;
1366 reg = <0x0 0xffc01000 0x0 0x1000>,
1367 <0x0 0xffc02000 0x0 0x2000>,
1368 <0x0 0xffc04000 0x0 0x2000>,
1369 <0x0 0xffc06000 0x0 0x2000>;
1370 interrupts = <GIC_PPI 9 0xf04>;
1373 efuse: efuse@ffb40000 {
1374 compatible = "rockchip,rk3288-efuse";
1375 reg = <0x0 0xffb40000 0x0 0x20>;
1376 #address-cells = <1>;
1378 clocks = <&cru PCLK_EFUSE256>;
1379 clock-names = "pclk_efuse";
1381 cpu_leakage: cpu_leakage@17 {
1387 compatible = "rockchip,rk3288-pinctrl";
1388 rockchip,grf = <&grf>;
1389 rockchip,pmu = <&pmu>;
1390 #address-cells = <2>;
1394 gpio0: gpio0@ff750000 {
1395 compatible = "rockchip,gpio-bank";
1396 reg = <0x0 0xff750000 0x0 0x100>;
1397 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1398 clocks = <&cru PCLK_GPIO0>;
1403 interrupt-controller;
1404 #interrupt-cells = <2>;
1407 gpio1: gpio1@ff780000 {
1408 compatible = "rockchip,gpio-bank";
1409 reg = <0x0 0xff780000 0x0 0x100>;
1410 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1411 clocks = <&cru PCLK_GPIO1>;
1416 interrupt-controller;
1417 #interrupt-cells = <2>;
1420 gpio2: gpio2@ff790000 {
1421 compatible = "rockchip,gpio-bank";
1422 reg = <0x0 0xff790000 0x0 0x100>;
1423 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1424 clocks = <&cru PCLK_GPIO2>;
1429 interrupt-controller;
1430 #interrupt-cells = <2>;
1433 gpio3: gpio3@ff7a0000 {
1434 compatible = "rockchip,gpio-bank";
1435 reg = <0x0 0xff7a0000 0x0 0x100>;
1436 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1437 clocks = <&cru PCLK_GPIO3>;
1442 interrupt-controller;
1443 #interrupt-cells = <2>;
1446 gpio4: gpio4@ff7b0000 {
1447 compatible = "rockchip,gpio-bank";
1448 reg = <0x0 0xff7b0000 0x0 0x100>;
1449 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1450 clocks = <&cru PCLK_GPIO4>;
1455 interrupt-controller;
1456 #interrupt-cells = <2>;
1459 gpio5: gpio5@ff7c0000 {
1460 compatible = "rockchip,gpio-bank";
1461 reg = <0x0 0xff7c0000 0x0 0x100>;
1462 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&cru PCLK_GPIO5>;
1468 interrupt-controller;
1469 #interrupt-cells = <2>;
1472 gpio6: gpio6@ff7d0000 {
1473 compatible = "rockchip,gpio-bank";
1474 reg = <0x0 0xff7d0000 0x0 0x100>;
1475 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1476 clocks = <&cru PCLK_GPIO6>;
1481 interrupt-controller;
1482 #interrupt-cells = <2>;
1485 gpio7: gpio7@ff7e0000 {
1486 compatible = "rockchip,gpio-bank";
1487 reg = <0x0 0xff7e0000 0x0 0x100>;
1488 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1489 clocks = <&cru PCLK_GPIO7>;
1494 interrupt-controller;
1495 #interrupt-cells = <2>;
1498 gpio8: gpio8@ff7f0000 {
1499 compatible = "rockchip,gpio-bank";
1500 reg = <0x0 0xff7f0000 0x0 0x100>;
1501 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1502 clocks = <&cru PCLK_GPIO8>;
1507 interrupt-controller;
1508 #interrupt-cells = <2>;
1512 hdmi_cec_c0: hdmi-cec-c0 {
1513 rockchip,pins = <7 RK_PC0 RK_FUNC_2 &pcfg_pull_none>;
1516 hdmi_cec_c7: hdmi-cec-c7 {
1517 rockchip,pins = <7 RK_PC7 RK_FUNC_4 &pcfg_pull_none>;
1520 hdmi_ddc: hdmi-ddc {
1521 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1522 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1526 pcfg_pull_up: pcfg-pull-up {
1530 pcfg_pull_down: pcfg-pull-down {
1534 pcfg_pull_none: pcfg-pull-none {
1538 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1540 drive-strength = <12>;
1544 global_pwroff: global-pwroff {
1545 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1548 ddrio_pwroff: ddrio-pwroff {
1549 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1552 ddr0_retention: ddr0-retention {
1553 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1556 ddr1_retention: ddr1-retention {
1557 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1563 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1568 i2c0_xfer: i2c0-xfer {
1569 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1570 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1575 i2c1_xfer: i2c1-xfer {
1576 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1577 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1582 i2c2_xfer: i2c2-xfer {
1583 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1584 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1589 i2c3_xfer: i2c3-xfer {
1590 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1591 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1596 i2c4_xfer: i2c4-xfer {
1597 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1598 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1603 i2c5_xfer: i2c5-xfer {
1604 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1605 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1610 i2s0_bus: i2s0-bus {
1611 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1612 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1613 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1614 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1615 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1616 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1621 lcdc_ctl: lcdc-ctl {
1622 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1623 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1624 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1625 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1630 sdmmc_clk: sdmmc-clk {
1631 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1634 sdmmc_cmd: sdmmc-cmd {
1635 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1638 sdmmc_cd: sdmmc-cd {
1639 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1642 sdmmc_bus1: sdmmc-bus1 {
1643 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1646 sdmmc_bus4: sdmmc-bus4 {
1647 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1648 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1649 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1650 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1655 sdio0_bus1: sdio0-bus1 {
1656 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1659 sdio0_bus4: sdio0-bus4 {
1660 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1661 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1662 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1663 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1666 sdio0_cmd: sdio0-cmd {
1667 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1670 sdio0_clk: sdio0-clk {
1671 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1674 sdio0_cd: sdio0-cd {
1675 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1678 sdio0_wp: sdio0-wp {
1679 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1682 sdio0_pwr: sdio0-pwr {
1683 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1686 sdio0_bkpwr: sdio0-bkpwr {
1687 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1690 sdio0_int: sdio0-int {
1691 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1696 sdio1_bus1: sdio1-bus1 {
1697 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1700 sdio1_bus4: sdio1-bus4 {
1701 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1702 <3 25 4 &pcfg_pull_up>,
1703 <3 26 4 &pcfg_pull_up>,
1704 <3 27 4 &pcfg_pull_up>;
1707 sdio1_cd: sdio1-cd {
1708 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1711 sdio1_wp: sdio1-wp {
1712 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1715 sdio1_bkpwr: sdio1-bkpwr {
1716 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1719 sdio1_int: sdio1-int {
1720 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1723 sdio1_cmd: sdio1-cmd {
1724 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1727 sdio1_clk: sdio1-clk {
1728 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1731 sdio1_pwr: sdio1-pwr {
1732 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1737 emmc_clk: emmc-clk {
1738 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1741 emmc_cmd: emmc-cmd {
1742 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1745 emmc_pwr: emmc-pwr {
1746 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1749 emmc_bus1: emmc-bus1 {
1750 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1753 emmc_bus4: emmc-bus4 {
1754 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1755 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1756 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1757 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1760 emmc_bus8: emmc-bus8 {
1761 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1762 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1763 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1764 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1765 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1766 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1767 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1768 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1773 spi0_clk: spi0-clk {
1774 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1776 spi0_cs0: spi0-cs0 {
1777 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1780 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1783 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1785 spi0_cs1: spi0-cs1 {
1786 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1790 spi1_clk: spi1-clk {
1791 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1793 spi1_cs0: spi1-cs0 {
1794 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1797 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1800 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1805 spi2_cs1: spi2-cs1 {
1806 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1808 spi2_clk: spi2-clk {
1809 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1811 spi2_cs0: spi2-cs0 {
1812 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1815 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1818 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1823 uart0_xfer: uart0-xfer {
1824 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1825 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1828 uart0_cts: uart0-cts {
1829 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1832 uart0_rts: uart0-rts {
1833 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1838 uart1_xfer: uart1-xfer {
1839 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1840 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1843 uart1_cts: uart1-cts {
1844 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1847 uart1_rts: uart1-rts {
1848 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1853 uart2_xfer: uart2-xfer {
1854 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1855 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1857 /* no rts / cts for uart2 */
1861 uart3_xfer: uart3-xfer {
1862 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1863 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1866 uart3_cts: uart3-cts {
1867 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1870 uart3_rts: uart3-rts {
1871 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1876 uart4_xfer: uart4-xfer {
1877 rockchip,pins = <5 15 3 &pcfg_pull_up>,
1878 <5 14 3 &pcfg_pull_none>;
1881 uart4_cts: uart4-cts {
1882 rockchip,pins = <5 12 3 &pcfg_pull_up>;
1885 uart4_rts: uart4-rts {
1886 rockchip,pins = <5 13 3 &pcfg_pull_none>;
1891 otp_gpio: otp-gpio {
1892 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1896 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1901 pwm0_pin: pwm0-pin {
1902 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1907 pwm1_pin: pwm1-pin {
1908 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1913 pwm2_pin: pwm2-pin {
1914 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1919 pwm3_pin: pwm3-pin {
1920 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1925 rgmii_pins: rgmii-pins {
1926 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1927 <3 31 3 &pcfg_pull_none>,
1928 <3 26 3 &pcfg_pull_none>,
1929 <3 27 3 &pcfg_pull_none>,
1930 <3 28 3 &pcfg_pull_none_12ma>,
1931 <3 29 3 &pcfg_pull_none_12ma>,
1932 <3 24 3 &pcfg_pull_none_12ma>,
1933 <3 25 3 &pcfg_pull_none_12ma>,
1934 <4 0 3 &pcfg_pull_none>,
1935 <4 5 3 &pcfg_pull_none>,
1936 <4 6 3 &pcfg_pull_none>,
1937 <4 9 3 &pcfg_pull_none_12ma>,
1938 <4 4 3 &pcfg_pull_none_12ma>,
1939 <4 1 3 &pcfg_pull_none>,
1940 <4 3 3 &pcfg_pull_none>;
1943 rmii_pins: rmii-pins {
1944 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1945 <3 31 3 &pcfg_pull_none>,
1946 <3 28 3 &pcfg_pull_none>,
1947 <3 29 3 &pcfg_pull_none>,
1948 <4 0 3 &pcfg_pull_none>,
1949 <4 5 3 &pcfg_pull_none>,
1950 <4 4 3 &pcfg_pull_none>,
1951 <4 1 3 &pcfg_pull_none>,
1952 <4 2 3 &pcfg_pull_none>,
1953 <4 3 3 &pcfg_pull_none>;
1958 spdif_tx: spdif-tx {
1959 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;