arch/arm/boot/dts/rk3288-veyron.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Google Veyron (and derivatives) board device tree source
   4  *
   5  * Copyright 2015 Google, Inc
   6  */
   7
   8 #include <dt-bindings/clock/rockchip,rk808.h>
   9 #include <dt-bindings/input/input.h>
  10 #include "rk3288.dtsi"
  11
  12 / {
  13         memory@0 {
  14                 device_type = "memory";
  15                 reg = <0x0 0x0 0x0 0x80000000>;
  16         };
  17
  18         gpio_keys: gpio-keys {
  19                 compatible = "gpio-keys";
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&pwr_key_l>;
  25                 power {
  26                         label = "Power";
  27                         gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
  28                         linux,code = <KEY_POWER>;
  29                         debounce-interval = <100>;
  30                         wakeup-source;
  31                 };
  32         };
  33
  34         gpio-restart {
  35                 compatible = "gpio-restart";
  36                 gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
  37                 pinctrl-names = "default";
  38                 pinctrl-0 = <&ap_warm_reset_h>;
  39                 priority = <200>;
  40         };
  41
  42         emmc_pwrseq: emmc-pwrseq {
  43                 compatible = "mmc-pwrseq-emmc";
  44                 pinctrl-0 = <&emmc_reset>;
  45                 pinctrl-names = "default";
  46                 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
  47         };
  48
  49         sdio_pwrseq: sdio-pwrseq {
  50                 compatible = "mmc-pwrseq-simple";
  51                 clocks = <&rk808 RK808_CLKOUT1>;
  52                 clock-names = "ext_clock";
  53                 pinctrl-names = "default";
  54                 pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
  55
  56                 /*
  57                  * On the module itself this is one of these (depending
  58                  * on the actual card populated):
  59                  * - SDIO_RESET_L_WL_REG_ON
  60                  * - PDN (power down when low)
  61                  */
  62                 reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
  63         };
  64
  65         vcc_5v: vcc-5v {
  66                 compatible = "regulator-fixed";
  67                 regulator-name = "vcc_5v";
  68                 regulator-always-on;
  69                 regulator-boot-on;
  70                 regulator-min-microvolt = <5000000>;
  71                 regulator-max-microvolt = <5000000>;
  72         };
  73
  74         vcc33_sys: vcc33-sys {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "vcc33_sys";
  77                 regulator-always-on;
  78                 regulator-boot-on;
  79                 regulator-min-microvolt = <3300000>;
  80                 regulator-max-microvolt = <3300000>;
  81         };
  82
  83         vcc50_hdmi: vcc50-hdmi {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "vcc50_hdmi";
  86                 regulator-always-on;
  87                 regulator-boot-on;
  88                 vin-supply = <&vcc_5v>;
  89         };
  90 };
  91
  92 &cpu0 {
  93         cpu0-supply = <&vdd_cpu>;
  94 };
  95
  96 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
  97 &cpu_opp_table {
  98         /delete-node/ opp-312000000;
  99
 100         opp-1512000000 {
 101                 opp-microvolt = <1250000>;
 102         };
 103         opp-1608000000 {
 104                 opp-microvolt = <1300000>;
 105         };
 106         opp-1704000000 {
 107                 opp-hz = /bits/ 64 <1704000000>;
 108                 opp-microvolt = <1350000>;
 109         };
 110         opp-1800000000 {
 111                 opp-hz = /bits/ 64 <1800000000>;
 112                 opp-microvolt = <1400000>;
 113         };
 114 };
 115
 116 &emmc {
 117         status = "okay";
 118
 119         bus-width = <8>;
 120         cap-mmc-highspeed;
 121         rockchip,default-sample-phase = <158>;
 122         disable-wp;
 123         mmc-hs200-1_8v;
 124         mmc-pwrseq = <&emmc_pwrseq>;
 125         non-removable;
 126         pinctrl-names = "default";
 127         pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 128 };
 129
 130 &gpu {
 131         mali-supply = <&vdd_gpu>;
 132         status = "okay";
 133 };
 134
 135 &hdmi {
 136         ddc-i2c-bus = <&i2c5>;
 137         status = "okay";
 138 };
 139
 140 &i2c0 {
 141         status = "okay";
 142
 143         clock-frequency = <400000>;
 144         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 145         i2c-scl-rising-time-ns = <100>;         /* 45ns measured */
 146
 147         rk808: pmic@1b {
 148                 compatible = "rockchip,rk808";
 149                 reg = <0x1b>;
 150                 clock-output-names = "xin32k", "wifibt_32kin";
 151                 interrupt-parent = <&gpio0>;
 152                 interrupts = <RK_PA4 IRQ_TYPE_LEVEL_LOW>;
 153                 pinctrl-names = "default";
 154                 pinctrl-0 = <&pmic_int_l>;
 155                 rockchip,system-power-controller;
 156                 wakeup-source;
 157                 #clock-cells = <1>;
 158
 159                 vcc1-supply = <&vcc33_sys>;
 160                 vcc2-supply = <&vcc33_sys>;
 161                 vcc3-supply = <&vcc33_sys>;
 162                 vcc4-supply = <&vcc33_sys>;
 163                 vcc6-supply = <&vcc_5v>;
 164                 vcc7-supply = <&vcc33_sys>;
 165                 vcc8-supply = <&vcc33_sys>;
 166                 vcc12-supply = <&vcc_18>;
 167                 vddio-supply = <&vcc33_io>;
 168
 169                 regulators {
 170                         vdd_cpu: DCDC_REG1 {
 171                                 regulator-name = "vdd_arm";
 172                                 regulator-always-on;
 173                                 regulator-boot-on;
 174                                 regulator-min-microvolt = <750000>;
 175                                 regulator-max-microvolt = <1450000>;
 176                                 regulator-ramp-delay = <6001>;
 177                                 regulator-state-mem {
 178                                         regulator-off-in-suspend;
 179                                 };
 180                         };
 181
 182                         vdd_gpu: DCDC_REG2 {
 183                                 regulator-name = "vdd_gpu";
 184                                 regulator-always-on;
 185                                 regulator-boot-on;
 186                                 regulator-min-microvolt = <800000>;
 187                                 regulator-max-microvolt = <1250000>;
 188                                 regulator-ramp-delay = <6001>;
 189                                 regulator-state-mem {
 190                                         regulator-on-in-suspend;
 191                                         regulator-suspend-microvolt = <1000000>;
 192                                 };
 193                         };
 194
 195                         vcc135_ddr: DCDC_REG3 {
 196                                 regulator-name = "vcc135_ddr";
 197                                 regulator-always-on;
 198                                 regulator-boot-on;
 199                                 regulator-state-mem {
 200                                         regulator-on-in-suspend;
 201                                 };
 202                         };
 203
 204                         /*
 205                          * vcc_18 has several aliases.  (vcc18_flashio and
 206                          * vcc18_wl).  We'll add those aliases here just to
 207                          * make it easier to follow the schematic.  The signals
 208                          * are actually hooked together and only separated for
 209                          * power measurement purposes).
 210                          */
 211                         vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
 212                                 regulator-name = "vcc_18";
 213                                 regulator-always-on;
 214                                 regulator-boot-on;
 215                                 regulator-min-microvolt = <1800000>;
 216                                 regulator-max-microvolt = <1800000>;
 217                                 regulator-state-mem {
 218                                         regulator-on-in-suspend;
 219                                         regulator-suspend-microvolt = <1800000>;
 220                                 };
 221                         };
 222
 223                         /*
 224                          * Note that both vcc33_io and vcc33_pmuio are always
 225                          * powered together. To simplify the logic in the dts
 226                          * we just refer to vcc33_io every time something is
 227                          * powered from vcc33_pmuio. In fact, on later boards
 228                          * (such as danger) they're the same net.
 229                          */
 230                         vcc33_io: LDO_REG1 {
 231                                 regulator-name = "vcc33_io";
 232                                 regulator-always-on;
 233                                 regulator-boot-on;
 234                                 regulator-min-microvolt = <3300000>;
 235                                 regulator-max-microvolt = <3300000>;
 236                                 regulator-state-mem {
 237                                         regulator-on-in-suspend;
 238                                         regulator-suspend-microvolt = <3300000>;
 239                                 };
 240                         };
 241
 242                         vdd_10: LDO_REG3 {
 243                                 regulator-name = "vdd_10";
 244                                 regulator-always-on;
 245                                 regulator-boot-on;
 246                                 regulator-min-microvolt = <1000000>;
 247                                 regulator-max-microvolt = <1000000>;
 248                                 regulator-state-mem {
 249                                         regulator-on-in-suspend;
 250                                         regulator-suspend-microvolt = <1000000>;
 251                                 };
 252                         };
 253
 254                         vdd10_lcd_pwren_h: LDO_REG7 {
 255                                 regulator-name = "vdd10_lcd_pwren_h";
 256                                 regulator-always-on;
 257                                 regulator-boot-on;
 258                                 regulator-min-microvolt = <2500000>;
 259                                 regulator-max-microvolt = <2500000>;
 260                                 regulator-state-mem {
 261                                         regulator-off-in-suspend;
 262                                 };
 263                         };
 264
 265                         vcc33_lcd: SWITCH_REG1 {
 266                                 regulator-name = "vcc33_lcd";
 267                                 regulator-always-on;
 268                                 regulator-boot-on;
 269                                 regulator-state-mem {
 270                                         regulator-off-in-suspend;
 271                                 };
 272                         };
 273                 };
 274         };
 275 };
 276
 277 &i2c1 {
 278         status = "okay";
 279
 280         clock-frequency = <400000>;
 281         i2c-scl-falling-time-ns = <50>;         /* 2.5ns measured */
 282         i2c-scl-rising-time-ns = <100>;         /* 40ns measured */
 283
 284         tpm: tpm@20 {
 285                 compatible = "infineon,slb9645tt";
 286                 reg = <0x20>;
 287                 powered-while-suspended;
 288         };
 289 };
 290
 291 &i2c2 {
 292         status = "okay";
 293
 294         /* 100kHz since 4.7k resistors don't rise fast enough */
 295         clock-frequency = <100000>;
 296         i2c-scl-falling-time-ns = <50>;         /* 10ns measured */
 297         i2c-scl-rising-time-ns = <800>;         /* 600ns measured */
 298 };
 299
 300 &i2c4 {
 301         status = "okay";
 302
 303         clock-frequency = <400000>;
 304         i2c-scl-falling-time-ns = <50>;         /* 11ns measured */
 305         i2c-scl-rising-time-ns = <300>;         /* 225ns measured */
 306 };
 307
 308 &i2c5 {
 309         status = "okay";
 310
 311         clock-frequency = <100000>;
 312         i2c-scl-falling-time-ns = <300>;
 313         i2c-scl-rising-time-ns = <1000>;
 314 };
 315
 316 &io_domains {
 317         status = "okay";
 318
 319         bb-supply = <&vcc33_io>;
 320         dvp-supply = <&vcc_18>;
 321         flash0-supply = <&vcc18_flashio>;
 322         gpio1830-supply = <&vcc33_io>;
 323         gpio30-supply = <&vcc33_io>;
 324         lcdc-supply = <&vcc33_lcd>;
 325         wifi-supply = <&vcc18_wl>;
 326 };
 327
 328 &pwm1 {
 329         status = "okay";
 330 };
 331
 332 &sdio0 {
 333         status = "okay";
 334
 335         bus-width = <4>;
 336         cap-sd-highspeed;
 337         cap-sdio-irq;
 338         keep-power-in-suspend;
 339         mmc-pwrseq = <&sdio_pwrseq>;
 340         non-removable;
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
 343         sd-uhs-sdr12;
 344         sd-uhs-sdr25;
 345         sd-uhs-sdr50;
 346         sd-uhs-sdr104;
 347         vmmc-supply = <&vcc33_sys>;
 348         vqmmc-supply = <&vcc18_wl>;
 349 };
 350
 351 &spi2 {
 352         status = "okay";
 353
 354         rx-sample-delay-ns = <12>;
 355
 356         flash@0 {
 357                 compatible = "jedec,spi-nor";
 358                 spi-max-frequency = <50000000>;
 359                 reg = <0>;
 360         };
 361 };
 362
 363 &tsadc {
 364         status = "okay";
 365
 366         rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
 367         rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
 368 };
 369
 370 &uart0 {
 371         status = "okay";
 372
 373         /* We need to go faster than 24MHz, so adjust clock parents / rates */
 374         assigned-clocks = <&cru SCLK_UART0>;
 375         assigned-clock-rates = <48000000>;
 376
 377         /* Pins don't include flow control by default; add that in */
 378         pinctrl-names = "default";
 379         pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 380 };
 381
 382 &uart1 {
 383         status = "okay";
 384 };
 385
 386 &uart2 {
 387         status = "okay";
 388 };
 389
 390 &usbphy {
 391         status = "okay";
 392 };
 393
 394 &usb_host0_ehci {
 395         status = "okay";
 396
 397         needs-reset-on-resume;
 398 };
 399
 400 &usb_host1 {
 401         status = "okay";
 402 };
 403
 404 &usb_otg {
 405         status = "okay";
 406
 407         assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
 408         assigned-clock-parents = <&usbphy0>;
 409         dr_mode = "host";
 410 };
 411
 412 &vopb {
 413         status = "okay";
 414 };
 415
 416 &vopb_mmu {
 417         status = "okay";
 418 };
 419
 420 &wdt {
 421         status = "okay";
 422 };
 423
 424 &pinctrl {
 425         pinctrl-names = "default", "sleep";
 426         pinctrl-0 = <
 427                 /* Common for sleep and wake, but no owners */
 428                 &global_pwroff
 429         >;
 430         pinctrl-1 = <
 431                 /* Common for sleep and wake, but no owners */
 432                 &global_pwroff
 433         >;
 434
 435         pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 436                 bias-disable;
 437                 drive-strength = <8>;
 438         };
 439
 440         pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 441                 bias-pull-up;
 442                 drive-strength = <8>;
 443         };
 444
 445         pcfg_output_high: pcfg-output-high {
 446                 output-high;
 447         };
 448
 449         pcfg_output_low: pcfg-output-low {
 450                 output-low;
 451         };
 452
 453         buttons {
 454                 pwr_key_l: pwr-key-l {
 455                         rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
 456                 };
 457         };
 458
 459         emmc {
 460                 emmc_reset: emmc-reset {
 461                         rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
 462                 };
 463
 464                 /*
 465                  * We run eMMC at max speed; bump up drive strength.
 466                  * We also have external pulls, so disable the internal ones.
 467                  */
 468                 emmc_clk: emmc-clk {
 469                         rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 470                 };
 471
 472                 emmc_cmd: emmc-cmd {
 473                         rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 474                 };
 475
 476                 emmc_bus8: emmc-bus8 {
 477                         rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 478                                         <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 479                                         <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 480                                         <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 481                                         <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 482                                         <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 483                                         <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
 484                                         <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 485                 };
 486         };
 487
 488         pmic {
 489                 pmic_int_l: pmic-int-l {
 490                         rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
 491                 };
 492         };
 493
 494         reboot {
 495                 ap_warm_reset_h: ap-warm-reset-h {
 496                         rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
 497                 };
 498         };
 499
 500         recovery-switch {
 501                 rec_mode_l: rec-mode-l {
 502                         rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
 503                 };
 504         };
 505
 506         sdio0 {
 507                 wifi_enable_h: wifienable-h {
 508                         rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
 509                 };
 510
 511                 /* NOTE: mislabelled on schematic; should be bt_enable_h */
 512                 bt_enable_l: bt-enable-l {
 513                         rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
 514                 };
 515
 516                 /*
 517                  * We run sdio0 at max speed; bump up drive strength.
 518                  * We also have external pulls, so disable the internal ones.
 519                  */
 520                 sdio0_bus4: sdio0-bus4 {
 521                         rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 522                                         <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 523                                         <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
 524                                         <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 525                 };
 526
 527                 sdio0_cmd: sdio0-cmd {
 528                         rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 529                 };
 530
 531                 sdio0_clk: sdio0-clk {
 532                         rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
 533                 };
 534         };
 535
 536         tpm {
 537                 tpm_int_h: tpm-int-h {
 538                         rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
 539                 };
 540         };
 541
 542         write-protect {
 543                 fw_wp_ap: fw-wp-ap {
 544                         rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
 545                 };
 546         };
 547 };