1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Veyron Speedy Rev 1+ board device tree source
5 * Copyright 2015 Google, Inc
9 #include "rk3288-veyron-chromebook.dtsi"
10 #include "cros-ec-sbs.dtsi"
13 model = "Google Speedy";
14 compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
15 "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
16 "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
17 "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
18 "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
20 panel_regulator: panel-regulator {
21 compatible = "regulator-fixed";
23 gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
24 pinctrl-names = "default";
25 pinctrl-0 = <&lcd_enable_h>;
26 regulator-name = "panel_regulator";
27 startup-delay-us = <100000>;
28 vin-supply = <&vcc33_sys>;
31 vcc18_lcd: vcc18-lcd {
32 compatible = "regulator-fixed";
34 gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&avdd_1v8_disp_en>;
37 regulator-name = "vcc18_lcd";
40 vin-supply = <&vcc18_wl>;
43 backlight_regulator: backlight-regulator {
44 compatible = "regulator-fixed";
46 gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&bl_pwr_en>;
49 regulator-name = "backlight_regulator";
50 vin-supply = <&vcc33_sys>;
51 startup-delay-us = <15000>;
56 power-supply = <&backlight_regulator>;
60 temperature = <65000>;
64 temperature = <70000>;
68 temperature = <90000>;
72 /delete-property/pinctrl-names;
73 /delete-property/pinctrl-0;
79 temperature = <80000>;
83 temperature = <90000>;
87 power-supply= <&panel_regulator>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pmic_int_l>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
104 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&drv_5v>;
111 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
112 pinctrl-names = "default";
113 pinctrl-0 = <&vcc50_hdmi_en>;
117 gpio-line-names = "PMIC_SLEEP_AP",
128 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
145 gpio-line-names = "CONFIG0",
163 gpio-line-names = "FLASH0_D0",
181 "FLASH0_CS2/EMMC_CMD",
183 "FLASH0_DQS/EMMC_CLKO";
187 gpio-line-names = "",
225 gpio-line-names = "",
250 gpio-line-names = "I2S0_SCLK",
256 "ALS_INT", /* not connected */
277 gpio-line-names = "LCDC_BL",
284 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
310 gpio-line-names = "RAM_ID0",
325 bl_pwr_en: bl_pwr_en {
326 rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
332 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
337 vcc50_hdmi_en: vcc50-hdmi-en {
338 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
343 lcd_enable_h: lcd-en {
344 rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
347 avdd_1v8_disp_en: avdd-1v8-disp-en {
348 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
354 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
358 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;